drm/i915/icl: WaDisableCleanEvicts

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
v6:
  - Rebased
  - C, not lisp (Chris)

References: HSDES#1405733216
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-7-git-send-email-oscar.mateo@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7fe505ce5888a04688e1ccbaf52139fcf4fa0803..a7bd739fde8231d19a043ed6c7cc7847dfe32865 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7232,8 +7232,9 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE       (1<<27)
 
 #define GEN8_L3SQCREG4                         _MMIO(0xb118)
-#define  GEN8_LQSC_RO_PERF_DIS                 (1<<27)
-#define  GEN8_LQSC_FLUSH_COHERENT_LINES                (1<<21)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE                (1 << 6)
+#define  GEN8_LQSC_RO_PERF_DIS                 (1 << 27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES                (1 << 21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0                           _MMIO(0x7300)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2561c55043c58bc8425906e48a6f38c2e1b99e07..7e8bcc2ae091625db3bd1b36427d9044fc88c48b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -720,6 +720,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
        I915_WRITE(GEN11_GACB_PERF_CTRL,
                   (I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
                   GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+
+       /* Wa_1405733216:icl
+        * Formerly known as WaDisableCleanEvicts
+        */
+       I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+                                  GEN11_LQSC_CLEAN_EVICT_DISABLE);
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)