Merge master.kernel.org:/home/rmk/linux-2.6-arm
authorLinus Torvalds <torvalds@linux-foundation.org>
Tue, 13 Apr 2010 01:37:34 +0000 (18:37 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Tue, 13 Apr 2010 01:37:34 +0000 (18:37 -0700)
* master.kernel.org:/home/rmk/linux-2.6-arm: (21 commits)
  ARM: Fix ioremap_cached()/ioremap_wc() for SMP platforms
  ARM: 6043/1: AT91 slow-clock resume: Don't wait for a disabled PLL to lock
  ARM: 6031/1: fix Thumb-2 decompressor
  ARM: 6029/1: ep93xx: gpio.c: local functions should be static
  ARM: 6028/1: ARM: add MAINTAINERS for U300
  ARM: 6024/1: bcmring: fix missing down on semaphore in dma.c
  MXC: mach_armadillo5x0: Add USB Host support.
  ARM mach-mx3: duplicated include
  ARM mach-mx3: duplicated include
  imx31: add watchdog device on litekit board.
  imx3: Add watchdog platform device support
  MXC: mach-mx31_3ds: add support for freescale mc13783 power management device.
  MXC: mach-mx31_3ds: Add SPI1 device support.
  MXC: mach-mx31_3ds: Add support for on board NAND Flash.
  MXC: mach-mx31_3ds: Update variable names over recent mach name modification.
  imx31: fix parent clock for rtc
  i.MX51: remove NFC AXI static mapping
  i.MX51: determine silicon revision dynamically
  i.MX51: map TZIC dynamically
  i.MX51: Use correct clock for gpt
  ...

20 files changed:
MAINTAINERS
arch/arm/boot/compressed/head.S
arch/arm/mach-at91/pm_slowclock.S
arch/arm/mach-bcmring/dma.c
arch/arm/mach-ep93xx/gpio.c
arch/arm/mach-mx3/Kconfig
arch/arm/mach-mx3/clock-imx31.c
arch/arm/mach-mx3/devices.c
arch/arm/mach-mx3/devices.h
arch/arm/mach-mx3/mach-armadillo5x0.c
arch/arm/mach-mx3/mach-mx31_3ds.c
arch/arm/mach-mx3/mach-pcm037.c
arch/arm/mach-mx3/mx31lite-db.c
arch/arm/mach-mx5/clock-mx51.c
arch/arm/mach-mx5/cpu.c
arch/arm/mach-mx5/mm.c
arch/arm/mm/mmu.c
arch/arm/plat-mxc/include/mach/board-mx31_3ds.h [moved from arch/arm/plat-mxc/include/mach/board-mx31pdk.h with 93% similarity]
arch/arm/plat-mxc/include/mach/mx51.h
arch/arm/plat-mxc/include/mach/uncompress.h

index 7a9ccda2a3070183af6f19e361181ed2bc1bade2..5b422908d0f3dafc2ffda2624e8e9b4a9b53d5bf 100644 (file)
@@ -971,6 +971,16 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:     http://www.mcuos.com
 S:     Maintained
 
+ARM/U300 MACHINE SUPPORT
+M:     Linus Walleij <linus.walleij@stericsson.com>
+L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:     Supported
+F:     arch/arm/mach-u300/
+F:     drivers/i2c/busses/i2c-stu300.c
+F:     drivers/rtc/rtc-coh901331.c
+F:     drivers/watchdog/coh901327_wdt.c
+F:     drivers/dma/coh901318*
+
 ARM/U8500 ARM ARCHITECTURE
 M:     Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
index 0f23009170a1ae1b961e0f66d39ae2410f8f2566..6ab6b337a913c67f7951fdf0623ac87efd168b1d 100644 (file)
@@ -172,7 +172,7 @@ not_angel:
                adr     r0, LC0
  ARM(          ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
  THUMB(                ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip}   )
- THUMB(                ldr     sp, [r0, #28]                           )
+ THUMB(                ldr     sp, [r0, #32]                           )
                subs    r0, r0, r1              @ calculate the delta offset
 
                                                @ if delta is zero, we are
index 987fab3d846a539441f3fbe435042d28b19bfd10..9fcbd6ca0090b1f177f7fedfe78be21a74275bc8 100644 (file)
@@ -205,13 +205,25 @@ ENTRY(at91_slow_clock)
        ldr     r3, .saved_pllbr
        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
 
+       tst     r3, #(AT91_PMC_MUL &  0xff0000)
+       bne     1f
+       tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+       beq     2f
+1:
        wait_pllblock
+2:
 
        /* Restore PLLA setting */
        ldr     r3, .saved_pllar
        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
 
+       tst     r3, #(AT91_PMC_MUL &  0xff0000)
+       bne     3f
+       tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+       beq     4f
+3:
        wait_pllalock
+4:
 
 #ifdef SLOWDOWN_MASTER_CLOCK
        /*
index 2ccf670ce1ac2601b826a761354782c4befde8e9..29c0a911df262f6d70b5c369afa4788c44f0c07a 100644 (file)
@@ -2221,11 +2221,15 @@ EXPORT_SYMBOL(dma_map_create_descriptor_ring);
 int dma_unmap(DMA_MemMap_t *memMap,    /* Stores state information about the map */
              int dirtied       /* non-zero if any of the pages were modified */
     ) {
+
+       int rc = 0;
        int regionIdx;
        int segmentIdx;
        DMA_Region_t *region;
        DMA_Segment_t *segment;
 
+       down(&memMap->lock);
+
        for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
                region = &memMap->region[regionIdx];
 
@@ -2239,7 +2243,8 @@ int dma_unmap(DMA_MemMap_t *memMap,       /* Stores state information about the map */
                                        printk(KERN_ERR
                                               "%s: vmalloc'd pages are not yet supported\n",
                                               __func__);
-                                       return -EINVAL;
+                                       rc = -EINVAL;
+                                       goto out;
                                }
 
                        case DMA_MEM_TYPE_KMALLOC:
@@ -2276,7 +2281,8 @@ int dma_unmap(DMA_MemMap_t *memMap,       /* Stores state information about the map */
                                        printk(KERN_ERR
                                               "%s: Unsupported memory type: %d\n",
                                               __func__, region->memType);
-                                       return -EINVAL;
+                                       rc = -EINVAL;
+                                       goto out;
                                }
                        }
 
@@ -2314,9 +2320,10 @@ int dma_unmap(DMA_MemMap_t *memMap,      /* Stores state information about the map */
        memMap->numRegionsUsed = 0;
        memMap->inUse = 0;
 
+out:
        up(&memMap->lock);
 
-       return 0;
+       return rc;
 }
 
 EXPORT_SYMBOL(dma_unmap);
index cc377ae8c4281324926f6d8f9c6ac645cd53b487..cf547ad7ebd441737fb3e6a47983c1d4643c090f 100644 (file)
@@ -25,7 +25,7 @@
 #include <mach/hardware.h>
 
 /*************************************************************************
- * GPIO handling for EP93xx
+ * Interrupt handling for EP93xx on-chip GPIOs
  *************************************************************************/
 static unsigned char gpio_int_unmasked[3];
 static unsigned char gpio_int_enabled[3];
@@ -40,7 +40,7 @@ static const u8 eoi_register_offset[3]                = { 0x98, 0xb4, 0x54 };
 static const u8 int_en_register_offset[3]      = { 0x9c, 0xb8, 0x58 };
 static const u8 int_debounce_register_offset[3]        = { 0xa8, 0xc4, 0x64 };
 
-void ep93xx_gpio_update_int_params(unsigned port)
+static void ep93xx_gpio_update_int_params(unsigned port)
 {
        BUG_ON(port > 2);
 
@@ -56,7 +56,7 @@ void ep93xx_gpio_update_int_params(unsigned port)
                EP93XX_GPIO_REG(int_en_register_offset[port]));
 }
 
-void ep93xx_gpio_int_mask(unsigned line)
+static inline void ep93xx_gpio_int_mask(unsigned line)
 {
        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
 }
index 3872af1cf2c322a7ac9494b31e6fbd06513bf68d..170f68e46dd5caceb5bd83bb000e5eaf846e538a 100644 (file)
@@ -62,6 +62,15 @@ config MACH_MX31_3DS
          Include support for MX31PDK (3DS) platform. This includes specific
          configurations for the board and its peripherals.
 
+config MACH_MX31_3DS_MXC_NAND_USE_BBT
+       bool "Make the MXC NAND driver use the in flash Bad Block Table"
+       depends on MACH_MX31_3DS
+       depends on MTD_NAND_MXC
+       help
+         Enable this if you want that the MXC NAND driver uses the in flash
+         Bad Block Table to know what blocks are bad instead of scanning the
+         entire flash looking for bad block markers.
+
 config MACH_MX31MOBOARD
        bool "Support mx31moboard platforms (EPFL Mobots group)"
        select ARCH_MX31
@@ -95,6 +104,7 @@ config MACH_PCM043
 config MACH_ARMADILLO5X0
        bool "Support Atmark Armadillo-500 Development Base Board"
        select ARCH_MX31
+       select MXC_ULPI if USB_ULPI
        help
          Include support for Atmark Armadillo-500 platform. This includes
          specific configurations for the board and its peripherals.
index 80dba9966b5e54a1f3d40bd5fbe82b3071b13772..9a9eb6de6127efd0b7a6241a17a5f9d88b4e09e1 100644 (file)
@@ -468,6 +468,7 @@ static struct clk ahb_clk = {
        }
 
 DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 
 DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
@@ -490,7 +491,7 @@ DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
 DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
 DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
 DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
-DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ckil_clk);
 DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
 DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
@@ -514,7 +515,6 @@ DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk)
 DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
 DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c) \
        { \
@@ -572,7 +572,6 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "iim", iim_clk)
        _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
        _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
-       _REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
 };
 
 int __init mx31_clocks_init(unsigned long fref)
index 6adb586515ea5412d7e1223c1768a59cf91237a9..f8911154a9fa8cac1badb0ab45c6265675d93a92 100644 (file)
@@ -575,11 +575,26 @@ struct platform_device imx_ssi_device1 = {
        .resource = imx_ssi_resources1,
 };
 
-static int mx3_devices_init(void)
+static struct resource imx_wdt_resources[] = {
+       {
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+struct platform_device imx_wdt_device0 = {
+       .name           = "imx-wdt",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(imx_wdt_resources),
+       .resource       = imx_wdt_resources,
+};
+
+static int __init mx3_devices_init(void)
 {
        if (cpu_is_mx31()) {
                mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
                mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
+               imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
+               imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
                mxc_register_device(&mxc_rnga_device, NULL);
        }
        if (cpu_is_mx35()) {
@@ -597,6 +612,8 @@ static int mx3_devices_init(void)
                imx_ssi_resources0[1].end = MX35_INT_SSI1;
                imx_ssi_resources1[1].start = MX35_INT_SSI2;
                imx_ssi_resources1[1].end = MX35_INT_SSI2;
+               imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
+               imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
        }
 
        return 0;
index 42cf175eac6bb8c141b668fab316eb8ec45c7234..4f77eb501274c0fcf5406252d158641de3efd159 100644 (file)
@@ -25,4 +25,5 @@ extern struct platform_device mxc_spi_device1;
 extern struct platform_device mxc_spi_device2;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
-
+extern struct platform_device imx_ssi_device1;
+extern struct platform_device imx_wdt_device0;
index 3d72b0b89705991118d2282a943e1144c28c8a5e..5f72ec91af2d62c97acbdff70fbccd4988c292b5 100644 (file)
@@ -36,6 +36,9 @@
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <linux/i2c.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -52,6 +55,8 @@
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
 #include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 
 #include "devices.h"
 #include "crm_regs.h"
@@ -103,8 +108,158 @@ static int armadillo5x0_pins[] = {
        /* I2C2 */
        MX31_PIN_CSPI2_MOSI__SCL,
        MX31_PIN_CSPI2_MISO__SDA,
+       /* OTG */
+       MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+       MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+       MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+       MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+       MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+       MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+       MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+       MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+       MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+       MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+       MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+       MX31_PIN_USBOTG_STP__USBOTG_STP,
+       /* USB host 2 */
+       IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
+       IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
 };
 
+/* USB */
+#if defined(CONFIG_USB_ULPI)
+
+#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
+#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
+#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                       PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int usbotg_init(struct platform_device *pdev)
+{
+       int err;
+
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+       /* Chip already enabled by hardware */
+       /* OTG phy reset*/
+       err = gpio_request(OTG_RESET, "USB-OTG-RESET");
+       if (err) {
+               pr_err("Failed to request the usb otg reset gpio\n");
+               return err;
+       }
+
+       err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
+       if (err) {
+               pr_err("Failed to reset the usb otg phy\n");
+               goto otg_free_reset;
+       }
+
+       gpio_set_value(OTG_RESET, 0/*LOW*/);
+       mdelay(5);
+       gpio_set_value(OTG_RESET, 1/*HIGH*/);
+
+       return 0;
+
+otg_free_reset:
+       gpio_free(OTG_RESET);
+       return err;
+}
+
+static int usbh2_init(struct platform_device *pdev)
+{
+       int err;
+
+       mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+       mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+
+       mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+
+
+       /* Enable the chip */
+       err = gpio_request(USBH2_CS, "USB-H2-CS");
+       if (err) {
+               pr_err("Failed to request the usb host 2 CS gpio\n");
+               return err;
+       }
+
+       err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
+       if (err) {
+               pr_err("Failed to drive the usb host 2 CS gpio\n");
+               goto h2_free_cs;
+       }
+
+       /* H2 phy reset*/
+       err = gpio_request(USBH2_RESET, "USB-H2-RESET");
+       if (err) {
+               pr_err("Failed to request the usb host 2 reset gpio\n");
+               goto h2_free_cs;
+       }
+
+       err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
+       if (err) {
+               pr_err("Failed to reset the usb host 2 phy\n");
+               goto h2_free_reset;
+       }
+
+       gpio_set_value(USBH2_RESET, 0/*LOW*/);
+       mdelay(5);
+       gpio_set_value(USBH2_RESET, 1/*HIGH*/);
+
+       return 0;
+
+h2_free_reset:
+       gpio_free(USBH2_RESET);
+h2_free_cs:
+       gpio_free(USBH2_CS);
+       return err;
+}
+
+static struct mxc_usbh_platform_data usbotg_pdata = {
+       .init   = usbotg_init,
+       .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+       .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+       .init   = usbh2_init,
+       .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+       .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+#endif /* CONFIG_USB_ULPI */
+
 /* RTC over I2C*/
 #define ARMADILLO5X0_RTC_GPIO  IOMUX_TO_GPIO(MX31_PIN_SRXD4)
 
@@ -393,6 +548,17 @@ static void __init armadillo5x0_init(void)
        if (armadillo5x0_i2c_rtc.irq == 0)
                pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
        i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
+
+       /* USB */
+#if defined(CONFIG_USB_ULPI)
+       usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                       USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+       usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                       USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+       mxc_register_device(&mxc_otg_host, &usbotg_pdata);
+       mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
 }
 
 static void __init armadillo5x0_timer_init(void)
index b88c18ad769819ba86852c02a97eb74e088203d2..f54af1e29ca48a9dfcb142887d5f85d1b770e6b6 100644 (file)
@@ -23,6 +23,9 @@
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/machine.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31pdk.h>
+#include <mach/board-mx31_3ds.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/mxc_nand.h>
+#include <mach/spi.h>
 #include "devices.h"
 
 /*!
- * @file mx31pdk.c
+ * @file mx31_3ds.c
  *
  * @brief This file contains the board-specific initialization routines.
  *
  * @ingroup System
  */
 
-static int mx31pdk_pins[] = {
+static int mx31_3ds_pins[] = {
        /* UART1 */
        MX31_PIN_CTS1__CTS1,
        MX31_PIN_RTS1__RTS1,
        MX31_PIN_TXD1__TXD1,
        MX31_PIN_RXD1__RXD1,
        IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
+       /* SPI 1 */
+       MX31_PIN_CSPI2_SCLK__SCLK,
+       MX31_PIN_CSPI2_MOSI__MOSI,
+       MX31_PIN_CSPI2_MISO__MISO,
+       MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+       MX31_PIN_CSPI2_SS0__SS0,
+       MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
+       /* MC13783 IRQ */
+       IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
+};
+
+/* Regulators */
+static struct regulator_init_data pwgtx_init = {
+       .constraints = {
+               .boot_on        = 1,
+               .always_on      = 1,
+       },
+};
+
+static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
+       {
+               .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
+               .init_data = &pwgtx_init,
+       }, {
+               .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
+               .init_data = &pwgtx_init,
+       },
+};
+
+/* MC13783 */
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+       .regulators = mx31_3ds_regulators,
+       .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
+       .flags  = MC13783_USE_REGULATOR,
+};
+
+/* SPI */
+static int spi1_internal_chipselect[] = {
+       MXC_SPI_CS(0),
+       MXC_SPI_CS(2),
+};
+
+static struct spi_imx_master spi1_pdata = {
+       .chipselect     = spi1_internal_chipselect,
+       .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
+};
+
+static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
+       {
+               .modalias       = "mc13783",
+               .max_speed_hz   = 1000000,
+               .bus_num        = 1,
+               .chip_select    = 1, /* SS2 */
+               .platform_data  = &mc13783_pdata,
+               .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+               .mode = SPI_CS_HIGH,
+       },
+};
+
+/*
+ * NAND Flash
+ */
+static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
+       .width          = 1,
+       .hw_ecc         = 1,
+#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
+       .flash_bbt      = 1,
+#endif
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -95,7 +168,7 @@ static struct platform_device smsc911x_device = {
  * LEDs, switches, interrupts for Ethernet.
  */
 
-static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
+static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
 {
        uint32_t imr_val;
        uint32_t int_valid;
@@ -163,7 +236,7 @@ static struct irq_chip expio_irq_chip = {
        .unmask = expio_unmask_irq,
 };
 
-static int __init mx31pdk_init_expio(void)
+static int __init mx31_3ds_init_expio(void)
 {
        int i;
        int ret;
@@ -176,7 +249,7 @@ static int __init mx31pdk_init_expio(void)
                return -ENODEV;
        }
 
-       pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n",
+       pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
                __raw_readw(CPLD_CODE_VER_REG));
 
        /*
@@ -201,7 +274,7 @@ static int __init mx31pdk_init_expio(void)
                set_irq_flags(i, IRQF_VALID);
        }
        set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-       set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler);
+       set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
 
        return 0;
 }
@@ -209,7 +282,7 @@ static int __init mx31pdk_init_expio(void)
 /*
  * This structure defines the MX31 memory map.
  */
-static struct map_desc mx31pdk_io_desc[] __initdata = {
+static struct map_desc mx31_3ds_io_desc[] __initdata = {
        {
                .virtual = MX31_CS5_BASE_ADDR_VIRT,
                .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
@@ -221,10 +294,10 @@ static struct map_desc mx31pdk_io_desc[] __initdata = {
 /*
  * Set up static virtual mappings.
  */
-static void __init mx31pdk_map_io(void)
+static void __init mx31_3ds_map_io(void)
 {
        mx31_map_io();
-       iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
+       iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -232,35 +305,40 @@ static void __init mx31pdk_map_io(void)
  */
 static void __init mxc_board_init(void)
 {
-       mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins),
-                                     "mx31pdk");
+       mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
+                                     "mx31_3ds");
 
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+       mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
+
+       mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+       spi_register_board_info(mx31_3ds_spi_devs,
+                                               ARRAY_SIZE(mx31_3ds_spi_devs));
 
-       if (!mx31pdk_init_expio())
+       if (!mx31_3ds_init_expio())
                platform_device_register(&smsc911x_device);
 }
 
-static void __init mx31pdk_timer_init(void)
+static void __init mx31_3ds_timer_init(void)
 {
        mx31_clocks_init(26000000);
 }
 
-static struct sys_timer mx31pdk_timer = {
-       .init   = mx31pdk_timer_init,
+static struct sys_timer mx31_3ds_timer = {
+       .init   = mx31_3ds_timer_init,
 };
 
 /*
  * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_MX31PDK data structure.
+ * initialize __mach_desc_MX31_3DS data structure.
  */
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .phys_io        = MX31_AIPS1_BASE_ADDR,
        .io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
-       .map_io         = mx31pdk_map_io,
+       .map_io         = mx31_3ds_map_io,
        .init_irq       = mx31_init_irq,
        .init_machine   = mxc_board_init,
-       .timer          = &mx31pdk_timer,
+       .timer          = &mx31_3ds_timer,
 MACHINE_END
index 034ec81900657d9b8880d39963c4008b4b7f208a..2df1ec55a97e6565980b27fd0ade0754921b20e1 100644 (file)
@@ -35,7 +35,6 @@
 #include <linux/can/platform/sja1000.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
 #include <linux/gfp.h>
 
 #include <media/soc_camera.h>
index ccd874225c3b6b19d5a52008b6bffe0efd1fc69a..093c595ca58119e2fef5d7924b84c8e0d92c36d2 100644 (file)
@@ -28,7 +28,6 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 
@@ -206,5 +205,6 @@ void __init mx31lite_db_init(void)
        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
        platform_device_register(&litekit_led_device);
+       mxc_register_device(&imx_wdt_device0, NULL);
 }
 
index be90c03101cd8bd27c2d72653b5e8f5f64d9d922..8f85f73b83a8a1b4a6e95f4070521c0bbd7d0d1d 100644 (file)
@@ -757,7 +757,7 @@ DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
 
 /* GPT */
 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-       NULL,  NULL, &ipg_perclk, NULL);
+       NULL,  NULL, &ipg_clk, NULL);
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
        NULL,  NULL, &ipg_clk, NULL);
 
index 41c769f08c4dd42e5a4361b6ccc02b5d557b81bc..2d37785e3857d32575a5948f36574e4770a0b917 100644 (file)
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/module.h>
 #include <mach/hardware.h>
 #include <asm/io.h>
 
+static int cpu_silicon_rev = -1;
+
+#define SI_REV 0x48
+
+static void query_silicon_parameter(void)
+{
+       void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
+       u32 rev;
+
+       if (!rom) {
+               cpu_silicon_rev = -EINVAL;
+               return;
+       }
+
+       rev = readl(rom + SI_REV);
+       switch (rev) {
+       case 0x1:
+               cpu_silicon_rev = MX51_CHIP_REV_1_0;
+               break;
+       case 0x2:
+               cpu_silicon_rev = MX51_CHIP_REV_1_1;
+               break;
+       case 0x10:
+               cpu_silicon_rev = MX51_CHIP_REV_2_0;
+               break;
+       case 0x20:
+               cpu_silicon_rev = MX51_CHIP_REV_3_0;
+               break;
+       default:
+               cpu_silicon_rev = 0;
+       }
+
+       iounmap(rom);
+}
+
+/*
+ * Returns:
+ *     the silicon revision of the cpu
+ *     -EINVAL - not a mx51
+ */
+int mx51_revision(void)
+{
+       if (!cpu_is_mx51())
+               return -EINVAL;
+
+       if (cpu_silicon_rev == -1)
+               query_silicon_parameter();
+
+       return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx51_revision);
+
 static int __init post_cpu_init(void)
 {
        unsigned int reg;
index c21e18be7af869082262d524a5d776df9a1a8f53..b7677ef80cc4388a4c414c4b7c8e1269137227a6 100644 (file)
@@ -34,11 +34,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
                .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
                .length = MX51_DEBUG_SIZE,
                .type = MT_DEVICE
-       }, {
-               .virtual = MX51_TZIC_BASE_ADDR_VIRT,
-               .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
-               .length = MX51_TZIC_SIZE,
-               .type = MT_DEVICE
        }, {
                .virtual = MX51_AIPS1_BASE_ADDR_VIRT,
                .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
@@ -54,11 +49,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
                .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
                .length = MX51_AIPS2_SIZE,
                .type = MT_DEVICE
-       }, {
-               .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
-               .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
-               .length = MX51_NFC_AXI_SIZE,
-               .type = MT_DEVICE
        },
 };
 
@@ -69,14 +59,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
  */
 void __init mx51_map_io(void)
 {
-       u32 tzic_addr;
-
-       if (mx51_revision() < MX51_CHIP_REV_2_0)
-               tzic_addr = 0x8FFFC000;
-       else
-               tzic_addr = 0xE0003000;
-       mxc_io_desc[2].pfn =  __phys_to_pfn(tzic_addr);
-
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
@@ -85,5 +67,17 @@ void __init mx51_map_io(void)
 
 void __init mx51_init_irq(void)
 {
-       tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
+       unsigned long tzic_addr;
+       void __iomem *tzic_virt;
+
+       if (mx51_revision() < MX51_CHIP_REV_2_0)
+               tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
+       else
+               tzic_addr = MX51_TZIC_BASE_ADDR;
+
+       tzic_virt = ioremap(tzic_addr, SZ_16K);
+       if (!tzic_virt)
+               panic("unable to map TZIC interrupt controller\n");
+
+       tzic_init_irq(tzic_virt);
 }
index 9d4da6ac28ebf9fae8718de70af211beede72156..4223d086aa1768c22f56085c59fb1a73cfb0f5ab 100644 (file)
@@ -420,6 +420,10 @@ static void __init build_mem_type_table(void)
                user_pgprot |= L_PTE_SHARED;
                kern_pgprot |= L_PTE_SHARED;
                vecs_pgprot |= L_PTE_SHARED;
+               mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
+               mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
+               mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
+               mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
                mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 #endif
similarity index 93%
rename from arch/arm/plat-mxc/include/mach/board-mx31pdk.h
rename to arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index 2bbd6ed17f50d0ca5bb5c70836344a054632b243..da92933a233bae5d2f45855df8a1e4d539a8e7b3 100644 (file)
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
+#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
 
 /* Definitions for components on the Debug board */
 
@@ -56,4 +56,4 @@
 
 #define MXC_MAX_EXP_IO_LINES   16
 
-#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
index 771532b6b4a600300900e4403f379b471b16b26f..5aad344d56515c82a1ef7eaf0dd5e9248e15ab7c 100644 (file)
@@ -14,7 +14,7 @@
  * FB100000    70000000        1M      SPBA 0
  * FB000000    73F00000        1M      AIPS 1
  * FB200000    83F00000        1M      AIPS 2
- * FA100000    8FFFC000        16K     TZIC (interrupt controller)
+ *             8FFFC000        16K     TZIC (interrupt controller)
  *             90000000        256M    CSD0 SDRAM/DDR
  *             A0000000        256M    CSD1 SDRAM/DDR
  *             B0000000        128M    CS0 Flash
  *             C8000000        64M     CS3 Flash
  *             CC000000        32M     CS4 SRAM
  *             CE000000        32M     CS5 SRAM
- * F9000000    CFFF0000        64K     NFC (NAND Flash AXI)
+ *             CFFF0000        64K     NFC (NAND Flash AXI)
  *
  */
 
+/*
+ * IROM
+ */
+#define MX51_IROM_BASE_ADDR            0x0
+#define MX51_IROM_SIZE                 SZ_64K
+
 /*
  * IRAM
  */
@@ -40,7 +46,6 @@
  * NFC
  */
 #define MX51_NFC_AXI_BASE_ADDR         0xCFFF0000      /* NAND flash AXI */
-#define MX51_NFC_AXI_BASE_ADDR_VIRT    0xF9000000
 #define MX51_NFC_AXI_SIZE              SZ_64K
 
 /*
@@ -49,9 +54,8 @@
 #define MX51_GPU_BASE_ADDR             0x20000000
 #define MX51_GPU2D_BASE_ADDR           0xD0000000
 
-#define MX51_TZIC_BASE_ADDR            0x8FFFC000
-#define MX51_TZIC_BASE_ADDR_VIRT       0xFA100000
-#define MX51_TZIC_SIZE                 SZ_16K
+#define MX51_TZIC_BASE_ADDR_TO1                0x8FFFC000
+#define MX51_TZIC_BASE_ADDR            0xE0000000
 
 #define MX51_DEBUG_BASE_ADDR           0x60000000
 #define MX51_DEBUG_BASE_ADDR_VIRT      0xFA200000
 #define MX51_IO_ADDRESS(x)                                     \
        (void __iomem *)                                        \
        (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) :    \
-       MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) :     \
        MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :   \
        MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :   \
        MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :   \
-       MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) :   \
-       MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
+       MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
        0xDEADBEEF)
 
 /*
 #define MX51_IRAM_IO_ADDRESS(x)  \
        (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
 
-#define MX51_TZIC_IO_ADDRESS(x)  \
-       (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
-
 #define MX51_DEBUG_IO_ADDRESS(x)  \
        (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
 
 #define MX51_AIPS2_IO_ADDRESS(x)  \
        (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
 
-#define MX51_NFC_AXI_IO_ADDRESS(x) \
-       (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
-
 #define MX51_IS_MEM_DEVICE_NONSHARED(x)                0
 
 /*
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 
-extern unsigned int system_rev;
-
-static inline unsigned int mx51_revision(void)
-{
-       return system_rev;
-}
+extern int mx51_revision(void);
 #endif
 
 #endif /*  __ASM_ARCH_MXC_MX51_H__ */
index 52e476a150ca5f22caed350304eb481097f66541..b6d3d0fddc48aebb62763c2d364bed0103909063 100644 (file)
@@ -66,6 +66,7 @@ static inline void flush(void)
 #define MX2X_UART1_BASE_ADDR   0x1000a000
 #define MX3X_UART1_BASE_ADDR   0x43F90000
 #define MX3X_UART2_BASE_ADDR   0x43F94000
+#define MX51_UART1_BASE_ADDR   0x73fbc000
 
 static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -101,6 +102,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
        case MACH_TYPE_MAGX_ZN5:
                uart_base = MX3X_UART2_BASE_ADDR;
                break;
+       case MACH_TYPE_MX51_BABBAGE:
+               uart_base = MX51_UART1_BASE_ADDR;
+               break;
        default:
                break;
        }