Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/genesis-2.6 into devel-stable
authorRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 6 Aug 2010 17:13:19 +0000 (18:13 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 6 Aug 2010 17:13:19 +0000 (18:13 +0100)
Conflicts:
drivers/net/irda/sh_irda.c

46 files changed:
MAINTAINERS
arch/arm/mach-shmobile/Kconfig
arch/arm/mach-shmobile/Makefile
arch/arm/mach-shmobile/board-ap4evb.c
arch/arm/mach-shmobile/board-g3evm.c
arch/arm/mach-shmobile/board-g4evm.c
arch/arm/mach-shmobile/clock-sh7367.c
arch/arm/mach-shmobile/clock-sh7372.c [new file with mode: 0644]
arch/arm/mach-shmobile/clock-sh7377.c [new file with mode: 0644]
arch/arm/mach-shmobile/clock.c [new file with mode: 0644]
arch/arm/mach-shmobile/include/mach/common.h
arch/arm/mach-shmobile/include/mach/irqs.h
arch/arm/mach-shmobile/include/mach/memory.h
arch/arm/mach-shmobile/include/mach/sh7372.h
arch/arm/mach-shmobile/include/mach/vmalloc.h
arch/arm/mach-shmobile/intc-sh7367.c
arch/arm/mach-shmobile/intc-sh7372.c
arch/arm/mach-shmobile/intc-sh7377.c
arch/arm/mach-shmobile/pfc-sh7372.c
arch/arm/mach-shmobile/setup-sh7367.c
arch/arm/mach-shmobile/setup-sh7372.c
arch/arm/mach-shmobile/setup-sh7377.c
arch/sh/boards/mach-ap325rxa/setup.c
arch/sh/boards/mach-kfr2r09/Makefile
arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
drivers/dma/Kconfig
drivers/dma/shdma.c
drivers/i2c/busses/Kconfig
drivers/i2c/busses/i2c-sh_mobile.c
drivers/net/irda/sh_irda.c
drivers/serial/sh-sci.c
drivers/serial/sh-sci.h
drivers/sh/Makefile
drivers/sh/clk-cpg.c
drivers/video/Kconfig
drivers/video/Makefile
drivers/video/sh_mipi_dsi.c [new file with mode: 0644]
drivers/video/sh_mobile_hdmi.c [new file with mode: 0644]
drivers/video/sh_mobile_lcdcfb.c
include/linux/serial_core.h
include/linux/sh_clk.h
include/video/mipi_display.h [new file with mode: 0644]
include/video/sh_mipi_dsi.h [new file with mode: 0644]
include/video/sh_mobile_hdmi.h [new file with mode: 0644]
include/video/sh_mobile_lcdc.h

index 5fb38d3f1423d61a0312174c77d588908a7e1e02..0c0d829176a2a3184caa163e5bff0d338e59e6fe 100644 (file)
@@ -955,8 +955,9 @@ ARM/SHMOBILE ARM ARCHITECTURE
 M:     Paul Mundt <lethal@linux-sh.org>
 M:     Magnus Damm <magnus.damm@gmail.com>
 L:     linux-sh@vger.kernel.org
-T:     git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
 W:     http://oss.renesas.com
+Q:     http://patchwork.kernel.org/project/linux-sh/list/
+T:     git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
 S:     Supported
 F:     arch/arm/mach-shmobile/
 F:     drivers/sh/
index 4c704b4e8b340c9a6482e2c3ec87da15029c67a8..54b479c35ee01d2db0f2f5c75f9786f329293146 100644 (file)
@@ -7,6 +7,7 @@ config ARCH_SH7367
        select CPU_V6
        select HAVE_CLK
        select COMMON_CLKDEV
+       select SH_CLK_CPG
        select GENERIC_CLOCKEVENTS
 
 config ARCH_SH7377
@@ -14,6 +15,7 @@ config ARCH_SH7377
        select CPU_V7
        select HAVE_CLK
        select COMMON_CLKDEV
+       select SH_CLK_CPG
        select GENERIC_CLOCKEVENTS
 
 config ARCH_SH7372
@@ -21,6 +23,7 @@ config ARCH_SH7372
        select CPU_V7
        select HAVE_CLK
        select COMMON_CLKDEV
+       select SH_CLK_CPG
        select GENERIC_CLOCKEVENTS
 
 comment "SH-Mobile Board Type"
@@ -39,6 +42,20 @@ config MACH_AP4EVB
        bool "AP4EVB board"
        depends on ARCH_SH7372
        select ARCH_REQUIRE_GPIOLIB
+       select SH_LCD_MIPI_DSI
+
+choice
+       prompt "AP4EVB LCD panel selection"
+       default AP4EVB_QHD
+       depends on MACH_AP4EVB
+
+config AP4EVB_QHD
+       bool "MIPI-DSI QHD (960x540)"
+
+config AP4EVB_WVGA
+       bool "Parallel WVGA (800x480)"
+
+endchoice
 
 comment "SH-Mobile System Configuration"
 
@@ -88,6 +105,15 @@ config SH_TIMER_CMT
        help
          This enables build of the CMT timer driver.
 
+config SH_TIMER_TMU
+       bool "TMU timer driver"
+       default y
+       help
+         This enables build of the TMU timer driver.
+
 endmenu
 
+config SH_CLK_CPG
+       bool
+
 endif
index 6d385d371c332aad7c448542b262bf85d8314c00..5e16b4c692222a4a45d5728cec5b4970cae495e0 100644 (file)
@@ -3,12 +3,12 @@
 #
 
 # Common objects
-obj-y                          := timer.o console.o
+obj-y                          := timer.o console.o clock.o
 
 # CPU objects
 obj-$(CONFIG_ARCH_SH7367)      += setup-sh7367.o clock-sh7367.o intc-sh7367.o
-obj-$(CONFIG_ARCH_SH7377)      += setup-sh7377.o clock-sh7367.o intc-sh7377.o
-obj-$(CONFIG_ARCH_SH7372)      += setup-sh7372.o clock-sh7367.o intc-sh7372.o
+obj-$(CONFIG_ARCH_SH7377)      += setup-sh7377.o clock-sh7377.o intc-sh7377.o
+obj-$(CONFIG_ARCH_SH7372)      += setup-sh7372.o clock-sh7372.o intc-sh7372.o
 
 # Pinmux setup
 pfc-$(CONFIG_ARCH_SH7367)      := pfc-sh7367.o
index 1c2ec96ce2610c88a9292b7edcf6adc1f390b808..23d472f9525e6a160c97cbf8adc21c505819fb05 100644 (file)
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/clk.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mmc/host.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
+#include <linux/sh_intc.h>
+#include <linux/sh_clk.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
+#include <linux/usb/r8a66597.h>
+
+#include <sound/sh_fsi.h>
+
+#include <video/sh_mobile_hdmi.h>
+#include <video/sh_mobile_lcdc.h>
+#include <video/sh_mipi_dsi.h>
+
 #include <mach/common.h>
+#include <mach/irqs.h>
 #include <mach/sh7372.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/time.h>
 
 /*
  * Address     Interface               BusWidth        note
  */
 
 /*
- * KEYSC
+ * LCD / IRQ / KEYSC / IrDA
+ *
+ * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
+ * LCD = 2nd LCDC (WVGA)
  *
- * SW43                KEYSC
- * -------------------------
- * ON          enable
- * OFF         disable
+ *             |               SW43                    |
+ * SW3         |       ON              |       OFF     |
+ * -------------+-----------------------+---------------+
+ * ON          | KEY / IrDA            | LCD           |
+ * OFF         | KEY / IrDA / IRQ      | IRQ           |
+ *
+ *
+ * QHD / WVGA display
+ *
+ * You can choice display type on menuconfig.
+ * Then, check above dip-switch.
+ */
+
+/*
+ * USB
+ *
+ * J7 : 1-2  MAX3355E VBUS
+ *      2-3  DC 5.0V
+ *
+ * S39: bit2: off
+ */
+
+/*
+ * FSI/FSMI
+ *
+ * SW41        :  ON : SH-Mobile AP4 Audio Mode
+ *     : OFF : Bluetooth Audio Mode
+ */
+
+/*
+ * MMC0/SDHI1 (CN7)
+ *
+ * J22 : select card voltage
+ *       1-2 pin : 1.8v
+ *       2-3 pin : 3.3v
+ *
+ *        SW1  |             SW33
+ *             | bit1 | bit2 | bit3 | bit4
+ * ------------+------+------+------+-------
+ * MMC0   OFF  |  OFF |  ON  |  ON  |  X
+ * SDHI1  OFF  |  ON  |   X  |  OFF | ON
+ *
+ * voltage lebel
+ * CN7 : 1.8v
+ * CN12: 3.3v
  */
 
 /* MTD */
@@ -148,7 +212,7 @@ static struct resource smc911x_resources[] = {
                .end    = 0x16000000 - 1,
                .flags  = IORESOURCE_MEM,
        }, {
-               .start  = 6,
+               .start  = evt2irq(0x02c0) /* IRQ6A */,
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
        },
 };
@@ -169,6 +233,180 @@ static struct platform_device smc911x_device = {
        },
 };
 
+/* SH_MMCIF */
+static struct resource sh_mmcif_resources[] = {
+       [0] = {
+               .name   = "SH_MMCIF",
+               .start  = 0xE6BD0000,
+               .end    = 0xE6BD00FF,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               /* MMC ERR */
+               .start  = evt2irq(0x1ac0),
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               /* MMC NOR */
+               .start  = evt2irq(0x1ae0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+       .sup_pclk       = 0,
+       .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+       .caps           = MMC_CAP_4_BIT_DATA |
+                         MMC_CAP_8_BIT_DATA |
+                         MMC_CAP_NEEDS_POLL,
+};
+
+static struct platform_device sh_mmcif_device = {
+       .name           = "sh_mmcif",
+       .id             = 0,
+       .dev            = {
+               .dma_mask               = NULL,
+               .coherent_dma_mask      = 0xffffffff,
+               .platform_data          = &sh_mmcif_plat,
+       },
+       .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+       .resource       = sh_mmcif_resources,
+};
+
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+       .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+       .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+};
+
+static struct resource sdhi0_resources[] = {
+       [0] = {
+               .name   = "SDHI0",
+               .start  = 0xe6850000,
+               .end    = 0xe68501ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x0e00) /* SDHI0 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi0_device = {
+       .name           = "sh_mobile_sdhi",
+       .num_resources  = ARRAY_SIZE(sdhi0_resources),
+       .resource       = sdhi0_resources,
+       .id             = 0,
+       .dev    = {
+               .platform_data  = &sdhi0_info,
+       },
+};
+
+/* SDHI1 */
+static struct sh_mobile_sdhi_info sdhi1_info = {
+       .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+       .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+       .tmio_ocr_mask  = MMC_VDD_165_195,
+};
+
+static struct resource sdhi1_resources[] = {
+       [0] = {
+               .name   = "SDHI1",
+               .start  = 0xe6860000,
+               .end    = 0xe68601ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x0e80),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi1_device = {
+       .name           = "sh_mobile_sdhi",
+       .num_resources  = ARRAY_SIZE(sdhi1_resources),
+       .resource       = sdhi1_resources,
+       .id             = 1,
+       .dev    = {
+               .platform_data  = &sdhi1_info,
+       },
+};
+
+/* USB1 */
+static void usb1_host_port_power(int port, int power)
+{
+       if (!power) /* only power-on supported for now */
+               return;
+
+       /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
+       __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+}
+
+static struct r8a66597_platdata usb1_host_data = {
+       .on_chip        = 1,
+       .port_power     = usb1_host_port_power,
+};
+
+static struct resource usb1_host_resources[] = {
+       [0] = {
+               .name   = "USBHS",
+               .start  = 0xE68B0000,
+               .end    = 0xE68B00E6 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device usb1_host_device = {
+       .name   = "r8a66597_hcd",
+       .id     = 1,
+       .dev = {
+               .dma_mask               = NULL,         /*  not use dma */
+               .coherent_dma_mask      = 0xffffffff,
+               .platform_data          = &usb1_host_data,
+       },
+       .num_resources  = ARRAY_SIZE(usb1_host_resources),
+       .resource       = usb1_host_resources,
+};
+
+static struct sh_mobile_lcdc_info lcdc_info = {
+       .ch[0] = {
+               .chan = LCDC_CHAN_MAINLCD,
+               .bpp = 16,
+       }
+};
+
+static struct resource lcdc_resources[] = {
+       [0] = {
+               .name   = "LCDC",
+               .start  = 0xfe940000, /* P4-only space */
+               .end    = 0xfe943fff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0x580),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device lcdc_device = {
+       .name           = "sh_mobile_lcdc_fb",
+       .num_resources  = ARRAY_SIZE(lcdc_resources),
+       .resource       = lcdc_resources,
+       .dev    = {
+               .platform_data  = &lcdc_info,
+               .coherent_dma_mask = ~0,
+       },
+};
+
+/*
+ * QHD display
+ */
+#ifdef CONFIG_AP4EVB_QHD
+
 /* KEYSC (Needs SW43 set to ON) */
 static struct sh_keysc_info keysc_info = {
        .mode           = SH_KEYSC_MODE_1,
@@ -191,7 +429,7 @@ static struct resource keysc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 79,
+               .start  = evt2irq(0x0be0), /* KEYSC_KEY */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -206,32 +444,362 @@ static struct platform_device keysc_device = {
        },
 };
 
-/* SDHI0 */
-static struct resource sdhi0_resources[] = {
+/* MIPI-DSI */
+static struct resource mipidsi0_resources[] = {
        [0] = {
-               .name   = "SDHI0",
-               .start  = 0xe6850000,
-               .end    = 0xe68501ff,
+               .start  = 0xffc60000,
+               .end    = 0xffc68fff,
                .flags  = IORESOURCE_MEM,
        },
+};
+
+static struct sh_mipi_dsi_info mipidsi0_info = {
+       .data_format    = MIPI_RGB888,
+       .lcd_chan       = &lcdc_info.ch[0],
+};
+
+static struct platform_device mipidsi0_device = {
+       .name           = "sh-mipi-dsi",
+       .num_resources  = ARRAY_SIZE(mipidsi0_resources),
+       .resource       = mipidsi0_resources,
+       .id             = 0,
+       .dev    = {
+               .platform_data  = &mipidsi0_info,
+       },
+};
+
+/* This function will disappear when we switch to (runtime) PM */
+static int __init ap4evb_init_display_clk(void)
+{
+       struct clk *lcdc_clk;
+       struct clk *dsitx_clk;
+       int ret;
+
+       lcdc_clk = clk_get(&lcdc_device.dev, "sh_mobile_lcdc_fb.0");
+       if (IS_ERR(lcdc_clk))
+               return PTR_ERR(lcdc_clk);
+
+       dsitx_clk = clk_get(&mipidsi0_device.dev, "sh-mipi-dsi.0");
+       if (IS_ERR(dsitx_clk)) {
+               ret = PTR_ERR(dsitx_clk);
+               goto eclkdsitxget;
+       }
+
+       ret = clk_enable(lcdc_clk);
+       if (ret < 0)
+               goto eclklcdcon;
+
+       ret = clk_enable(dsitx_clk);
+       if (ret < 0)
+               goto eclkdsitxon;
+
+       return 0;
+
+eclkdsitxon:
+       clk_disable(lcdc_clk);
+eclklcdcon:
+       clk_put(dsitx_clk);
+eclkdsitxget:
+       clk_put(lcdc_clk);
+
+       return ret;
+}
+device_initcall(ap4evb_init_display_clk);
+
+static struct platform_device *qhd_devices[] __initdata = {
+       &mipidsi0_device,
+       &keysc_device,
+};
+#endif /* CONFIG_AP4EVB_QHD */
+
+/* FSI */
+#define IRQ_FSI                evt2irq(0x1840)
+#define FSIACKCR       0xE6150018
+static void fsiackcr_init(struct clk *clk)
+{
+       u32 status = __raw_readl(clk->enable_reg);
+
+       /* use external clock */
+       status &= ~0x000000ff;
+       status |= 0x00000080;
+       __raw_writel(status, clk->enable_reg);
+}
+
+static struct clk_ops fsiackcr_clk_ops = {
+       .init = fsiackcr_init,
+};
+
+static struct clk fsiackcr_clk = {
+       .ops            = &fsiackcr_clk_ops,
+       .enable_reg     = (void __iomem *)FSIACKCR,
+       .rate           = 0, /* unknown */
+};
+
+static struct sh_fsi_platform_info fsi_info = {
+       .porta_flags = SH_FSI_BRS_INV |
+                      SH_FSI_OUT_SLAVE_MODE |
+                      SH_FSI_IN_SLAVE_MODE |
+                      SH_FSI_OFMT(PCM) |
+                      SH_FSI_IFMT(PCM),
+};
+
+static struct resource fsi_resources[] = {
+       [0] = {
+               .name   = "FSI",
+               .start  = 0xFE3C0000,
+               .end    = 0xFE3C0400 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
        [1] = {
-               .start  = 96,
+               .start  = IRQ_FSI,
                .flags  = IORESOURCE_IRQ,
        },
 };
 
-static struct platform_device sdhi0_device = {
-       .name           = "sh_mobile_sdhi",
-       .num_resources  = ARRAY_SIZE(sdhi0_resources),
-       .resource       = sdhi0_resources,
-       .id             = 0,
+static struct platform_device fsi_device = {
+       .name           = "sh_fsi2",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(fsi_resources),
+       .resource       = fsi_resources,
+       .dev    = {
+               .platform_data  = &fsi_info,
+       },
+};
+
+static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
+       .clock_source = LCDC_CLK_EXTERNAL,
+       .ch[0] = {
+               .chan = LCDC_CHAN_MAINLCD,
+               .bpp = 16,
+               .interface_type = RGB24,
+               .clock_divider = 1,
+               .flags = LCDC_FLAGS_DWPOL,
+               .lcd_cfg = {
+                       .name = "HDMI",
+                       /* So far only 720p is supported */
+                       .xres = 1280,
+                       .yres = 720,
+                       /*
+                        * If left and right margins are not multiples of 8,
+                        * LDHAJR will be adjusted accordingly by the LCDC
+                        * driver. Until we start using EDID, these values
+                        * might have to be adjusted for different monitors.
+                        */
+                       .left_margin = 200,
+                       .right_margin = 88,
+                       .hsync_len = 48,
+                       .upper_margin = 20,
+                       .lower_margin = 5,
+                       .vsync_len = 5,
+                       .pixclock = 13468,
+                       .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+               },
+       }
+};
+
+static struct resource lcdc1_resources[] = {
+       [0] = {
+               .name   = "LCDC1",
+               .start  = 0xfe944000,
+               .end    = 0xfe947fff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0x17a0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device lcdc1_device = {
+       .name           = "sh_mobile_lcdc_fb",
+       .num_resources  = ARRAY_SIZE(lcdc1_resources),
+       .resource       = lcdc1_resources,
+       .id             = 1,
+       .dev    = {
+               .platform_data  = &sh_mobile_lcdc1_info,
+               .coherent_dma_mask = ~0,
+       },
+};
+
+static struct sh_mobile_hdmi_info hdmi_info = {
+       .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
+       .lcd_dev = &lcdc1_device.dev,
+};
+
+static struct resource hdmi_resources[] = {
+       [0] = {
+               .name   = "HDMI",
+               .start  = 0xe6be0000,
+               .end    = 0xe6be00ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
+               .start  = evt2irq(0x17e0),
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device hdmi_device = {
+       .name           = "sh-mobile-hdmi",
+       .num_resources  = ARRAY_SIZE(hdmi_resources),
+       .resource       = hdmi_resources,
+       .id             = -1,
+       .dev    = {
+               .platform_data  = &hdmi_info,
+       },
 };
 
 static struct platform_device *ap4evb_devices[] __initdata = {
        &nor_flash_device,
        &smc911x_device,
-       &keysc_device,
        &sdhi0_device,
+       &sdhi1_device,
+       &usb1_host_device,
+       &fsi_device,
+       &sh_mmcif_device,
+       &lcdc1_device,
+       &lcdc_device,
+       &hdmi_device,
+};
+
+static int __init hdmi_init_pm_clock(void)
+{
+       struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+       int ret;
+       long rate;
+
+       if (IS_ERR(hdmi_ick)) {
+               ret = PTR_ERR(hdmi_ick);
+               pr_err("Cannot get HDMI ICK: %d\n", ret);
+               goto out;
+       }
+
+       ret = clk_set_parent(&pllc2_clk, &dv_clki_div2_clk);
+       if (ret < 0) {
+               pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, pllc2_clk.usecount);
+               goto out;
+       }
+
+       pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&pllc2_clk));
+
+       rate = clk_round_rate(&pllc2_clk, 594000000);
+       if (rate < 0) {
+               pr_err("Cannot get suitable rate: %ld\n", rate);
+               ret = rate;
+               goto out;
+       }
+
+       ret = clk_set_rate(&pllc2_clk, rate);
+       if (ret < 0) {
+               pr_err("Cannot set rate %ld: %d\n", rate, ret);
+               goto out;
+       }
+
+       pr_debug("PLLC2 set frequency %lu\n", rate);
+
+       ret = clk_set_parent(hdmi_ick, &pllc2_clk);
+       if (ret < 0) {
+               pr_err("Cannot set HDMI parent: %d\n", ret);
+               goto out;
+       }
+
+out:
+       if (!IS_ERR(hdmi_ick))
+               clk_put(hdmi_ick);
+       return ret;
+}
+
+device_initcall(hdmi_init_pm_clock);
+
+/*
+ * FIXME !!
+ *
+ * gpio_no_direction
+ * gpio_pull_up
+ * are quick_hack.
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static void __init gpio_no_direction(u32 addr)
+{
+       __raw_writeb(0x00, addr);
+}
+
+static void __init gpio_pull_up(u32 addr)
+{
+       u8 data = __raw_readb(addr);
+
+       data &= 0x0F;
+       data |= 0xC0;
+       __raw_writeb(data, addr);
+}
+
+/* TouchScreen */
+#define IRQ28  evt2irq(0x3380) /* IRQ28A */
+#define IRQ7   evt2irq(0x02e0) /* IRQ7A */
+static int ts_get_pendown_state(void)
+{
+       int val1, val2;
+
+       gpio_free(GPIO_FN_IRQ28_123);
+       gpio_free(GPIO_FN_IRQ7_40);
+
+       gpio_request(GPIO_PORT123, NULL);
+       gpio_request(GPIO_PORT40, NULL);
+
+       gpio_direction_input(GPIO_PORT123);
+       gpio_direction_input(GPIO_PORT40);
+
+       val1 = gpio_get_value(GPIO_PORT123);
+       val2 = gpio_get_value(GPIO_PORT40);
+
+       gpio_request(GPIO_FN_IRQ28_123, NULL);  /* for QHD */
+       gpio_request(GPIO_FN_IRQ7_40, NULL);    /* for WVGA */
+
+       return val1 ^ val2;
+}
+
+#define PORT40CR       0xE6051028
+#define PORT123CR      0xE605007B
+static int ts_init(void)
+{
+       gpio_request(GPIO_FN_IRQ28_123, NULL);  /* for QHD */
+       gpio_request(GPIO_FN_IRQ7_40, NULL);    /* for WVGA */
+
+       gpio_pull_up(PORT40CR);
+       gpio_pull_up(PORT123CR);
+
+       return 0;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+       .model                  = 2007,
+       .x_plate_ohms           = 180,
+       .get_pendown_state      = ts_get_pendown_state,
+       .init_platform_hw       = ts_init,
+};
+
+static struct i2c_board_info tsc_device = {
+       I2C_BOARD_INFO("tsc2007", 0x48),
+       .type           = "tsc2007",
+       .platform_data  = &tsc2007_info,
+       /*.irq is selected on ap4evb_init */
+};
+
+/* I2C */
+static struct i2c_board_info i2c0_devices[] = {
+       {
+               I2C_BOARD_INFO("ak4643", 0x13),
+       },
+};
+
+static struct i2c_board_info i2c1_devices[] = {
+       {
+               I2C_BOARD_INFO("r2025sd", 0x32),
+       },
 };
 
 static struct map_desc ap4evb_io_desc[] __initdata = {
@@ -250,14 +818,18 @@ static void __init ap4evb_map_io(void)
 {
        iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
 
-       /* setup early devices, clocks and console here as well */
+       /* setup early devices and console here as well */
        sh7372_add_early_devices();
-       sh7367_clock_init(); /* use g3 clocks for now */
        shmobile_setup_console();
 }
 
+#define GPIO_PORT9CR   0xE6051009
+#define GPIO_PORT10CR  0xE605100A
 static void __init ap4evb_init(void)
 {
+       u32 srcr4;
+       struct clk *clk;
+
        sh7372_pinmux_init();
 
        /* enable SCIFA0 */
@@ -296,6 +868,93 @@ static void __init ap4evb_init(void)
        gpio_export(GPIO_PORT34, 0);
        gpio_export(GPIO_PORT35, 0);
 
+       /* SDHI0 */
+       gpio_request(GPIO_FN_SDHICD0, NULL);
+       gpio_request(GPIO_FN_SDHIWP0, NULL);
+       gpio_request(GPIO_FN_SDHICMD0, NULL);
+       gpio_request(GPIO_FN_SDHICLK0, NULL);
+       gpio_request(GPIO_FN_SDHID0_3, NULL);
+       gpio_request(GPIO_FN_SDHID0_2, NULL);
+       gpio_request(GPIO_FN_SDHID0_1, NULL);
+       gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+       /* SDHI1 */
+       gpio_request(GPIO_FN_SDHICMD1, NULL);
+       gpio_request(GPIO_FN_SDHICLK1, NULL);
+       gpio_request(GPIO_FN_SDHID1_3, NULL);
+       gpio_request(GPIO_FN_SDHID1_2, NULL);
+       gpio_request(GPIO_FN_SDHID1_1, NULL);
+       gpio_request(GPIO_FN_SDHID1_0, NULL);
+
+       /* MMCIF */
+       gpio_request(GPIO_FN_MMCD0_0, NULL);
+       gpio_request(GPIO_FN_MMCD0_1, NULL);
+       gpio_request(GPIO_FN_MMCD0_2, NULL);
+       gpio_request(GPIO_FN_MMCD0_3, NULL);
+       gpio_request(GPIO_FN_MMCD0_4, NULL);
+       gpio_request(GPIO_FN_MMCD0_5, NULL);
+       gpio_request(GPIO_FN_MMCD0_6, NULL);
+       gpio_request(GPIO_FN_MMCD0_7, NULL);
+       gpio_request(GPIO_FN_MMCCMD0, NULL);
+       gpio_request(GPIO_FN_MMCCLK0, NULL);
+
+       /* USB enable */
+       gpio_request(GPIO_FN_VBUS0_1,    NULL);
+       gpio_request(GPIO_FN_IDIN_1_18,  NULL);
+       gpio_request(GPIO_FN_PWEN_1_115, NULL);
+       gpio_request(GPIO_FN_OVCN_1_114, NULL);
+       gpio_request(GPIO_FN_EXTLP_1,    NULL);
+       gpio_request(GPIO_FN_OVCN2_1,    NULL);
+
+       /* setup USB phy */
+       __raw_writew(0x8a0a, 0xE6058130);       /* USBCR2 */
+
+       /* enable FSI2 */
+       gpio_request(GPIO_FN_FSIAIBT,   NULL);
+       gpio_request(GPIO_FN_FSIAILR,   NULL);
+       gpio_request(GPIO_FN_FSIAISLD,  NULL);
+       gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+       gpio_request(GPIO_PORT161,      NULL);
+       gpio_direction_output(GPIO_PORT161, 0); /* slave */
+
+       gpio_request(GPIO_PORT9, NULL);
+       gpio_request(GPIO_PORT10, NULL);
+       gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
+       gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
+
+       /* set SPU2 clock to 119.6 MHz */
+       clk = clk_get(NULL, "spu_clk");
+       if (!IS_ERR(clk)) {
+               clk_set_rate(clk, clk_round_rate(clk, 119600000));
+               clk_put(clk);
+       }
+
+       /* change parent of FSI A */
+       clk = clk_get(NULL, "fsia_clk");
+       if (!IS_ERR(clk)) {
+               clk_register(&fsiackcr_clk);
+               clk_set_parent(clk, &fsiackcr_clk);
+               clk_put(clk);
+       }
+
+       /*
+        * set irq priority, to avoid sound chopping
+        * when NFS rootfs is used
+        *  FSI(3) > SMSC911X(2)
+        */
+       intc_set_priority(IRQ_FSI, 3);
+
+       i2c_register_board_info(0, i2c0_devices,
+                               ARRAY_SIZE(i2c0_devices));
+
+       i2c_register_board_info(1, i2c1_devices,
+                               ARRAY_SIZE(i2c1_devices));
+
+#ifdef CONFIG_AP4EVB_QHD
+       /*
+        * QHD
+        */
+
        /* enable KEYSC */
        gpio_request(GPIO_FN_KEYOUT0, NULL);
        gpio_request(GPIO_FN_KEYOUT1, NULL);
@@ -308,26 +967,122 @@ static void __init ap4evb_init(void)
        gpio_request(GPIO_FN_KEYIN3_133, NULL);
        gpio_request(GPIO_FN_KEYIN4,     NULL);
 
-       /* SDHI0 */
-       gpio_request(GPIO_FN_SDHICD0, NULL);
-       gpio_request(GPIO_FN_SDHIWP0, NULL);
-       gpio_request(GPIO_FN_SDHICMD0, NULL);
-       gpio_request(GPIO_FN_SDHICLK0, NULL);
-       gpio_request(GPIO_FN_SDHID0_3, NULL);
-       gpio_request(GPIO_FN_SDHID0_2, NULL);
-       gpio_request(GPIO_FN_SDHID0_1, NULL);
-       gpio_request(GPIO_FN_SDHID0_0, NULL);
+       /* enable TouchScreen */
+       set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
+
+       tsc_device.irq = IRQ28;
+       i2c_register_board_info(1, &tsc_device, 1);
+
+       /* LCDC0 */
+       lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
+       lcdc_info.ch[0].interface_type          = RGB24;
+       lcdc_info.ch[0].clock_divider           = 1;
+       lcdc_info.ch[0].flags                   = LCDC_FLAGS_DWPOL;
+       lcdc_info.ch[0].lcd_cfg.name            = "R63302(QHD)";
+       lcdc_info.ch[0].lcd_cfg.xres            = 544;
+       lcdc_info.ch[0].lcd_cfg.yres            = 961;
+       lcdc_info.ch[0].lcd_cfg.left_margin     = 72;
+       lcdc_info.ch[0].lcd_cfg.right_margin    = 600;
+       lcdc_info.ch[0].lcd_cfg.hsync_len       = 16;
+       lcdc_info.ch[0].lcd_cfg.upper_margin    = 8;
+       lcdc_info.ch[0].lcd_cfg.lower_margin    = 8;
+       lcdc_info.ch[0].lcd_cfg.vsync_len       = 2;
+       lcdc_info.ch[0].lcd_cfg.sync            = FB_SYNC_VERT_HIGH_ACT |
+                                                 FB_SYNC_HOR_HIGH_ACT;
+       lcdc_info.ch[0].lcd_size_cfg.width      = 44;
+       lcdc_info.ch[0].lcd_size_cfg.height     = 79;
+
+       platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
+
+#else
+       /*
+        * WVGA
+        */
+       gpio_request(GPIO_FN_LCDD17,   NULL);
+       gpio_request(GPIO_FN_LCDD16,   NULL);
+       gpio_request(GPIO_FN_LCDD15,   NULL);
+       gpio_request(GPIO_FN_LCDD14,   NULL);
+       gpio_request(GPIO_FN_LCDD13,   NULL);
+       gpio_request(GPIO_FN_LCDD12,   NULL);
+       gpio_request(GPIO_FN_LCDD11,   NULL);
+       gpio_request(GPIO_FN_LCDD10,   NULL);
+       gpio_request(GPIO_FN_LCDD9,    NULL);
+       gpio_request(GPIO_FN_LCDD8,    NULL);
+       gpio_request(GPIO_FN_LCDD7,    NULL);
+       gpio_request(GPIO_FN_LCDD6,    NULL);
+       gpio_request(GPIO_FN_LCDD5,    NULL);
+       gpio_request(GPIO_FN_LCDD4,    NULL);
+       gpio_request(GPIO_FN_LCDD3,    NULL);
+       gpio_request(GPIO_FN_LCDD2,    NULL);
+       gpio_request(GPIO_FN_LCDD1,    NULL);
+       gpio_request(GPIO_FN_LCDD0,    NULL);
+       gpio_request(GPIO_FN_LCDDISP,  NULL);
+       gpio_request(GPIO_FN_LCDDCK,   NULL);
+
+       gpio_request(GPIO_PORT189, NULL); /* backlight */
+       gpio_direction_output(GPIO_PORT189, 1);
+
+       gpio_request(GPIO_PORT151, NULL); /* LCDDON */
+       gpio_direction_output(GPIO_PORT151, 1);
+
+       lcdc_info.clock_source                  = LCDC_CLK_BUS;
+       lcdc_info.ch[0].interface_type          = RGB18;
+       lcdc_info.ch[0].clock_divider           = 2;
+       lcdc_info.ch[0].flags                   = 0;
+       lcdc_info.ch[0].lcd_cfg.name            = "WVGA Panel";
+       lcdc_info.ch[0].lcd_cfg.xres            = 800;
+       lcdc_info.ch[0].lcd_cfg.yres            = 480;
+       lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
+       lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
+       lcdc_info.ch[0].lcd_cfg.hsync_len       = 70;
+       lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
+       lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
+       lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
+       lcdc_info.ch[0].lcd_cfg.sync            = 0;
+       lcdc_info.ch[0].lcd_size_cfg.width      = 152;
+       lcdc_info.ch[0].lcd_size_cfg.height     = 91;
+
+       /* enable TouchScreen */
+       set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
+
+       tsc_device.irq = IRQ7;
+       i2c_register_board_info(0, &tsc_device, 1);
+#endif /* CONFIG_AP4EVB_QHD */
 
        sh7372_add_standard_devices();
 
+       /* HDMI */
+       gpio_request(GPIO_FN_HDMI_HPD, NULL);
+       gpio_request(GPIO_FN_HDMI_CEC, NULL);
+
+       /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
+#define SRCR4 0xe61580bc
+       srcr4 = __raw_readl(SRCR4);
+       __raw_writel(srcr4 | (1 << 13), SRCR4);
+       udelay(50);
+       __raw_writel(srcr4 & ~(1 << 13), SRCR4);
+
        platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
 }
 
+static void __init ap4evb_timer_init(void)
+{
+       sh7372_clock_init();
+       shmobile_timer.init();
+
+       /* External clock source */
+       clk_set_rate(&dv_clki_clk, 27000000);
+}
+
+static struct sys_timer ap4evb_timer = {
+       .init           = ap4evb_timer_init,
+};
+
 MACHINE_START(AP4EVB, "ap4evb")
        .phys_io        = 0xe6000000,
        .io_pg_offst    = ((0xe6000000) >> 18) & 0xfffc,
        .map_io         = ap4evb_map_io,
        .init_irq       = sh7372_init_irq,
        .init_machine   = ap4evb_init,
-       .timer          = &shmobile_timer,
+       .timer          = &ap4evb_timer,
 MACHINE_END
index 9247503296c4135807fc1a19f24894413ccc7de1..a5525901e91f43e849811688d2066c6909f65ca8 100644 (file)
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+/*
+ * IrDA
+ *
+ * S67: 5bit : ON  power
+ *    : 6bit : ON  remote control
+ *             OFF IrDA
+ */
 
 static struct mtd_partition nor_flash_partitions[] = {
        {
@@ -91,7 +100,7 @@ static struct platform_device nor_flash_device = {
 };
 
 /* USBHS */
-void usb_host_port_power(int port, int power)
+static void usb_host_port_power(int port, int power)
 {
        if (!power) /* only power-on supported for now */
                return;
@@ -113,7 +122,7 @@ static struct resource usb_host_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 65,
+               .start  = evt2irq(0xa20), /* USBHS_USHI0 */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -153,7 +162,7 @@ static struct resource keysc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 79,
+               .start  = evt2irq(0xbe0), /* KEYSC_KEY */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -209,11 +218,31 @@ static struct platform_device nand_flash_device = {
        },
 };
 
+static struct resource irda_resources[] = {
+       [0] = {
+               .start  = 0xE6D00000,
+               .end    = 0xE6D01FD4 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x480), /* IRDA */
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device irda_device = {
+       .name           = "sh_irda",
+       .id             = -1,
+       .resource       = irda_resources,
+       .num_resources  = ARRAY_SIZE(irda_resources),
+};
+
 static struct platform_device *g3evm_devices[] __initdata = {
        &nor_flash_device,
        &usb_host_device,
        &keysc_device,
        &nand_flash_device,
+       &irda_device,
 };
 
 static struct map_desc g3evm_io_desc[] __initdata = {
@@ -232,9 +261,8 @@ static void __init g3evm_map_io(void)
 {
        iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
 
-       /* setup early devices, clocks and console here as well */
+       /* setup early devices and console here as well */
        sh7367_add_early_devices();
-       sh7367_clock_init();
        shmobile_setup_console();
 }
 
@@ -271,9 +299,6 @@ static void __init g3evm_init(void)
        gpio_request(GPIO_FN_EXTLP, NULL);
        gpio_request(GPIO_FN_IDIN, NULL);
 
-       /* enable clock in SYMSTPCR2 */
-       __raw_writel(__raw_readl(0xe6158048) & ~(1 << 22), 0xe6158048);
-
        /* setup USB phy */
        __raw_writew(0x0300, 0xe605810a);       /* USBCR1 */
        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
@@ -318,16 +343,32 @@ static void __init g3evm_init(void)
        /* FOE, FCDE, FSC on dedicated pins */
        __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
 
+       /* IrDA */
+       gpio_request(GPIO_FN_IRDA_OUT, NULL);
+       gpio_request(GPIO_FN_IRDA_IN, NULL);
+       gpio_request(GPIO_FN_IRDA_FIRSEL, NULL);
+       set_irq_type(evt2irq(0x480), IRQ_TYPE_LEVEL_LOW);
+
        sh7367_add_standard_devices();
 
        platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
 }
 
+static void __init g3evm_timer_init(void)
+{
+       sh7367_clock_init();
+       shmobile_timer.init();
+}
+
+static struct sys_timer g3evm_timer = {
+       .init           = g3evm_timer_init,
+};
+
 MACHINE_START(G3EVM, "g3evm")
        .phys_io        = 0xe6000000,
        .io_pg_offst    = ((0xe6000000) >> 18) & 0xfffc,
        .map_io         = g3evm_map_io,
        .init_irq       = sh7367_init_irq,
        .init_machine   = g3evm_init,
-       .timer          = &shmobile_timer,
+       .timer          = &g3evm_timer,
 MACHINE_END
index 10673a90be52946cd391adb2aa611f7e9e3ab18c..2c3ff6f7f34cec4909897fd13422c6ef04a65f54 100644 (file)
 #include <linux/io.h>
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
+#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/gpio.h>
 #include <mach/sh7377.h>
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+/*
+ * SDHI
+ *
+ * SDHI0 : card detection is possible
+ * SDHI1 : card detection is impossible
+ *
+ * [G4-MAIN-BOARD]
+ * JP74 : short                # DBG_2V8A    for SDHI0
+ * JP75 : NC           # DBG_3V3A    for SDHI0
+ * JP76 : NC           # DBG_3V3A_SD for SDHI0
+ * JP77 : NC           # 3V3A_SDIO   for SDHI1
+ * JP78 : short                # DBG_2V8A    for SDHI1
+ * JP79 : NC           # DBG_3V3A    for SDHI1
+ * JP80 : NC           # DBG_3V3A_SD for SDHI1
+ *
+ * [G4-CORE-BOARD]
+ * S32 : all off       # to dissever from G3-CORE_DBG board
+ * S33 : all off       # to dissever from G3-CORE_DBG board
+ *
+ * [G3-CORE_DBG-BOARD]
+ * S1  : all off       # to dissever from G3-CORE_DBG board
+ * S3  : all off       # to dissever from G3-CORE_DBG board
+ * S4  : all off       # to dissever from G3-CORE_DBG board
+ */
 
 static struct mtd_partition nor_flash_partitions[] = {
        {
@@ -90,7 +117,7 @@ static struct platform_device nor_flash_device = {
 };
 
 /* USBHS */
-void usb_host_port_power(int port, int power)
+static void usb_host_port_power(int port, int power)
 {
        if (!power) /* only power-on supported for now */
                return;
@@ -112,8 +139,7 @@ static struct resource usb_host_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 65,
-               .end    = 65,
+               .start  = evt2irq(0x0a20), /* USBHS_USHI0 */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -154,7 +180,7 @@ static struct resource keysc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 79,
+               .start  = evt2irq(0x0be0), /* KEYSC_KEY */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -169,10 +195,53 @@ static struct platform_device keysc_device = {
        },
 };
 
+/* SDHI */
+static struct resource sdhi0_resources[] = {
+       [0] = {
+               .name   = "SDHI0",
+               .start  = 0xe6d50000,
+               .end    = 0xe6d501ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x0e00), /* SDHI0 */
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi0_device = {
+       .name           = "sh_mobile_sdhi",
+       .num_resources  = ARRAY_SIZE(sdhi0_resources),
+       .resource       = sdhi0_resources,
+       .id             = 0,
+};
+
+static struct resource sdhi1_resources[] = {
+       [0] = {
+               .name   = "SDHI1",
+               .start  = 0xe6d60000,
+               .end    = 0xe6d601ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x0e80), /* SDHI1 */
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device sdhi1_device = {
+       .name           = "sh_mobile_sdhi",
+       .num_resources  = ARRAY_SIZE(sdhi1_resources),
+       .resource       = sdhi1_resources,
+       .id             = 1,
+};
+
 static struct platform_device *g4evm_devices[] __initdata = {
        &nor_flash_device,
        &usb_host_device,
        &keysc_device,
+       &sdhi0_device,
+       &sdhi1_device,
 };
 
 static struct map_desc g4evm_io_desc[] __initdata = {
@@ -191,12 +260,41 @@ static void __init g4evm_map_io(void)
 {
        iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
 
-       /* setup early devices, clocks and console here as well */
+       /* setup early devices and console here as well */
        sh7377_add_early_devices();
-       sh7367_clock_init(); /* use g3 clocks for now */
        shmobile_setup_console();
 }
 
+#define GPIO_SDHID0_D0 0xe60520fc
+#define GPIO_SDHID0_D1 0xe60520fd
+#define GPIO_SDHID0_D2 0xe60520fe
+#define GPIO_SDHID0_D3 0xe60520ff
+#define GPIO_SDHICMD0  0xe6052100
+
+#define GPIO_SDHID1_D0 0xe6052103
+#define GPIO_SDHID1_D1 0xe6052104
+#define GPIO_SDHID1_D2 0xe6052105
+#define GPIO_SDHID1_D3 0xe6052106
+#define GPIO_SDHICMD1  0xe6052107
+
+/*
+ * FIXME !!
+ *
+ * gpio_pull_up is quick_hack.
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static void __init gpio_pull_up(u32 addr)
+{
+       u8 data = __raw_readb(addr);
+
+       data &= 0x0F;
+       data |= 0xC0;
+       __raw_writeb(data, addr);
+}
+
 static void __init g4evm_init(void)
 {
        sh7377_pinmux_init();
@@ -229,9 +327,6 @@ static void __init g4evm_init(void)
        gpio_request(GPIO_FN_EXTLP, NULL);
        gpio_request(GPIO_FN_IDIN, NULL);
 
-       /* enable clock in SMSTPCR3 */
-       __raw_writel(__raw_readl(0xe615013c) & ~(1 << 22), 0xe615013c);
-
        /* setup USB phy */
        __raw_writew(0x0200, 0xe605810a);       /* USBCR1 */
        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
@@ -253,16 +348,54 @@ static void __init g4evm_init(void)
        gpio_request(GPIO_FN_PORT71_KEYIN5_PU, NULL);
        gpio_request(GPIO_FN_PORT72_KEYIN6_PU, NULL);
 
+       /* SDHI0 */
+       gpio_request(GPIO_FN_SDHICLK0, NULL);
+       gpio_request(GPIO_FN_SDHICD0, NULL);
+       gpio_request(GPIO_FN_SDHID0_0, NULL);
+       gpio_request(GPIO_FN_SDHID0_1, NULL);
+       gpio_request(GPIO_FN_SDHID0_2, NULL);
+       gpio_request(GPIO_FN_SDHID0_3, NULL);
+       gpio_request(GPIO_FN_SDHICMD0, NULL);
+       gpio_request(GPIO_FN_SDHIWP0, NULL);
+       gpio_pull_up(GPIO_SDHID0_D0);
+       gpio_pull_up(GPIO_SDHID0_D1);
+       gpio_pull_up(GPIO_SDHID0_D2);
+       gpio_pull_up(GPIO_SDHID0_D3);
+       gpio_pull_up(GPIO_SDHICMD0);
+
+       /* SDHI1 */
+       gpio_request(GPIO_FN_SDHICLK1, NULL);
+       gpio_request(GPIO_FN_SDHID1_0, NULL);
+       gpio_request(GPIO_FN_SDHID1_1, NULL);
+       gpio_request(GPIO_FN_SDHID1_2, NULL);
+       gpio_request(GPIO_FN_SDHID1_3, NULL);
+       gpio_request(GPIO_FN_SDHICMD1, NULL);
+       gpio_pull_up(GPIO_SDHID1_D0);
+       gpio_pull_up(GPIO_SDHID1_D1);
+       gpio_pull_up(GPIO_SDHID1_D2);
+       gpio_pull_up(GPIO_SDHID1_D3);
+       gpio_pull_up(GPIO_SDHICMD1);
+
        sh7377_add_standard_devices();
 
        platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
 }
 
+static void __init g4evm_timer_init(void)
+{
+       sh7377_clock_init();
+       shmobile_timer.init();
+}
+
+static struct sys_timer g4evm_timer = {
+       .init           = g4evm_timer_init,
+};
+
 MACHINE_START(G4EVM, "g4evm")
        .phys_io        = 0xe6000000,
        .io_pg_offst    = ((0xe6000000) >> 18) & 0xfffc,
        .map_io         = g4evm_map_io,
        .init_irq       = sh7377_init_irq,
        .init_machine   = g4evm_init,
-       .timer          = &shmobile_timer,
+       .timer          = &g4evm_timer,
 MACHINE_END
index bb940c6e4e6ca6f26ac87824b919a316aec732ed..b6454c9f2abb07b48b01899b87fdb281153c9b2b 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Preliminary clock framework support for sh7367
+ * SH7367 clock framework support
  *
  * Copyright (C) 2010  Magnus Damm
  *
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 #include <linux/init.h>
-#include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <mach/common.h>
+#include <asm/clkdev.h>
+
+/* SH7367 registers */
+#define RTFRQCR    0xe6150000
+#define SYFRQCR    0xe6150004
+#define CMFRQCR    0xe61500E0
+#define VCLKCR1    0xe6150008
+#define VCLKCR2    0xe615000C
+#define VCLKCR3    0xe615001C
+#define SCLKACR    0xe6150010
+#define SCLKBCR    0xe6150014
+#define SUBUSBCKCR 0xe6158080
+#define SPUCKCR    0xe6150084
+#define MSUCKCR    0xe6150088
+#define MVI3CKCR   0xe6150090
+#define VOUCKCR    0xe6150094
+#define MFCK1CR    0xe6150098
+#define MFCK2CR    0xe615009C
+#define PLLC1CR    0xe6150028
+#define PLLC2CR    0xe615002C
+#define RTMSTPCR0  0xe6158030
+#define RTMSTPCR2  0xe6158038
+#define SYMSTPCR0  0xe6158040
+#define SYMSTPCR2  0xe6158048
+#define CMMSTPCR0  0xe615804c
 
-struct clk {
-       const char *name;
-       unsigned long rate;
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+       .rate           = 32768,
 };
 
-#include <asm/clkdev.h>
+/*
+ * 26MHz default rate for the EXTALB1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7367_extalb1_clk = {
+       .rate           = 26666666,
+};
 
-int __clk_get(struct clk *clk)
-{
-       return 1;
-}
-EXPORT_SYMBOL(__clk_get);
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7367_extal2_clk = {
+       .rate           = 48000000,
+};
 
-void __clk_put(struct clk *clk)
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
 {
+       return clk->parent->rate / 2;
 }
-EXPORT_SYMBOL(__clk_put);
 
+static struct clk_ops div2_clk_ops = {
+       .recalc         = div2_recalc,
+};
+
+/* Divide extalb1 by two */
+static struct clk extalb1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh7367_extalb1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh7367_extal2_clk,
+};
 
-int clk_enable(struct clk *clk)
+/* PLLC1 */
+static unsigned long pllc1_recalc(struct clk *clk)
 {
-       return 0;
+       unsigned long mult = 1;
+
+       if (__raw_readl(PLLC1CR) & (1 << 14))
+               mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
+
+       return clk->parent->rate * mult;
 }
-EXPORT_SYMBOL(clk_enable);
 
-void clk_disable(struct clk *clk)
+static struct clk_ops pllc1_clk_ops = {
+       .recalc         = pllc1_recalc,
+};
+
+static struct clk pllc1_clk = {
+       .ops            = &pllc1_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &extalb1_div2_clk,
+};
+
+/* Divide PLLC1 by two */
+static struct clk pllc1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &pllc1_clk,
+};
+
+/* PLLC2 */
+static unsigned long pllc2_recalc(struct clk *clk)
 {
+       unsigned long mult = 1;
+
+       if (__raw_readl(PLLC2CR) & (1 << 31))
+               mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
+
+       return clk->parent->rate * mult;
 }
-EXPORT_SYMBOL(clk_disable);
 
-unsigned long clk_get_rate(struct clk *clk)
+static struct clk_ops pllc2_clk_ops = {
+       .recalc         = pllc2_recalc,
+};
+
+static struct clk pllc2_clk = {
+       .ops            = &pllc2_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &extalb1_div2_clk,
+};
+
+static struct clk *main_clks[] = {
+       &r_clk,
+       &sh7367_extalb1_clk,
+       &sh7367_extal2_clk,
+       &extalb1_div2_clk,
+       &extal2_div2_clk,
+       &pllc1_clk,
+       &pllc1_div2_clk,
+       &pllc2_clk,
+};
+
+static void div4_kick(struct clk *clk)
 {
-       return clk ? clk->rate : 0;
+       unsigned long value;
+
+       /* set KICK bit in SYFRQCR to update hardware setting */
+       value = __raw_readl(SYFRQCR);
+       value |= (1 << 31);
+       __raw_writel(value, SYFRQCR);
 }
-EXPORT_SYMBOL(clk_get_rate);
 
-/* a static peripheral clock for now - enough to get sh-sci working */
-static struct clk peripheral_clk = {
-       .name       = "peripheral_clk",
-       .rate       = 48000000,
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                         24, 32, 36, 48, 0, 72, 0, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+       .divisors = divisors,
+       .nr_divisors = ARRAY_SIZE(divisors),
 };
 
-/* a static rclk for now - enough to get sh_cmt working */
-static struct clk r_clk = {
-       .name       = "r_clk",
-       .rate       = 32768,
+static struct clk_div4_table div4_table = {
+       .div_mult_table = &div4_div_mult_table,
+       .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
+       DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
+       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+       [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
+       [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
+       [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
+       [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
+       [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
+       [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
+       [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
+       [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
+       [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
 };
 
-/* a static usb0 for now - enough to get r8a66597 working */
-static struct clk usb0_clk = {
-       .name       = "usb0",
+enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
+       DIV6_MVI3, DIV6_MF1, DIV6_MF2,
+       DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
+       DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+       [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
+       [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
+       [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
+       [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
+       [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
+       [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
+       [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
+       [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
+       [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
+       [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
+       [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
+       [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
 };
 
-/* a static keysc0 clk for now - enough to get sh_keysc working */
-static struct clk keysc0_clk = {
-       .name       = "keysc0",
+enum { RTMSTP001,
+       RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
+       RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
+       SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
+       SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
+       SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
+       SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
+       CMMSTP003,
+       MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[MSTP_NR] = {
+       [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
+       [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
+       [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
+       [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
+       [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
+       [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
+       [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
+       [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
+       [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
+       [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
+       [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
+       [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
+       [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
+       [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
+       [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
+       [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
+       [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
+       [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
+       [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
+       [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
+       [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
+       [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
+       [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
+       [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
+       [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
+       [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
+       [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
+       [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
 };
 
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
 static struct clk_lookup lookups[] = {
-       {
-               .clk = &peripheral_clk,
-       }, {
-               .clk = &r_clk,
-       }, {
-               .clk = &usb0_clk,
-       }, {
-               .clk = &keysc0_clk,
-       }
+       /* main clocks */
+       CLKDEV_CON_ID("r_clk", &r_clk),
+       CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
+       CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
+       CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
+       CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
+       CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
+       CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
+       CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
+
+       /* DIV4 clocks */
+       CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
+       CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
+       CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
+       CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
+       CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
+       CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
+       CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
+       CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
+       CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
+       CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
+       CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
+       CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
+
+       /* DIV6 clocks */
+       CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
+       CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
+       CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
+       CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
+       CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
+       CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
+       CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
+       CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
+       CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+       CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+       CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+       CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
+
+       /* MSTP32 clocks */
+       CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
+       CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
+       CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
+       CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
+       CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
+       CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
+       CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
+       CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
+       CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
+       CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
+       CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
+       CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */
+       CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
+       CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
+       CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
+       CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
+       CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
+       CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
 };
 
 void __init sh7367_clock_init(void)
 {
-       int i;
+       int k, ret = 0;
+
+       for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+               ret = clk_register(main_clks[k]);
+
+       if (!ret)
+               ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+       if (!ret)
+               ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+       if (!ret)
+               ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
-       for (i = 0; i < ARRAY_SIZE(lookups); i++) {
-               lookups[i].con_id = lookups[i].clk->name;
-               clkdev_add(&lookups[i]);
-       }
+       if (!ret)
+               clk_init();
+       else
+               panic("failed to setup sh7367 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
new file mode 100644 (file)
index 0000000..fb4e9b1
--- /dev/null
@@ -0,0 +1,560 @@
+/*
+ * SH7372 clock framework support
+ *
+ * Copyright (C) 2010 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <mach/common.h>
+#include <asm/clkdev.h>
+
+/* SH7372 registers */
+#define FRQCRA         0xe6150000
+#define FRQCRB         0xe6150004
+#define FRQCRC         0xe61500e0
+#define FRQCRD         0xe61500e4
+#define VCLKCR1                0xe6150008
+#define VCLKCR2                0xe615000c
+#define VCLKCR3                0xe615001c
+#define FMSICKCR       0xe6150010
+#define FMSOCKCR       0xe6150014
+#define FSIACKCR       0xe6150018
+#define FSIBCKCR       0xe6150090
+#define SUBCKCR                0xe6150080
+#define SPUCKCR                0xe6150084
+#define VOUCKCR                0xe6150088
+#define HDMICKCR       0xe6150094
+#define DSITCKCR       0xe6150060
+#define DSI0PCKCR      0xe6150064
+#define DSI1PCKCR      0xe6150098
+#define PLLC01CR       0xe6150028
+#define PLLC2CR                0xe615002c
+#define SMSTPCR0       0xe6150130
+#define SMSTPCR1       0xe6150134
+#define SMSTPCR2       0xe6150138
+#define SMSTPCR3       0xe615013c
+#define SMSTPCR4       0xe6150140
+
+/* Platforms must set frequency on their DV_CLKI pin */
+struct clk dv_clki_clk = {
+};
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+       .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTAL1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7372_extal1_clk = {
+       .rate           = 26000000,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7372_extal2_clk = {
+       .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+       return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+       .recalc         = div2_recalc,
+};
+
+/* Divide dv_clki by two */
+struct clk dv_clki_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &dv_clki_clk,
+};
+
+/* Divide extal1 by two */
+static struct clk extal1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh7372_extal1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh7372_extal2_clk,
+};
+
+/* Divide extal2 by four */
+static struct clk extal2_div4_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &extal2_div2_clk,
+};
+
+/* PLLC0 and PLLC1 */
+static unsigned long pllc01_recalc(struct clk *clk)
+{
+       unsigned long mult = 1;
+
+       if (__raw_readl(PLLC01CR) & (1 << 14))
+               mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
+
+       return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc01_clk_ops = {
+       .recalc         = pllc01_recalc,
+};
+
+static struct clk pllc0_clk = {
+       .ops            = &pllc01_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &extal1_div2_clk,
+       .enable_reg     = (void __iomem *)FRQCRC,
+};
+
+static struct clk pllc1_clk = {
+       .ops            = &pllc01_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &extal1_div2_clk,
+       .enable_reg     = (void __iomem *)FRQCRA,
+};
+
+/* Divide PLLC1 by two */
+static struct clk pllc1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &pllc1_clk,
+};
+
+/* PLLC2 */
+
+/* Indices are important - they are the actual src selecting values */
+static struct clk *pllc2_parent[] = {
+       [0] = &extal1_div2_clk,
+       [1] = &extal2_div2_clk,
+       [2] = &dv_clki_div2_clk,
+};
+
+/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
+static struct cpufreq_frequency_table pllc2_freq_table[29];
+
+static void pllc2_table_rebuild(struct clk *clk)
+{
+       int i;
+
+       /* Initialise PLLC2 frequency table */
+       for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
+               pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
+               pllc2_freq_table[i].index = i;
+       }
+
+       /* This is a special entry - switching PLL off makes it a repeater */
+       pllc2_freq_table[i].frequency = clk->parent->rate;
+       pllc2_freq_table[i].index = i;
+
+       pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
+       pllc2_freq_table[i].index = i;
+}
+
+static unsigned long pllc2_recalc(struct clk *clk)
+{
+       unsigned long mult = 1;
+
+       pllc2_table_rebuild(clk);
+
+       /*
+        * If the PLL is off, mult == 1, clk->rate will be updated in
+        * pllc2_enable().
+        */
+       if (__raw_readl(PLLC2CR) & (1 << 31))
+               mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
+
+       return clk->parent->rate * mult;
+}
+
+static long pllc2_round_rate(struct clk *clk, unsigned long rate)
+{
+       return clk_rate_table_round(clk, clk->freq_table, rate);
+}
+
+static int pllc2_enable(struct clk *clk)
+{
+       int i;
+
+       __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
+
+       for (i = 0; i < 100; i++)
+               if (__raw_readl(PLLC2CR) & 0x80000000) {
+                       clk->rate = pllc2_recalc(clk);
+                       return 0;
+               }
+
+       pr_err("%s(): timeout!\n", __func__);
+
+       return -ETIMEDOUT;
+}
+
+static void pllc2_disable(struct clk *clk)
+{
+       __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
+}
+
+static int pllc2_set_rate(struct clk *clk,
+                         unsigned long rate, int algo_id)
+{
+       unsigned long value;
+       int idx;
+
+       idx = clk_rate_table_find(clk, clk->freq_table, rate);
+       if (idx < 0)
+               return idx;
+
+       if (rate == clk->parent->rate) {
+               pllc2_disable(clk);
+               return 0;
+       }
+
+       value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
+
+       if (value & 0x80000000)
+               pllc2_disable(clk);
+
+       __raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
+
+       if (value & 0x80000000)
+               return pllc2_enable(clk);
+
+       return 0;
+}
+
+static int pllc2_set_parent(struct clk *clk, struct clk *parent)
+{
+       u32 value;
+       int ret, i;
+
+       if (!clk->parent_table || !clk->parent_num)
+               return -EINVAL;
+
+       /* Search the parent */
+       for (i = 0; i < clk->parent_num; i++)
+               if (clk->parent_table[i] == parent)
+                       break;
+
+       if (i == clk->parent_num)
+               return -ENODEV;
+
+       ret = clk_reparent(clk, parent);
+       if (ret < 0)
+               return ret;
+
+       value = __raw_readl(PLLC2CR) & ~(3 << 6);
+
+       __raw_writel(value | (i << 6), PLLC2CR);
+
+       /* Rebiuld the frequency table */
+       pllc2_table_rebuild(clk);
+
+       return 0;
+}
+
+static struct clk_ops pllc2_clk_ops = {
+       .recalc         = pllc2_recalc,
+       .round_rate     = pllc2_round_rate,
+       .set_rate       = pllc2_set_rate,
+       .enable         = pllc2_enable,
+       .disable        = pllc2_disable,
+       .set_parent     = pllc2_set_parent,
+};
+
+struct clk pllc2_clk = {
+       .ops            = &pllc2_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &extal1_div2_clk,
+       .freq_table     = pllc2_freq_table,
+       .parent_table   = pllc2_parent,
+       .parent_num     = ARRAY_SIZE(pllc2_parent),
+};
+
+static struct clk *main_clks[] = {
+       &dv_clki_clk,
+       &r_clk,
+       &sh7372_extal1_clk,
+       &sh7372_extal2_clk,
+       &dv_clki_div2_clk,
+       &extal1_div2_clk,
+       &extal2_div2_clk,
+       &extal2_div4_clk,
+       &pllc0_clk,
+       &pllc1_clk,
+       &pllc1_div2_clk,
+       &pllc2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+       unsigned long value;
+
+       /* set KICK bit in FRQCRB to update hardware setting */
+       value = __raw_readl(FRQCRB);
+       value |= (1 << 31);
+       __raw_writel(value, FRQCRB);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                         24, 32, 36, 48, 0, 72, 96, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+       .divisors = divisors,
+       .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+       .div_mult_table = &div4_div_mult_table,
+       .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
+       DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
+       DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
+       DIV4_DDRP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+       [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
+       [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
+       [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
+       [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
+       [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
+       [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
+       [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
+       [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
+       [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
+       [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
+       [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
+};
+
+enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
+       DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
+       DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
+       DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+       [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
+       [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
+       [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
+       [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
+       [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
+       [DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
+       [DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
+       [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
+       [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
+       [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
+       [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
+       [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
+       [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
+};
+
+enum { DIV6_HDMI, DIV6_REPARENT_NR };
+
+/* Indices are important - they are the actual src selecting values */
+static struct clk *hdmi_parent[] = {
+       [0] = &pllc1_div2_clk,
+       [1] = &pllc2_clk,
+       [2] = &dv_clki_clk,
+       [3] = NULL,     /* pllc2_div4 not implemented yet */
+};
+
+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
+       [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
+                                     hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
+};
+
+enum { MSTP001,
+       MSTP131, MSTP130,
+       MSTP129, MSTP128,
+       MSTP118, MSTP117, MSTP116,
+       MSTP106, MSTP101, MSTP100,
+       MSTP223,
+       MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
+       MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
+       MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[MSTP_NR] = {
+       [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
+       [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
+       [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
+       [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
+       [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
+       [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
+       [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
+       [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+       [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
+       [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
+       [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
+       [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
+       [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+       [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+       [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+       [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+       [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+       [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+       [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+       [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+       [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, CLK_ENABLE_ON_INIT), /* FSIA */
+       [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
+       [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
+       [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
+       [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
+       [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
+       [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
+       [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
+       [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
+       [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
+       [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
+       [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+       /* main clocks */
+       CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk),
+       CLKDEV_CON_ID("r_clk", &r_clk),
+       CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
+       CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
+       CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
+       CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
+       CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
+       CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
+       CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
+       CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
+       CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
+
+       /* DIV4 clocks */
+       CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
+       CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
+       CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
+       CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
+       CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
+       CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
+       CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
+       CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
+       CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
+       CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
+       CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
+       CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
+       CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
+       CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
+       CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
+
+       /* DIV6 clocks */
+       CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+       CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+       CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+       CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
+       CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
+       CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
+       CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
+       CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
+       CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
+       CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
+       CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
+       CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
+       CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
+       CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
+
+       /* MSTP32 clocks */
+       CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
+       CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
+       CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
+       CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
+       CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+       CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
+       CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+       CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+       CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+       CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+       CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+       CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
+       CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
+       CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
+       CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP323]), /* USB0 */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+       CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
+       CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
+       CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
+       CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
+       CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
+       CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+       {.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
+};
+
+void __init sh7372_clock_init(void)
+{
+       int k, ret = 0;
+
+       for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+               ret = clk_register(main_clks[k]);
+
+       if (!ret)
+               ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+       if (!ret)
+               ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+       if (!ret)
+               ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR);
+
+       if (!ret)
+               ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+       if (!ret)
+               clk_init();
+       else
+               panic("failed to setup sh7372 clocks\n");
+
+}
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
new file mode 100644 (file)
index 0000000..e007c28
--- /dev/null
@@ -0,0 +1,369 @@
+/*
+ * SH7377 clock framework support
+ *
+ * Copyright (C) 2010 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <mach/common.h>
+#include <asm/clkdev.h>
+
+/* SH7377 registers */
+#define RTFRQCR    0xe6150000
+#define SYFRQCR    0xe6150004
+#define CMFRQCR    0xe61500E0
+#define VCLKCR1    0xe6150008
+#define VCLKCR2    0xe615000C
+#define VCLKCR3    0xe615001C
+#define FMSICKCR   0xe6150010
+#define FMSOCKCR   0xe6150014
+#define FSICKCR    0xe6150018
+#define PLLC1CR    0xe6150028
+#define PLLC2CR    0xe615002C
+#define SUBUSBCKCR 0xe6150080
+#define SPUCKCR    0xe6150084
+#define MSUCKCR    0xe6150088
+#define MVI3CKCR   0xe6150090
+#define HDMICKCR   0xe6150094
+#define MFCK1CR    0xe6150098
+#define MFCK2CR    0xe615009C
+#define DSITCKCR   0xe6150060
+#define DSIPCKCR   0xe6150064
+#define SMSTPCR0   0xe6150130
+#define SMSTPCR1   0xe6150134
+#define SMSTPCR2   0xe6150138
+#define SMSTPCR3   0xe615013C
+#define SMSTPCR4   0xe6150140
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+       .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTALC1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7377_extalc1_clk = {
+       .rate           = 26666666,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh7377_extal2_clk = {
+       .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+       return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+       .recalc         = div2_recalc,
+};
+
+/* Divide extalc1 by two */
+static struct clk extalc1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh7377_extalc1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &sh7377_extal2_clk,
+};
+
+/* Divide extal2 by four */
+static struct clk extal2_div4_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &extal2_div2_clk,
+};
+
+/* PLLC1 */
+static unsigned long pllc1_recalc(struct clk *clk)
+{
+       unsigned long mult = 1;
+
+       if (__raw_readl(PLLC1CR) & (1 << 14))
+               mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
+
+       return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc1_clk_ops = {
+       .recalc         = pllc1_recalc,
+};
+
+static struct clk pllc1_clk = {
+       .ops            = &pllc1_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &extalc1_div2_clk,
+};
+
+/* Divide PLLC1 by two */
+static struct clk pllc1_div2_clk = {
+       .ops            = &div2_clk_ops,
+       .parent         = &pllc1_clk,
+};
+
+/* PLLC2 */
+static unsigned long pllc2_recalc(struct clk *clk)
+{
+       unsigned long mult = 1;
+
+       if (__raw_readl(PLLC2CR) & (1 << 31))
+               mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
+
+       return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc2_clk_ops = {
+       .recalc         = pllc2_recalc,
+};
+
+static struct clk pllc2_clk = {
+       .ops            = &pllc2_clk_ops,
+       .flags          = CLK_ENABLE_ON_INIT,
+       .parent         = &extalc1_div2_clk,
+};
+
+static struct clk *main_clks[] = {
+       &r_clk,
+       &sh7377_extalc1_clk,
+       &sh7377_extal2_clk,
+       &extalc1_div2_clk,
+       &extal2_div2_clk,
+       &extal2_div4_clk,
+       &pllc1_clk,
+       &pllc1_div2_clk,
+       &pllc2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+       unsigned long value;
+
+       /* set KICK bit in SYFRQCR to update hardware setting */
+       value = __raw_readl(SYFRQCR);
+       value |= (1 << 31);
+       __raw_writel(value, SYFRQCR);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                         24, 32, 36, 48, 0, 72, 96, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+       .divisors = divisors,
+       .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+       .div_mult_table = &div4_div_mult_table,
+       .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
+       DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
+       DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+       [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
+       [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
+       [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
+       [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
+       [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
+       [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
+       [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
+       [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
+       [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
+       [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
+};
+
+enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
+       DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
+       DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
+       DIV6_NR };
+
+static struct clk div6_clks[] = {
+       [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
+       [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
+       [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
+       [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
+       [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
+       [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
+       [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
+       [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
+       [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
+       [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
+       [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
+       [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
+       [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
+       [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
+       [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
+};
+
+enum { MSTP001,
+       MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
+       MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+       MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
+       MSTP315, MSTP314, MSTP313,
+       MSTP403,
+       MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+  SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[] = {
+       [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
+       [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
+       [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
+       [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
+       [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
+       [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+       [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
+       [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
+       [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
+       [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+       [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+       [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+       [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+       [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+       [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+       [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+       [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
+       [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+       [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
+       [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
+       [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
+       [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
+       [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
+       [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
+       [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+       /* main clocks */
+       CLKDEV_CON_ID("r_clk", &r_clk),
+       CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
+       CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
+       CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
+       CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
+       CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
+       CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
+       CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
+       CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
+
+       /* DIV4 clocks */
+       CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
+       CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
+       CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
+       CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
+       CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
+       CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
+       CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
+       CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
+       CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
+       CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
+       CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
+       CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
+       CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
+
+       /* DIV6 clocks */
+       CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
+       CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
+       CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+       CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
+       CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
+       CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
+       CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
+       CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
+       CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
+       CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
+       CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
+       CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
+       CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
+       CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
+       CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
+
+       /* MSTP32 clocks */
+       CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
+       CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
+       CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
+       CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+       CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
+       CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+       CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+       CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+       CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+       CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+       CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
+       CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
+       CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
+       CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
+       CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
+       CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
+       CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+       CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+       CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+};
+
+void __init sh7377_clock_init(void)
+{
+       int k, ret = 0;
+
+       for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+               ret = clk_register(main_clks[k]);
+
+       if (!ret)
+               ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+       if (!ret)
+               ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+       if (!ret)
+               ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+       if (!ret)
+               clk_init();
+       else
+               panic("failed to setup sh7377 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
new file mode 100644 (file)
index 0000000..b7c705a
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * SH-Mobile Timer
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sh_clk.h>
+
+int __init clk_init(void)
+{
+       /* Kick the child clocks.. */
+       recalculate_root_clocks();
+
+       /* Enable the necessary init clocks */
+       clk_enable_init_clocks();
+
+       return 0;
+}
+
+int __clk_get(struct clk *clk)
+{
+       return 1;
+}
+EXPORT_SYMBOL(__clk_get);
+
+void __clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(__clk_put);
index 57903605cc51aa45ce4f56c5c2107fb9b86ec850..efeef778a875fa0f20c934090f6fc6fda1663862 100644 (file)
@@ -3,21 +3,31 @@
 
 extern struct sys_timer shmobile_timer;
 extern void shmobile_setup_console(void);
+struct clk;
+extern int clk_init(void);
 
 extern void sh7367_init_irq(void);
 extern void sh7367_add_early_devices(void);
 extern void sh7367_add_standard_devices(void);
 extern void sh7367_clock_init(void);
 extern void sh7367_pinmux_init(void);
+extern struct clk sh7367_extalb1_clk;
+extern struct clk sh7367_extal2_clk;
 
 extern void sh7377_init_irq(void);
 extern void sh7377_add_early_devices(void);
 extern void sh7377_add_standard_devices(void);
+extern void sh7377_clock_init(void);
 extern void sh7377_pinmux_init(void);
+extern struct clk sh7377_extalc1_clk;
+extern struct clk sh7377_extal2_clk;
 
 extern void sh7372_init_irq(void);
 extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
+extern void sh7372_clock_init(void);
 extern void sh7372_pinmux_init(void);
+extern struct clk sh7372_extal1_clk;
+extern struct clk sh7372_extal2_clk;
 
 #endif /* __ARCH_MACH_COMMON_H */
index 132256bb8c817b1b5ab9aa08cd1af7875b22ca00..fa15b5f8a001127ca114b3fef16c39984adf88e1 100644 (file)
@@ -3,7 +3,13 @@
 
 #define NR_IRQS         512
 
+/* INTCA */
 #define evt2irq(evt)           (((evt) >> 5) - 16)
 #define irq2evt(irq)           (((irq) + 16) << 5)
 
+/* INTCS */
+#define INTCS_VECT_BASE                0x2200
+#define INTCS_VECT(n, vect)    INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt)     evt2irq(INTCS_VECT_BASE + (evt))
+
 #endif /* __ASM_MACH_IRQS_H */
index e188183f4dcee49ed7e6d5f7e5837d43cea3da00..377584e57e03121777fd0c7a4c723c596b333a4d 100644 (file)
@@ -4,4 +4,7 @@
 #define PHYS_OFFSET    UL(CONFIG_MEMORY_START)
 #define MEM_SIZE       UL(CONFIG_MEMORY_SIZE)
 
+/* DMA memory at 0xf6000000 - 0xffdfffff */
+#define CONSISTENT_DMA_SIZE (158 << 20)
+
 #endif /* __ASM_MACH_MEMORY_H */
index dc34f00c56b80e9ab9a31cd4dbc77b14d111772f..33e9700ded7e693fe4f3560dea4c1c50bcb43e98 100644 (file)
@@ -11,6 +11,8 @@
 #ifndef __ASM_SH7372_H__
 #define __ASM_SH7372_H__
 
+#include <linux/sh_clk.h>
+
 /*
  * Pin Function Controller:
  *     GPIO_FN_xx - GPIO used to select pin function
@@ -431,4 +433,32 @@ enum {
        GPIO_FN_SDENC_DV_CLKI,
 };
 
+/* DMA slave IDs */
+enum {
+       SHDMA_SLAVE_SCIF0_TX,
+       SHDMA_SLAVE_SCIF0_RX,
+       SHDMA_SLAVE_SCIF1_TX,
+       SHDMA_SLAVE_SCIF1_RX,
+       SHDMA_SLAVE_SCIF2_TX,
+       SHDMA_SLAVE_SCIF2_RX,
+       SHDMA_SLAVE_SCIF3_TX,
+       SHDMA_SLAVE_SCIF3_RX,
+       SHDMA_SLAVE_SCIF4_TX,
+       SHDMA_SLAVE_SCIF4_RX,
+       SHDMA_SLAVE_SCIF5_TX,
+       SHDMA_SLAVE_SCIF5_RX,
+       SHDMA_SLAVE_SCIF6_TX,
+       SHDMA_SLAVE_SCIF6_RX,
+       SHDMA_SLAVE_SDHI0_RX,
+       SHDMA_SLAVE_SDHI0_TX,
+       SHDMA_SLAVE_SDHI1_RX,
+       SHDMA_SLAVE_SDHI1_TX,
+       SHDMA_SLAVE_SDHI2_RX,
+       SHDMA_SLAVE_SDHI2_TX,
+};
+
+extern struct clk dv_clki_clk;
+extern struct clk dv_clki_div2_clk;
+extern struct clk pllc2_clk;
+
 #endif /* __ASM_SH7372_H__ */
index fb3c4f1ab25227bf64d697c3260a427221b4903a..4aecf6e3a859f801111fafa328a44b3d0de3b311 100644 (file)
@@ -1,6 +1,7 @@
 #ifndef __ASM_MACH_VMALLOC_H
 #define __ASM_MACH_VMALLOC_H
 
-#define VMALLOC_END       (PAGE_OFFSET + 0x24000000)
+/* Vmalloc at ... - 0xe5ffffff */
+#define VMALLOC_END 0xe6000000
 
 #endif /* __ASM_MACH_VMALLOC_H */
index 5ff70cadfc32045caf2d126e42a8c7c66df1e7a3..1a20c489b20d5e52e8e4debebad1206844e6c5af 100644 (file)
@@ -75,7 +75,7 @@ enum {
        ETM11, ARM11, USBHS, FLCTL, IIC1
 };
 
-static struct intc_vect intca_vectors[] = {
+static struct intc_vect intca_vectors[] __initdata = {
        INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
        INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
        INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
@@ -162,7 +162,7 @@ static struct intc_group intca_groups[] __initdata = {
        INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
 };
 
-static struct intc_mask_reg intca_mask_registers[] = {
+static struct intc_mask_reg intca_mask_registers[] __initdata = {
        { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
        { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
@@ -211,7 +211,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
            MISTY, CMT3, RWDT1, RWDT0 } },
 };
 
-static struct intc_prio_reg intca_prio_registers[] = {
+static struct intc_prio_reg intca_prio_registers[] __initdata = {
        { 0xe6900010, 0, 32, 4, /* INTPRI00A */
          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
        { 0xe6900014, 0, 32, 4, /* INTPRI10A */
@@ -263,8 +263,178 @@ static struct intc_desc intca_desc __initdata = {
                           intca_sense_registers, intca_ack_registers),
 };
 
+enum {
+       UNUSED_INTCS = 0,
+
+       INTCS,
+
+       /* interrupt sources INTCS */
+       VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
+       VIO3_VOU,
+       RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
+       VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
+       VPU,
+       SGX530,
+       _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
+       IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
+       IPMMU_IPMMUB, IPMMU_IPMMUS,
+       RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
+       MSIOF,
+       IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
+       TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
+       CMT,
+       TSIF,
+       IPMMUI,
+       MVI3,
+       ICB,
+       PEP,
+       ASA,
+       BEM,
+       VE2HO,
+       HQE,
+       JPEG,
+       LCDC,
+
+       /* interrupt groups INTCS */
+       _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
+};
+
+static struct intc_vect intcs_vectors[] = {
+       INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
+       INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
+       INTCS_VECT(VIO3_VOU, 0x780),
+       INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
+       INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
+       INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
+       INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
+       INTCS_VECT(VPU, 0x980),
+       INTCS_VECT(SGX530, 0x9e0),
+       INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
+       INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
+       INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
+       INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
+       INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
+       INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
+       INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
+       INTCS_VECT(MSIOF, 0xd20),
+       INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
+       INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
+       INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
+       INTCS_VECT(TMU_TUNI2, 0xec0),
+       INTCS_VECT(CMT, 0xf00),
+       INTCS_VECT(TSIF, 0xf20),
+       INTCS_VECT(IPMMUI, 0xf60),
+       INTCS_VECT(MVI3, 0x420),
+       INTCS_VECT(ICB, 0x480),
+       INTCS_VECT(PEP, 0x4a0),
+       INTCS_VECT(ASA, 0x4c0),
+       INTCS_VECT(BEM, 0x4e0),
+       INTCS_VECT(VE2HO, 0x520),
+       INTCS_VECT(HQE, 0x540),
+       INTCS_VECT(JPEG, 0x560),
+       INTCS_VECT(LCDC, 0x580),
+
+       INTC_VECT(INTCS, 0xf80),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+       INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
+                  _2DDMAC_2DDM2, _2DDMAC_2DDM3),
+       INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
+                  RTDMAC_1_DEI2, RTDMAC_1_DEI3),
+       INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
+       INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
+       INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
+       INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
+       INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
+       INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+       { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
+         { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
+           VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
+       { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
+         { VIO3_VOU, 0, VE2HO, VPU,
+           0, 0, 0, 0 } },
+       { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
+         { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
+           BEM, ASA, PEP, ICB } },
+       { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
+         { 0, 0, MVI3, 0,
+           JPEG, HQE, 0, LCDC } },
+       { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
+         { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
+           RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
+       { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
+         { 0, 0, MSIOF, 0,
+           SGX530, 0, 0, 0 } },
+       { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
+         { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
+           0, 0, 0, 0 } },
+       { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
+         { 0, 0, 0, CMT,
+           IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
+       { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
+         { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
+           0, 0, 0, 0 } },
+       { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
+         { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
+           0, 0, IPMMUI, TSIF } },
+       { 0xffd20104, 0, 16, /* INTAMASK */
+         { 0, 0, 0, 0, 0, 0, 0, 0,
+           0, 0, 0, 0, 0, 0, 0, INTCS } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+       { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
+       { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
+       { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
+       { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
+       { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
+       { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
+                                             TMU_TUNI2, 0 } },
+       { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
+       { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
+       { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
+       { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
+       { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
+       { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+       [0] = {
+               .start  = 0xffd20000,
+               .end    = 0xffd2ffff,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+       .name = "sh7367-intcs",
+       .resource = intcs_resources,
+       .num_resources = ARRAY_SIZE(intcs_resources),
+       .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                          intcs_prio_registers, NULL, NULL),
+};
+
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+       void __iomem *reg = (void *)get_irq_data(irq);
+       unsigned int evtcodeas = ioread32(reg);
+
+       generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+
 void __init sh7367_init_irq(void)
 {
-       /* INTCA */
+       void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
        register_intc_controller(&intca_desc);
+       register_intc_controller(&intcs_desc);
+
+       /* demux using INTEVTSA */
+       set_irq_data(evt2irq(0xf80), (void *)intevtsa);
+       set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
 }
index 3ce9d9bd5899e356d13917794fe8648c3f45426c..e3551b56cd03f489cd6196887ac2edb8fff3db1c 100644 (file)
@@ -319,17 +319,17 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
        { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
        { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
                                               CMT14, CMT15 } },
-       { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
+       { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
                                               MMC_MMC_ERR, MMC_MMC_NOR } },
-       { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
+       { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
                                               IIC4_WAITI4, IIC4_DTEI4 } },
-       { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
+       { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
                                               IIC3_WAITI3, IIC3_DTEI3 } },
-       { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
+       { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
                                               0/*TXI*/, 0/*TEI*/} },
-       { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
+       { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
                                               USB1_USB1I1, USB1_USB1I0 } },
-       { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
+       { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
 };
 
 static struct intc_sense_reg intca_sense_registers[] __initdata = {
@@ -363,7 +363,227 @@ static struct intc_desc intca_desc __initdata = {
                           intca_sense_registers, intca_ack_registers),
 };
 
+enum {
+       UNUSED_INTCS = 0,
+
+       INTCS,
+
+       /* interrupt sources INTCS */
+       VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
+       RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
+       CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
+       VPU,
+       TSIF1,
+       _3DG_SGX530,
+       _2DDMAC,
+       IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
+       IPMMU_IPMMUR, IPMMU_IPMMUR2,
+       RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
+       MSIOF,
+       IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
+       TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
+       CMT0,
+       TSIF0,
+       LMB,
+       CTI,
+       ICB,
+       JPU_JPEG,
+       LCDC,
+       LCRC,
+       RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
+       RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
+       ISP,
+       LCDC1,
+       CSIRX,
+       DSITX_DSITX0,
+       DSITX_DSITX1,
+       TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
+       CMT4,
+       DSITX1_DSITX1_0,
+       DSITX1_DSITX1_1,
+       CPORTS2R,
+       JPU6E,
+
+       /* interrupt groups INTCS */
+       RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
+       RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
+};
+
+static struct intc_vect intcs_vectors[] = {
+       INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
+       INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
+       INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
+       INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
+       INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
+       INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
+       INTCS_VECT(VPU, 0x980),
+       INTCS_VECT(TSIF1, 0x9a0),
+       INTCS_VECT(_3DG_SGX530, 0x9e0),
+       INTCS_VECT(_2DDMAC, 0xa00),
+       INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
+       INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
+       INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
+       INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
+       INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
+       INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
+       INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
+       INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
+       INTCS_VECT(TMU_TUNI2, 0xec0),
+       INTCS_VECT(CMT0, 0xf00),
+       INTCS_VECT(TSIF0, 0xf20),
+       INTCS_VECT(LMB, 0xf60),
+       INTCS_VECT(CTI, 0x400),
+       INTCS_VECT(ICB, 0x480),
+       INTCS_VECT(JPU_JPEG, 0x560),
+       INTCS_VECT(LCDC, 0x580),
+       INTCS_VECT(LCRC, 0x5a0),
+       INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
+       INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
+       INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
+       INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
+       INTCS_VECT(ISP, 0x1720),
+       INTCS_VECT(LCDC1, 0x1780),
+       INTCS_VECT(CSIRX, 0x17a0),
+       INTCS_VECT(DSITX_DSITX0, 0x17c0),
+       INTCS_VECT(DSITX_DSITX1, 0x17e0),
+       INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
+       INTCS_VECT(TMU1_TUNI2, 0x1940),
+       INTCS_VECT(CMT4, 0x1980),
+       INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
+       INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
+       INTCS_VECT(CPORTS2R, 0x1a20),
+       INTCS_VECT(JPU6E, 0x1a80),
+
+       INTC_VECT(INTCS, 0xf80),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+       INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
+                  RTDMAC_1_DEI2, RTDMAC_1_DEI3),
+       INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
+       INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
+       INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
+       INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
+       INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
+       INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
+       INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
+                  RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
+       INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
+                  RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
+       INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
+       INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+       { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
+         { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
+           VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
+       { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
+         { 0, 0, 0, VPU,
+           0, 0, 0, 0 } },
+       { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
+         { 0, 0, 0, _2DDMAC,
+           0, 0, 0, ICB } },
+       { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
+         { 0, 0, 0, CTI,
+           JPU_JPEG, 0, LCRC, LCDC } },
+       { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
+         { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
+           RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
+       { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
+         { 0, 0, MSIOF, 0,
+           _3DG_SGX530, 0, 0, 0 } },
+       { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
+         { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
+           0, 0, 0, 0 } },
+       { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
+         { 0, 0, 0, CMT0,
+           IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
+       { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
+         { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
+           0, 0, 0, 0 } },
+       { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
+         { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
+           0, TSIF1, LMB, TSIF0 } },
+       { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
+         { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
+           RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
+       { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
+         { 0, ISP, 0, 0,
+           LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
+       { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
+         { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
+           CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
+       { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
+         { 0, CPORTS2R, 0, 0,
+           JPU6E, 0, 0, 0 } },
+       { 0xffd20104, 0, 16, /* INTAMASK */
+         { 0, 0, 0, 0, 0, 0, 0, 0,
+           0, 0, 0, 0, 0, 0, 0, INTCS } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+       { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
+       { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
+       { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
+       { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
+       { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
+                                             TMU_TUNI2, TSIF1 } },
+       { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
+       { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
+       { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
+       { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
+       { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
+       { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
+       { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
+       { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
+       { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
+       { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
+       { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
+       { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
+                                              DSITX1_DSITX1_1, 0 } },
+       { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0, CPORTS2R, 0, 0 } },
+       { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+       [0] = {
+               .start  = 0xffd20000,
+               .end    = 0xffd201ff,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = 0xffd50000,
+               .end    = 0xffd501ff,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+       .name = "sh7372-intcs",
+       .resource = intcs_resources,
+       .num_resources = ARRAY_SIZE(intcs_resources),
+       .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                          intcs_prio_registers, NULL, NULL),
+};
+
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+       void __iomem *reg = (void *)get_irq_data(irq);
+       unsigned int evtcodeas = ioread32(reg);
+
+       generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+
 void __init sh7372_init_irq(void)
 {
+       void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
        register_intc_controller(&intca_desc);
+       register_intc_controller(&intcs_desc);
+
+       /* demux using INTEVTSA */
+       set_irq_data(evt2irq(0xf80), (void *)intevtsa);
+       set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
 }
index 5c781e2d1897e04ac4756fa2be4668087349cf1b..2cdeb8ccd821d3a0869db335dc63ee7bb51b6f89 100644 (file)
@@ -90,7 +90,7 @@ enum {
        ICUSB, ICUDMC
 };
 
-static struct intc_vect intca_vectors[] = {
+static struct intc_vect intca_vectors[] __initdata = {
        INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
        INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
        INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
@@ -202,7 +202,7 @@ static struct intc_group intca_groups[] __initdata = {
        INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
 };
 
-static struct intc_mask_reg intca_mask_registers[] = {
+static struct intc_mask_reg intca_mask_registers[] __initdata = {
        { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
        { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
@@ -272,7 +272,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
            SCIFA6, 0, 0, 0 } },
 };
 
-static struct intc_prio_reg intca_prio_registers[] = {
+static struct intc_prio_reg intca_prio_registers[] __initdata = {
        { 0xe6900010, 0, 32, 4, /* INTPRI00A */
          { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
        { 0xe6900014, 0, 32, 4, /* INTPRI10A */
@@ -346,7 +346,301 @@ static struct intc_desc intca_desc __initdata = {
                           intca_sense_registers, intca_ack_registers),
 };
 
+/* this macro ignore entry which is also in INTCA */
+#define __IGNORE(a...)
+#define __IGNORE0(a...) 0
+
+enum {
+       UNUSED_INTCS = 0,
+
+       INTCS,
+
+       /* interrupt sources INTCS */
+       VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
+       RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
+       CEU,
+       BEU_BEU0, BEU_BEU1, BEU_BEU2,
+       __IGNORE(MFI)
+       __IGNORE(BBIF2)
+       VPU,
+       TSIF1,
+       __IGNORE(SGX540)
+       _2DDMAC,
+       IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
+       IPMMU_IPMMUR, IPMMU_IPMMUR2,
+       RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
+       __IGNORE(KEYSC)
+       __IGNORE(TTI20)
+       __IGNORE(MSIOF)
+       IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
+       TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
+       CMT0,
+       TSIF0,
+       __IGNORE(CMT2)
+       LMB,
+       __IGNORE(MSUG)
+       __IGNORE(MSU_MSU, MSU_MSU2)
+       __IGNORE(CTI)
+       MVI3,
+       __IGNORE(RWDT0)
+       __IGNORE(RWDT1)
+       ICB,
+       PEP,
+       ASA,
+       __IGNORE(_2DG)
+       HQE,
+       JPU,
+       LCDC0,
+       __IGNORE(LCRC)
+       RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
+       RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
+       FRC,
+       LCDC1,
+       CSIRX,
+       DSITX_DSITX0, DSITX_DSITX1,
+       __IGNORE(SPU2_SPU0, SPU2_SPU1)
+       __IGNORE(FSI)
+       __IGNORE(FMSI)
+       __IGNORE(SCUV)
+       TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
+       TSIF2,
+       CMT4,
+       __IGNORE(MFIS2)
+       CPORTS2R,
+
+       /* interrupt groups INTCS */
+       RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
+       IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
+};
+
+#define INTCS_INTVECT 0x0F80
+static struct intc_vect intcs_vectors[] __initdata = {
+       INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
+       INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
+       INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
+       INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
+       INTCS_VECT(CEU, 0x0880),
+       INTCS_VECT(BEU_BEU0, 0x08A0),
+       INTCS_VECT(BEU_BEU1, 0x08C0),
+       INTCS_VECT(BEU_BEU2, 0x08E0),
+       __IGNORE(INTCS_VECT(MFI, 0x0900))
+       __IGNORE(INTCS_VECT(BBIF2, 0x0960))
+       INTCS_VECT(VPU, 0x0980),
+       INTCS_VECT(TSIF1, 0x09A0),
+       __IGNORE(INTCS_VECT(SGX540, 0x09E0))
+       INTCS_VECT(_2DDMAC, 0x0A00),
+       INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
+       INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
+       INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
+       INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
+       INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
+       INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
+       __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
+       __IGNORE(INTCS_VECT(TTI20, 0x0C80))
+       __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
+       INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
+       INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
+       INTCS_VECT(TMU_TUNI0, 0x0E80),
+       INTCS_VECT(TMU_TUNI1, 0x0EA0),
+       INTCS_VECT(TMU_TUNI2, 0x0EC0),
+       INTCS_VECT(CMT0, 0x0F00),
+       INTCS_VECT(TSIF0, 0x0F20),
+       __IGNORE(INTCS_VECT(CMT2, 0x0F40))
+       INTCS_VECT(LMB, 0x0F60),
+       __IGNORE(INTCS_VECT(MSUG, 0x0F80))
+       __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
+       __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
+       __IGNORE(INTCS_VECT(CTI, 0x0400))
+       INTCS_VECT(MVI3, 0x0420),
+       __IGNORE(INTCS_VECT(RWDT0, 0x0440))
+       __IGNORE(INTCS_VECT(RWDT1, 0x0460))
+       INTCS_VECT(ICB, 0x0480),
+       INTCS_VECT(PEP, 0x04A0),
+       INTCS_VECT(ASA, 0x04C0),
+       __IGNORE(INTCS_VECT(_2DG, 0x04E0))
+       INTCS_VECT(HQE, 0x0540),
+       INTCS_VECT(JPU, 0x0560),
+       INTCS_VECT(LCDC0, 0x0580),
+       __IGNORE(INTCS_VECT(LCRC, 0x05A0))
+       INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
+       INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
+       INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
+       INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
+       INTCS_VECT(FRC, 0x1700),
+       INTCS_VECT(LCDC1, 0x1780),
+       INTCS_VECT(CSIRX, 0x17A0),
+       INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
+       __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
+       __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
+       __IGNORE(INTCS_VECT(FSI, 0x1840))
+       __IGNORE(INTCS_VECT(FMSI, 0x1860))
+       __IGNORE(INTCS_VECT(SCUV, 0x1880))
+       INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
+       INTCS_VECT(TMU1_TUNI12, 0x1940),
+       INTCS_VECT(TSIF2, 0x1960),
+       INTCS_VECT(CMT4, 0x1980),
+       __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
+       INTCS_VECT(CPORTS2R, 0x1A20),
+
+       INTC_VECT(INTCS, INTCS_INTVECT),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+       INTC_GROUP(RTDMAC1_1,
+                  RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
+                  RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
+       INTC_GROUP(RTDMAC1_2,
+                  RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
+       INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
+       INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
+       INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
+       __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
+       INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
+       INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
+       INTC_GROUP(RTDMAC2_1,
+                  RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
+                  RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
+       INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
+       INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
+       __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
+       INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] __initdata = {
+       { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS  */
+         { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
+           VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
+       { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
+         { 0, 0, 0, VPU,
+           __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
+       { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
+         { 0, 0, 0, _2DDMAC,
+           __IGNORE0(_2DG), ASA, PEP, ICB } },
+       { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
+         { 0, 0, MVI3, __IGNORE0(CTI),
+           JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
+       { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
+         { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
+           RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
+       __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
+         { 0, 0, MSIOF, 0,
+           SGX540, 0, TTI20, 0 } })
+       { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
+         { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
+           0, 0, 0, 0 } },
+       __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
+         { 0, 0, 0, 0,
+           0, MSU_MSU, MSU_MSU2, MSUG } })
+       { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
+         { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
+           IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
+       { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
+         { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
+           0, 0, 0, 0 } },
+       { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
+         { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
+           0, TSIF1, LMB, TSIF0 } },
+       { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
+         { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
+           RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
+       { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
+         { FRC, 0, 0, 0,
+           LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
+       __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
+         {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
+          SCUV, 0, 0, 0 } })
+       { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
+         { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
+           CMT4, 0, 0, 0 } },
+       { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
+         { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
+           0, 0, 0, 0 } },
+       { 0xFFD20104, 0, 16, /* INTAMASK */
+         { 0, 0, 0, 0, 0, 0, 0, 0,
+           0, 0, 0, 0, 0, 0, 0, INTCS } }
+};
+
+static struct intc_prio_reg intcs_prio_registers[] __initdata = {
+       /* IPRAS */
+       { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
+       /* IPRBS */
+       { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
+       /* IPRCS */
+       __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
+       /* IPRES */
+       { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
+       /* IPRFS */
+       { 0xFFD20014, 0, 16, 4,
+         { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
+       /* IPRGS */
+       { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
+       /* IPRHS */
+       { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
+       /* IPRIS */
+       { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
+       /* IPRJS */
+       __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
+       /* IPRKS */
+       { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
+       /* IPRLS */
+       { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
+       /* IPRMS */
+       { 0xFFD20030, 0, 16, 4,
+         { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
+       /* IPRAS3 */
+       { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
+       /* IPRBS3 */
+       { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
+       /* IPRIS3 */
+       { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
+       /* IPRJS3 */
+       { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
+       /* IPRKS3 */
+       __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
+       /* IPRLS3 */
+       __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
+       /* IPRMS3 */
+       { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
+       /* IPRNS3 */
+       { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
+       /* IPROS3 */
+       { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+       [0] = {
+               .start  = 0xffd20000,
+               .end    = 0xffd500ff,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+       .name = "sh7377-intcs",
+       .resource = intcs_resources,
+       .num_resources = ARRAY_SIZE(intcs_resources),
+       .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
+                          intcs_mask_registers, intcs_prio_registers,
+                          NULL, NULL),
+};
+
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+       void __iomem *reg = (void *)get_irq_data(irq);
+       unsigned int evtcodeas = ioread32(reg);
+
+       generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+
+#define INTEVTSA 0xFFD20100
 void __init sh7377_init_irq(void)
 {
+       void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
+
        register_intc_controller(&intca_desc);
+       register_intc_controller(&intcs_desc);
+
+       /* demux using INTEVTSA */
+       set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
+       set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
 }
index 9557d0964d73eae7eeb373bd8e5940eddfc351e2..ec420353f8e3b3289b7d6cfa313c7089a9f8b1eb 100644 (file)
@@ -1160,6 +1160,9 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
 
+       GPIO_FN(LCDC0_SELECT),
+       GPIO_FN(LCDC1_SELECT),
+
        /* IRDA */
        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
index eca90716140e25c69aa3e07d1a71962e7c262e90..3148c11a550e2fa6e28641920aab5a4930b0fe04 100644 (file)
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+/* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
+                           evt2irq(0xc00), evt2irq(0xc00) },
 };
 
 static struct platform_device scif0_device = {
@@ -46,11 +48,13 @@ static struct platform_device scif0_device = {
        },
 };
 
+/* SCIFA1 */
 static struct plat_sci_port scif1_platform_data = {
        .mapbase        = 0xe6c50000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 81, 81, 81, 81 },
+       .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
+                           evt2irq(0xc20), evt2irq(0xc20) },
 };
 
 static struct platform_device scif1_device = {
@@ -61,11 +65,13 @@ static struct platform_device scif1_device = {
        },
 };
 
+/* SCIFA2 */
 static struct plat_sci_port scif2_platform_data = {
        .mapbase        = 0xe6c60000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 82, 82, 82, 82 },
+       .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
+                           evt2irq(0xc40), evt2irq(0xc40) },
 };
 
 static struct platform_device scif2_device = {
@@ -76,11 +82,13 @@ static struct platform_device scif2_device = {
        },
 };
 
+/* SCIFA3 */
 static struct plat_sci_port scif3_platform_data = {
        .mapbase        = 0xe6c70000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 83, 83, 83, 83 },
+       .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
+                           evt2irq(0xc60), evt2irq(0xc60) },
 };
 
 static struct platform_device scif3_device = {
@@ -91,11 +99,13 @@ static struct platform_device scif3_device = {
        },
 };
 
+/* SCIFA4 */
 static struct plat_sci_port scif4_platform_data = {
        .mapbase        = 0xe6c80000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 89, 89, 89, 89 },
+       .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
+                           evt2irq(0xd20), evt2irq(0xd20) },
 };
 
 static struct platform_device scif4_device = {
@@ -106,11 +116,13 @@ static struct platform_device scif4_device = {
        },
 };
 
+/* SCIFA5 */
 static struct plat_sci_port scif5_platform_data = {
        .mapbase        = 0xe6cb0000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 90, 90, 90, 90 },
+       .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
+                           evt2irq(0xd40), evt2irq(0xd40) },
 };
 
 static struct platform_device scif5_device = {
@@ -121,11 +133,13 @@ static struct platform_device scif5_device = {
        },
 };
 
+/* SCIFB */
 static struct plat_sci_port scif6_platform_data = {
        .mapbase        = 0xe6c30000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 91, 91, 91, 91 },
+       .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
+                           evt2irq(0xd60), evt2irq(0xd60) },
 };
 
 static struct platform_device scif6_device = {
@@ -153,7 +167,7 @@ static struct resource cmt10_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 72,
+               .start  = evt2irq(0xb00), /* CMT1_CMT10 */
                .flags  = IORESOURCE_IRQ,
        },
 };
index 1d1153290f594dabdf5d9dc45477a07d24f4db44..e26686c9d0b67b61fff64eabcecce68f0d185ea1 100644 (file)
 #include <linux/input.h>
 #include <linux/io.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
+#include <mach/sh7372.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+/* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
        .flags          = UPF_BOOT_AUTOCONF,
-       .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .type           = PORT_SCIFA,
+       .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
+                           evt2irq(0x0c00), evt2irq(0x0c00) },
 };
 
 static struct platform_device scif0_device = {
@@ -47,11 +51,13 @@ static struct platform_device scif0_device = {
        },
 };
 
+/* SCIFA1 */
 static struct plat_sci_port scif1_platform_data = {
        .mapbase        = 0xe6c50000,
        .flags          = UPF_BOOT_AUTOCONF,
-       .type           = PORT_SCIF,
-       .irqs           = { 81, 81, 81, 81 },
+       .type           = PORT_SCIFA,
+       .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
+                           evt2irq(0x0c20), evt2irq(0x0c20) },
 };
 
 static struct platform_device scif1_device = {
@@ -62,11 +68,13 @@ static struct platform_device scif1_device = {
        },
 };
 
+/* SCIFA2 */
 static struct plat_sci_port scif2_platform_data = {
        .mapbase        = 0xe6c60000,
        .flags          = UPF_BOOT_AUTOCONF,
-       .type           = PORT_SCIF,
-       .irqs           = { 82, 82, 82, 82 },
+       .type           = PORT_SCIFA,
+       .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
+                           evt2irq(0x0c40), evt2irq(0x0c40) },
 };
 
 static struct platform_device scif2_device = {
@@ -77,11 +85,13 @@ static struct platform_device scif2_device = {
        },
 };
 
+/* SCIFA3 */
 static struct plat_sci_port scif3_platform_data = {
        .mapbase        = 0xe6c70000,
        .flags          = UPF_BOOT_AUTOCONF,
-       .type           = PORT_SCIF,
-       .irqs           = { 83, 83, 83, 83 },
+       .type           = PORT_SCIFA,
+       .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
+                           evt2irq(0x0c60), evt2irq(0x0c60) },
 };
 
 static struct platform_device scif3_device = {
@@ -92,11 +102,13 @@ static struct platform_device scif3_device = {
        },
 };
 
+/* SCIFA4 */
 static struct plat_sci_port scif4_platform_data = {
        .mapbase        = 0xe6c80000,
        .flags          = UPF_BOOT_AUTOCONF,
-       .type           = PORT_SCIF,
-       .irqs           = { 89, 89, 89, 89 },
+       .type           = PORT_SCIFA,
+       .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
+                           evt2irq(0x0d20), evt2irq(0x0d20) },
 };
 
 static struct platform_device scif4_device = {
@@ -107,11 +119,13 @@ static struct platform_device scif4_device = {
        },
 };
 
+/* SCIFA5 */
 static struct plat_sci_port scif5_platform_data = {
        .mapbase        = 0xe6cb0000,
        .flags          = UPF_BOOT_AUTOCONF,
-       .type           = PORT_SCIF,
-       .irqs           = { 90, 90, 90, 90 },
+       .type           = PORT_SCIFA,
+       .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
+                           evt2irq(0x0d40), evt2irq(0x0d40) },
 };
 
 static struct platform_device scif5_device = {
@@ -122,11 +136,13 @@ static struct platform_device scif5_device = {
        },
 };
 
+/* SCIFB */
 static struct plat_sci_port scif6_platform_data = {
        .mapbase        = 0xe6c30000,
        .flags          = UPF_BOOT_AUTOCONF,
-       .type           = PORT_SCIF,
-       .irqs           = { 91, 91, 91, 91 },
+       .type           = PORT_SCIFB,
+       .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
+                           evt2irq(0x0d60), evt2irq(0x0d60) },
 };
 
 static struct platform_device scif6_device = {
@@ -137,11 +153,12 @@ static struct platform_device scif6_device = {
        },
 };
 
+/* CMT */
 static struct sh_timer_config cmt10_platform_data = {
        .name = "CMT10",
        .channel_offset = 0x10,
        .timer_bit = 0,
-       .clk = "r_clk",
+       .clk = "cmt1",
        .clockevent_rating = 125,
        .clocksource_rating = 125,
 };
@@ -154,7 +171,7 @@ static struct resource cmt10_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 72,
+               .start  = evt2irq(0x0b00), /* CMT1_CMT10 */
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -169,6 +186,337 @@ static struct platform_device cmt10_device = {
        .num_resources  = ARRAY_SIZE(cmt10_resources),
 };
 
+/* I2C */
+static struct resource iic0_resources[] = {
+       [0] = {
+               .name   = "IIC0",
+               .start  = 0xFFF20000,
+               .end    = 0xFFF20425 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
+               .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic0_device = {
+       .name           = "i2c-sh_mobile",
+       .id             = 0, /* "i2c0" clock */
+       .num_resources  = ARRAY_SIZE(iic0_resources),
+       .resource       = iic0_resources,
+};
+
+static struct resource iic1_resources[] = {
+       [0] = {
+               .name   = "IIC1",
+               .start  = 0xE6C20000,
+               .end    = 0xE6C20425 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = evt2irq(0x780), /* IIC1_ALI1 */
+               .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device iic1_device = {
+       .name           = "i2c-sh_mobile",
+       .id             = 1, /* "i2c1" clock */
+       .num_resources  = ARRAY_SIZE(iic1_resources),
+       .resource       = iic1_resources,
+};
+
+/* DMA */
+/* Transmit sizes and respective CHCR register values */
+enum {
+       XMIT_SZ_8BIT            = 0,
+       XMIT_SZ_16BIT           = 1,
+       XMIT_SZ_32BIT           = 2,
+       XMIT_SZ_64BIT           = 7,
+       XMIT_SZ_128BIT          = 3,
+       XMIT_SZ_256BIT          = 4,
+       XMIT_SZ_512BIT          = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT {                     \
+       [XMIT_SZ_8BIT]          = 0,    \
+       [XMIT_SZ_16BIT]         = 1,    \
+       [XMIT_SZ_32BIT]         = 2,    \
+       [XMIT_SZ_64BIT]         = 3,    \
+       [XMIT_SZ_128BIT]        = 4,    \
+       [XMIT_SZ_256BIT]        = 5,    \
+       [XMIT_SZ_512BIT]        = 6,    \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
+                        (((i) & 0xc) << (20 - 2)))
+
+static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
+       {
+               .slave_id       = SHDMA_SLAVE_SCIF0_TX,
+               .addr           = 0xe6c40020,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x21,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF0_RX,
+               .addr           = 0xe6c40024,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x22,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF1_TX,
+               .addr           = 0xe6c50020,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x25,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF1_RX,
+               .addr           = 0xe6c50024,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x26,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+               .addr           = 0xe6c60020,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x29,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+               .addr           = 0xe6c60024,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x2a,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF3_TX,
+               .addr           = 0xe6c70020,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x2d,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF3_RX,
+               .addr           = 0xe6c70024,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x2e,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF4_TX,
+               .addr           = 0xe6c80020,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x39,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF4_RX,
+               .addr           = 0xe6c80024,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x3a,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF5_TX,
+               .addr           = 0xe6cb0020,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x35,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF5_RX,
+               .addr           = 0xe6cb0024,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x36,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF6_TX,
+               .addr           = 0xe6c30040,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x3d,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SCIF6_RX,
+               .addr           = 0xe6c30060,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+               .mid_rid        = 0x3e,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI0_TX,
+               .addr           = 0xe6850030,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+               .mid_rid        = 0xc1,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI0_RX,
+               .addr           = 0xe6850030,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+               .mid_rid        = 0xc2,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI1_TX,
+               .addr           = 0xe6860030,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+               .mid_rid        = 0xc9,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI1_RX,
+               .addr           = 0xe6860030,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+               .mid_rid        = 0xca,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI2_TX,
+               .addr           = 0xe6870030,
+               .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+               .mid_rid        = 0xcd,
+       }, {
+               .slave_id       = SHDMA_SLAVE_SDHI2_RX,
+               .addr           = 0xe6870030,
+               .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+               .mid_rid        = 0xce,
+       },
+};
+
+static const struct sh_dmae_channel sh7372_dmae_channels[] = {
+       {
+               .offset = 0,
+               .dmars = 0,
+               .dmars_bit = 0,
+       }, {
+               .offset = 0x10,
+               .dmars = 0,
+               .dmars_bit = 8,
+       }, {
+               .offset = 0x20,
+               .dmars = 4,
+               .dmars_bit = 0,
+       }, {
+               .offset = 0x30,
+               .dmars = 4,
+               .dmars_bit = 8,
+       }, {
+               .offset = 0x50,
+               .dmars = 8,
+               .dmars_bit = 0,
+       }, {
+               .offset = 0x60,
+               .dmars = 8,
+               .dmars_bit = 8,
+       }
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma_platform_data = {
+       .slave          = sh7372_dmae_slaves,
+       .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
+       .channel        = sh7372_dmae_channels,
+       .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
+       .ts_low_shift   = 3,
+       .ts_low_mask    = 0x18,
+       .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
+       .ts_high_mask   = 0x00300000,
+       .ts_shift       = ts_shift,
+       .ts_shift_num   = ARRAY_SIZE(ts_shift),
+       .dmaor_init     = DMAOR_DME,
+};
+
+/* Resource order important! */
+static struct resource sh7372_dmae0_resources[] = {
+       {
+               /* Channel registers and DMAOR */
+               .start  = 0xfe008020,
+               .end    = 0xfe00808f,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               /* DMARSx */
+               .start  = 0xfe009000,
+               .end    = 0xfe00900b,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               /* DMA error IRQ */
+               .start  = 246,
+               .end    = 246,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               /* IRQ for channels 0-5 */
+               .start  = 240,
+               .end    = 245,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+/* Resource order important! */
+static struct resource sh7372_dmae1_resources[] = {
+       {
+               /* Channel registers and DMAOR */
+               .start  = 0xfe018020,
+               .end    = 0xfe01808f,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               /* DMARSx */
+               .start  = 0xfe019000,
+               .end    = 0xfe01900b,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               /* DMA error IRQ */
+               .start  = 254,
+               .end    = 254,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               /* IRQ for channels 0-5 */
+               .start  = 248,
+               .end    = 253,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+/* Resource order important! */
+static struct resource sh7372_dmae2_resources[] = {
+       {
+               /* Channel registers and DMAOR */
+               .start  = 0xfe028020,
+               .end    = 0xfe02808f,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               /* DMARSx */
+               .start  = 0xfe029000,
+               .end    = 0xfe02900b,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               /* DMA error IRQ */
+               .start  = 262,
+               .end    = 262,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               /* IRQ for channels 0-5 */
+               .start  = 256,
+               .end    = 261,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device dma0_device = {
+       .name           = "sh-dma-engine",
+       .id             = 0,
+       .resource       = sh7372_dmae0_resources,
+       .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
+       .dev            = {
+               .platform_data  = &dma_platform_data,
+       },
+};
+
+static struct platform_device dma1_device = {
+       .name           = "sh-dma-engine",
+       .id             = 1,
+       .resource       = sh7372_dmae1_resources,
+       .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
+       .dev            = {
+               .platform_data  = &dma_platform_data,
+       },
+};
+
+static struct platform_device dma2_device = {
+       .name           = "sh-dma-engine",
+       .id             = 2,
+       .resource       = sh7372_dmae2_resources,
+       .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
+       .dev            = {
+               .platform_data  = &dma_platform_data,
+       },
+};
+
 static struct platform_device *sh7372_early_devices[] __initdata = {
        &scif0_device,
        &scif1_device,
@@ -178,6 +526,11 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
        &scif5_device,
        &scif6_device,
        &cmt10_device,
+       &iic0_device,
+       &iic1_device,
+       &dma0_device,
+       &dma1_device,
+       &dma2_device,
 };
 
 void __init sh7372_add_standard_devices(void)
@@ -186,14 +539,8 @@ void __init sh7372_add_standard_devices(void)
                            ARRAY_SIZE(sh7372_early_devices));
 }
 
-#define SMSTPCR3 0xe615013c
-#define SMSTPCR3_CMT1 (1 << 29)
-
 void __init sh7372_add_early_devices(void)
 {
-       /* enable clock to CMT1 */
-       __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
-
        early_platform_add_devices(sh7372_early_devices,
                                   ARRAY_SIZE(sh7372_early_devices));
 }
index 60e37774c35c20d28c72de9b1aab70aa102012d5..bb4adf17dbf4613f7c388ab711b09a785470c026 100644 (file)
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+/* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xe6c40000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 80, 80, 80, 80 },
+       .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
+                           evt2irq(0xc00), evt2irq(0xc00) },
 };
 
 static struct platform_device scif0_device = {
@@ -47,11 +49,13 @@ static struct platform_device scif0_device = {
        },
 };
 
+/* SCIFA1 */
 static struct plat_sci_port scif1_platform_data = {
        .mapbase        = 0xe6c50000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 81, 81, 81, 81 },
+       .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
+                           evt2irq(0xc20), evt2irq(0xc20) },
 };
 
 static struct platform_device scif1_device = {
@@ -62,11 +66,13 @@ static struct platform_device scif1_device = {
        },
 };
 
+/* SCIFA2 */
 static struct plat_sci_port scif2_platform_data = {
        .mapbase        = 0xe6c60000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 82, 82, 82, 82 },
+       .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
+                           evt2irq(0xc40), evt2irq(0xc40) },
 };
 
 static struct platform_device scif2_device = {
@@ -77,11 +83,13 @@ static struct platform_device scif2_device = {
        },
 };
 
+/* SCIFA3 */
 static struct plat_sci_port scif3_platform_data = {
        .mapbase        = 0xe6c70000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 83, 83, 83, 83 },
+       .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
+                           evt2irq(0xc60), evt2irq(0xc60) },
 };
 
 static struct platform_device scif3_device = {
@@ -92,11 +100,13 @@ static struct platform_device scif3_device = {
        },
 };
 
+/* SCIFA4 */
 static struct plat_sci_port scif4_platform_data = {
        .mapbase        = 0xe6c80000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 89, 89, 89, 89 },
+       .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
+                           evt2irq(0xd20), evt2irq(0xd20) },
 };
 
 static struct platform_device scif4_device = {
@@ -107,11 +117,13 @@ static struct platform_device scif4_device = {
        },
 };
 
+/* SCIFA5 */
 static struct plat_sci_port scif5_platform_data = {
        .mapbase        = 0xe6cb0000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 90, 90, 90, 90 },
+       .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
+                           evt2irq(0xd40), evt2irq(0xd40) },
 };
 
 static struct platform_device scif5_device = {
@@ -122,11 +134,13 @@ static struct platform_device scif5_device = {
        },
 };
 
+/* SCIFA6 */
 static struct plat_sci_port scif6_platform_data = {
        .mapbase        = 0xe6cc0000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 196, 196, 196, 196 },
+       .irqs           = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
+                           intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
 };
 
 static struct platform_device scif6_device = {
@@ -137,11 +151,13 @@ static struct platform_device scif6_device = {
        },
 };
 
+/* SCIFB */
 static struct plat_sci_port scif7_platform_data = {
        .mapbase        = 0xe6c30000,
        .flags          = UPF_BOOT_AUTOCONF,
        .type           = PORT_SCIF,
-       .irqs           = { 91, 91, 91, 91 },
+       .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
+                           evt2irq(0xd60), evt2irq(0xd60) },
 };
 
 static struct platform_device scif7_device = {
@@ -169,7 +185,7 @@ static struct resource cmt10_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-               .start  = 72,
+               .start  = evt2irq(0xb00), /* CMT1_CMT10 */
                .flags  = IORESOURCE_IRQ,
        },
 };
index de375b64e410e939a2a011d53a67ecfd97fc7d97..3da116f47f01b732112c50337e6a39183bc9a696 100644 (file)
@@ -154,7 +154,7 @@ static struct platform_device nand_flash_device = {
 #define PORT_DRVCRA    0xA405018A
 #define PORT_DRVCRB    0xA405018C
 
-static void ap320_wvga_power_on(void *board_data)
+static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
 {
        msleep(100);
 
index 4e577a3bf6583ca4200f56f2405e43e90f54b87d..60dd63f4a4272893f069ef70064d2b63a1a4f6f2 100644 (file)
@@ -1,2 +1,4 @@
-obj-y   := setup.o sdram.o
-obj-$(CONFIG_FB_SH_MOBILE_LCDC)        +=  lcd_wqvga.o
+obj-y  := setup.o sdram.o
+ifneq ($(CONFIG_FB_SH_MOBILE_LCDC),)
+obj-y  +=  lcd_wqvga.o
+endif
index e9b970846c41fcb0c96a105ed277059f722a57b3..25e145fb7087c443e525d7726962c2defa49865e 100644 (file)
@@ -327,7 +327,7 @@ static int kfr2r09_lcd_backlight(int on)
        return 0;
 }
 
-void kfr2r09_lcd_on(void *board_data)
+void kfr2r09_lcd_on(void *board_data, struct fb_info *info)
 {
        kfr2r09_lcd_backlight(1);
 }
index 484ef42c2fb5b8d35084f9ef38c9693edadd5a16..07e635b0e04cd4adae2c0c8b5da8e198f231be08 100644 (file)
@@ -3,23 +3,23 @@
 
 #include <video/sh_mobile_lcdc.h>
 
-#ifdef CONFIG_FB_SH_MOBILE_LCDC
-void kfr2r09_lcd_on(void *board_data);
+#if defined(CONFIG_FB_SH_MOBILE_LCDC) || defined(CONFIG_FB_SH_MOBILE_LCDC_MODULE)
+void kfr2r09_lcd_on(void *board_data, struct fb_info *info);
 void kfr2r09_lcd_off(void *board_data);
 int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
                      struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
 void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
                       struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
 #else
-static inline void kfr2r09_lcd_on(void *board_data) {}
-static inline void kfr2r09_lcd_off(void *board_data) {}
-static inline int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
-                                   struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
+static void kfr2r09_lcd_on(void *board_data) {}
+static void kfr2r09_lcd_off(void *board_data) {}
+static int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
+                               struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
 {
        return -ENODEV;
 }
-static inline void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
-                                    struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
+static void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
+                               struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
 {
 }
 #endif
index 9e01e96fee944282aac81f9e9f2bbef3cc56294c..8344375dc01552f9332a432f23d02440dc471709 100644 (file)
@@ -128,7 +128,7 @@ config TXX9_DMAC
 
 config SH_DMAE
        tristate "Renesas SuperH DMAC support"
-       depends on SUPERH && SH_DMA
+       depends on (SUPERH && SH_DMA) || (ARM && ARCH_SHMOBILE)
        depends on !SH_DMA_API
        select DMA_ENGINE
        help
index a2a519fd2a24fc3ec9f4d1daa63fba110d99684e..fb64cf36ba61d0e786ecfeb802f43909ade4f2f2 100644 (file)
@@ -816,7 +816,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
        return ret;
 }
 
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 static irqreturn_t sh_dmae_err(int irq, void *data)
 {
        struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
@@ -1057,7 +1057,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
        /* Default transfer size of 32 bytes requires 32-byte alignment */
        shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
 
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
        chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 
        if (!chanirq_res)
@@ -1082,7 +1082,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
 
 #else
        chanirq_res = errirq_res;
-#endif /* CONFIG_CPU_SH4 */
+#endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
 
        if (chanirq_res->start == chanirq_res->end &&
            !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
@@ -1129,7 +1129,7 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
 chan_probe_err:
        sh_dmae_chan_remove(shdev);
 eirqres:
-#if defined(CONFIG_CPU_SH4)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
        free_irq(errirq, shdev);
 eirq_err:
 #endif
index bceafbfa72683698769890bfb664dbe57ea3a010..29e01f6238a7d24e29543a4dffea9a98479f4b7f 100644 (file)
@@ -549,7 +549,7 @@ config I2C_SH7760
 
 config I2C_SH_MOBILE
        tristate "SuperH Mobile I2C Controller"
-       depends on SUPERH
+       depends on SUPERH || ARCH_SHMOBILE
        help
          If you say yes to this option, support will be included for the
          built-in I2C interface on the Renesas SH-Mobile processor.
index ffb405d7c6f24caaf61a9837e66de0b4f417d490..598c49acaeb53eb7ae3d0bc9d0b4a1873901d5b2 100644 (file)
@@ -119,8 +119,10 @@ struct sh_mobile_i2c_data {
        struct i2c_adapter adap;
 
        struct clk *clk;
+       u_int8_t icic;
        u_int8_t iccl;
        u_int8_t icch;
+       u_int8_t flags;
 
        spinlock_t lock;
        wait_queue_head_t wait;
@@ -129,15 +131,17 @@ struct sh_mobile_i2c_data {
        int sr;
 };
 
+#define IIC_FLAG_HAS_ICIC67    (1 << 0)
+
 #define NORMAL_SPEED           100000 /* FAST_SPEED 400000 */
 
 /* Register offsets */
-#define ICDR(pd)               (pd->reg + 0x00)
-#define ICCR(pd)               (pd->reg + 0x04)
-#define ICSR(pd)               (pd->reg + 0x08)
-#define ICIC(pd)               (pd->reg + 0x0c)
-#define ICCL(pd)               (pd->reg + 0x10)
-#define ICCH(pd)               (pd->reg + 0x14)
+#define ICDR                   0x00
+#define ICCR                   0x04
+#define ICSR                   0x08
+#define ICIC                   0x0c
+#define ICCL                   0x10
+#define ICCH                   0x14
 
 /* Register bits */
 #define ICCR_ICE               0x80
@@ -155,11 +159,32 @@ struct sh_mobile_i2c_data {
 #define ICSR_WAIT              0x02
 #define ICSR_DTE               0x01
 
+#define ICIC_ICCLB8            0x80
+#define ICIC_ICCHB8            0x40
 #define ICIC_ALE               0x08
 #define ICIC_TACKE             0x04
 #define ICIC_WAITE             0x02
 #define ICIC_DTEE              0x01
 
+static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
+{
+       if (offs == ICIC)
+               data |= pd->icic;
+
+       iowrite8(data, pd->reg + offs);
+}
+
+static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
+{
+       return ioread8(pd->reg + offs);
+}
+
+static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
+                       unsigned char set, unsigned char clr)
+{
+       iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
+}
+
 static void activate_ch(struct sh_mobile_i2c_data *pd)
 {
        unsigned long i2c_clk;
@@ -187,6 +212,14 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
        else
                pd->iccl = (u_int8_t)(num/denom);
 
+       /* one more bit of ICCL in ICIC */
+       if (pd->flags & IIC_FLAG_HAS_ICIC67) {
+               if ((num/denom) > 0xff)
+                       pd->icic |= ICIC_ICCLB8;
+               else
+                       pd->icic &= ~ICIC_ICCLB8;
+       }
+
        /* Calculate the value for icch. From the data sheet:
           icch = (p clock / transfer rate) * (H / (L + H)) */
        num = i2c_clk * 4;
@@ -196,25 +229,33 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
        else
                pd->icch = (u_int8_t)(num/denom);
 
+       /* one more bit of ICCH in ICIC */
+       if (pd->flags & IIC_FLAG_HAS_ICIC67) {
+               if ((num/denom) > 0xff)
+                       pd->icic |= ICIC_ICCHB8;
+               else
+                       pd->icic &= ~ICIC_ICCHB8;
+       }
+
        /* Enable channel and configure rx ack */
-       iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+       iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 
        /* Mask all interrupts */
-       iowrite8(0, ICIC(pd));
+       iic_wr(pd, ICIC, 0);
 
        /* Set the clock */
-       iowrite8(pd->iccl, ICCL(pd));
-       iowrite8(pd->icch, ICCH(pd));
+       iic_wr(pd, ICCL, pd->iccl);
+       iic_wr(pd, ICCH, pd->icch);
 }
 
 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 {
        /* Clear/disable interrupts */
-       iowrite8(0, ICSR(pd));
-       iowrite8(0, ICIC(pd));
+       iic_wr(pd, ICSR, 0);
+       iic_wr(pd, ICIC, 0);
 
        /* Disable channel */
-       iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+       iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 
        /* Disable clock and mark device as idle */
        clk_disable(pd->clk);
@@ -233,35 +274,35 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 
        switch (op) {
        case OP_START: /* issue start and trigger DTE interrupt */
-               iowrite8(0x94, ICCR(pd));
+               iic_wr(pd, ICCR, 0x94);
                break;
        case OP_TX_FIRST: /* disable DTE interrupt and write data */
-               iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
-               iowrite8(data, ICDR(pd));
+               iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+               iic_wr(pd, ICDR, data);
                break;
        case OP_TX: /* write data */
-               iowrite8(data, ICDR(pd));
+               iic_wr(pd, ICDR, data);
                break;
        case OP_TX_STOP: /* write data and issue a stop afterwards */
-               iowrite8(data, ICDR(pd));
-               iowrite8(0x90, ICCR(pd));
+               iic_wr(pd, ICDR, data);
+               iic_wr(pd, ICCR, 0x90);
                break;
        case OP_TX_TO_RX: /* select read mode */
-               iowrite8(0x81, ICCR(pd));
+               iic_wr(pd, ICCR, 0x81);
                break;
        case OP_RX: /* just read data */
-               ret = ioread8(ICDR(pd));
+               ret = iic_rd(pd, ICDR);
                break;
        case OP_RX_STOP: /* enable DTE interrupt, issue stop */
-               iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
-                        ICIC(pd));
-               iowrite8(0xc0, ICCR(pd));
+               iic_wr(pd, ICIC,
+                      ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+               iic_wr(pd, ICCR, 0xc0);
                break;
        case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
-               iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
-                        ICIC(pd));
-               ret = ioread8(ICDR(pd));
-               iowrite8(0xc0, ICCR(pd));
+               iic_wr(pd, ICIC,
+                      ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+               ret = iic_rd(pd, ICDR);
+               iic_wr(pd, ICCR, 0xc0);
                break;
        }
 
@@ -367,7 +408,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
        unsigned char sr;
        int wakeup;
 
-       sr = ioread8(ICSR(pd));
+       sr = iic_rd(pd, ICSR);
        pd->sr |= sr; /* remember state */
 
        dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
@@ -376,7 +417,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 
        if (sr & (ICSR_AL | ICSR_TACK)) {
                /* don't interrupt transaction - continue to issue stop */
-               iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
+               iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
                wakeup = 0;
        } else if (pd->msg->flags & I2C_M_RD)
                wakeup = sh_mobile_i2c_isr_rx(pd);
@@ -384,7 +425,7 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
                wakeup = sh_mobile_i2c_isr_tx(pd);
 
        if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
-               iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
+               iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 
        if (wakeup) {
                pd->sr |= SW_DONE;
@@ -402,21 +443,21 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
        }
 
        /* Initialize channel registers */
-       iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
+       iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 
        /* Enable channel and configure rx ack */
-       iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
+       iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 
        /* Set the clock */
-       iowrite8(pd->iccl, ICCL(pd));
-       iowrite8(pd->icch, ICCH(pd));
+       iic_wr(pd, ICCL, pd->iccl);
+       iic_wr(pd, ICCH, pd->icch);
 
        pd->msg = usr_msg;
        pd->pos = -1;
        pd->sr = 0;
 
        /* Enable all interrupts to begin with */
-       iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
+       iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
        return 0;
 }
 
@@ -451,7 +492,7 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 
                retry_count = 1000;
 again:
-               val = ioread8(ICSR(pd));
+               val = iic_rd(pd, ICSR);
 
                dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 
@@ -576,6 +617,12 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
                goto err_irq;
        }
 
+       /* The IIC blocks on SH-Mobile ARM processors
+        * come with two new bits in ICIC.
+        */
+       if (size > 0x17)
+               pd->flags |= IIC_FLAG_HAS_ICIC67;
+
        /* Enable Runtime PM for this device.
         *
         * Also tell the Runtime PM core to ignore children
index edd5666f0ffbde3e7bdce003278e93b44227ad05..9e3f4f54281d984053155cb9a4854f876120b251 100644 (file)
@@ -748,7 +748,6 @@ static int __devinit sh_irda_probe(struct platform_device *pdev)
        struct net_device *ndev;
        struct sh_irda_self *self;
        struct resource *res;
-       char clk_name[8];
        int irq;
        int err = -ENOMEM;
 
@@ -775,10 +774,9 @@ static int __devinit sh_irda_probe(struct platform_device *pdev)
        if (err)
                goto err_mem_2;
 
-       snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id);
-       self->clk = clk_get(&pdev->dev, clk_name);
+       self->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(self->clk)) {
-               dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
+               dev_err(&pdev->dev, "cannot get irda clock\n");
                goto err_mem_3;
        }
 
index 5f90fcd7d107573312bbd44ab7be8839ab61b567..c291b3add1d2afb10b6aa241d77c356c98f0fd19 100644 (file)
@@ -346,6 +346,27 @@ static int scif_rxfill(struct uart_port *port)
                return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
        }
 }
+#elif defined(CONFIG_ARCH_SH7372)
+static int scif_txfill(struct uart_port *port)
+{
+       if (port->type == PORT_SCIFA)
+               return sci_in(port, SCFDR) >> 8;
+       else
+               return sci_in(port, SCTFDR);
+}
+
+static int scif_txroom(struct uart_port *port)
+{
+       return port->fifosize - scif_txfill(port);
+}
+
+static int scif_rxfill(struct uart_port *port)
+{
+       if (port->type == PORT_SCIFA)
+               return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
+       else
+               return sci_in(port, SCRFDR);
+}
 #else
 static int scif_txfill(struct uart_port *port)
 {
@@ -683,7 +704,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
                u16 ssr = sci_in(port, SCxSR);
 
                /* Disable future Rx interrupts */
-               if (port->type == PORT_SCIFA) {
+               if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
                        disable_irq_nosync(irq);
                        scr |= 0x4000;
                } else {
@@ -928,7 +949,7 @@ static void sci_dma_tx_complete(void *arg)
 
        if (!uart_circ_empty(xmit)) {
                schedule_work(&s->work_tx);
-       } else if (port->type == PORT_SCIFA) {
+       } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
                u16 ctrl = sci_in(port, SCSCR);
                sci_out(port, SCSCR, ctrl & ~SCI_CTRL_FLAGS_TIE);
        }
@@ -1184,7 +1205,7 @@ static void sci_start_tx(struct uart_port *port)
        unsigned short ctrl;
 
 #ifdef CONFIG_SERIAL_SH_SCI_DMA
-       if (port->type == PORT_SCIFA) {
+       if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
                u16 new, scr = sci_in(port, SCSCR);
                if (s->chan_tx)
                        new = scr | 0x8000;
@@ -1197,7 +1218,7 @@ static void sci_start_tx(struct uart_port *port)
            s->cookie_tx < 0)
                schedule_work(&s->work_tx);
 #endif
-       if (!s->chan_tx || port->type == PORT_SCIFA) {
+       if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
                /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
                ctrl = sci_in(port, SCSCR);
                sci_out(port, SCSCR, ctrl | SCI_CTRL_FLAGS_TIE);
@@ -1210,7 +1231,7 @@ static void sci_stop_tx(struct uart_port *port)
 
        /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
        ctrl = sci_in(port, SCSCR);
-       if (port->type == PORT_SCIFA)
+       if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
                ctrl &= ~0x8000;
        ctrl &= ~SCI_CTRL_FLAGS_TIE;
        sci_out(port, SCSCR, ctrl);
@@ -1222,7 +1243,7 @@ static void sci_start_rx(struct uart_port *port)
 
        /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
        ctrl |= sci_in(port, SCSCR);
-       if (port->type == PORT_SCIFA)
+       if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
                ctrl &= ~0x4000;
        sci_out(port, SCSCR, ctrl);
 }
@@ -1233,7 +1254,7 @@ static void sci_stop_rx(struct uart_port *port)
 
        /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
        ctrl = sci_in(port, SCSCR);
-       if (port->type == PORT_SCIFA)
+       if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
                ctrl &= ~0x4000;
        ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
        sci_out(port, SCSCR, ctrl);
@@ -1271,7 +1292,7 @@ static void rx_timer_fn(unsigned long arg)
        struct uart_port *port = &s->port;
        u16 scr = sci_in(port, SCSCR);
 
-       if (port->type == PORT_SCIFA) {
+       if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
                scr &= ~0x4000;
                enable_irq(s->irqs[1]);
        }
@@ -1524,6 +1545,8 @@ static const char *sci_type(struct uart_port *port)
                return "scif";
        case PORT_SCIFA:
                return "scifa";
+       case PORT_SCIFB:
+               return "scifb";
        }
 
        return NULL;
@@ -1612,6 +1635,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
        port->line      = index;
 
        switch (p->type) {
+       case PORT_SCIFB:
+               port->fifosize = 256;
+               break;
        case PORT_SCIFA:
                port->fifosize = 64;
                break;
index f70c49f915fa11c7878747f58973bebc899f5542..9b52f77a93057af3aa7ba8e69d002190f1b4aaab 100644 (file)
 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
   static inline unsigned int sci_##name##_in(struct uart_port *port)   \
   {                                                                    \
-    if (port->type == PORT_SCIF) {                                     \
+    if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {         \
       SCI_IN(scif_size, scif_offset)                                   \
     } else {   /* PORT_SCI or PORT_SCIFA */                            \
       SCI_IN(sci_size, sci_offset);                                    \
   }                                                                    \
   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
   {                                                                    \
-    if (port->type == PORT_SCIF) {                                     \
+    if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {         \
       SCI_OUT(scif_size, scif_offset, value)                           \
     } else {   /* PORT_SCI or PORT_SCIFA */                            \
       SCI_OUT(sci_size, sci_offset, value);                            \
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
       defined(CONFIG_CPU_SUBTYPE_SH7721) || \
       defined(CONFIG_ARCH_SH7367) || \
-      defined(CONFIG_ARCH_SH7377) || \
-      defined(CONFIG_ARCH_SH7372)
+      defined(CONFIG_ARCH_SH7377)
+#define SCIF_FNS(name, scif_offset, scif_size) \
+  CPU_SCIF_FNS(name, scif_offset, scif_size)
+#elif defined(CONFIG_ARCH_SH7372)
+#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
+  CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
 #define SCIF_FNS(name, scif_offset, scif_size) \
   CPU_SCIF_FNS(name, scif_offset, scif_size)
 #else
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
     defined(CONFIG_ARCH_SH7367) || \
-    defined(CONFIG_ARCH_SH7377) || \
-    defined(CONFIG_ARCH_SH7372)
+    defined(CONFIG_ARCH_SH7377)
 
 SCIF_FNS(SCSMR,  0x00, 16)
 SCIF_FNS(SCBRR,  0x04,  8)
@@ -436,6 +439,20 @@ SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCxTDR, 0x20,  8)
 SCIF_FNS(SCxRDR, 0x24,  8)
 SCIF_FNS(SCLSR,  0x00,  0)
+#elif defined(CONFIG_ARCH_SH7372)
+SCIF_FNS(SCSMR,  0x00, 16)
+SCIF_FNS(SCBRR,  0x04,  8)
+SCIF_FNS(SCSCR,  0x08, 16)
+SCIF_FNS(SCTDSR, 0x0c, 16)
+SCIF_FNS(SCFER,  0x10, 16)
+SCIF_FNS(SCxSR,  0x14, 16)
+SCIF_FNS(SCFCR,  0x18, 16)
+SCIF_FNS(SCFDR,  0x1c, 16)
+SCIF_FNS(SCTFDR, 0x38, 16)
+SCIF_FNS(SCRFDR, 0x3c, 16)
+SCIx_FNS(SCxTDR, 0x20,  8, 0x40,  8)
+SCIx_FNS(SCxRDR, 0x24,  8, 0x60,  8)
+SCIF_FNS(SCLSR,  0x00,  0)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
       defined(CONFIG_CPU_SUBTYPE_SH7724)
 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
index 78bb5127abd0a58bf06a3ac3588e7868d791ece0..08fc653a825caf66894f52296018619d2a762dbd 100644 (file)
@@ -1,9 +1,10 @@
 #
 # Makefile for the SuperH specific drivers.
 #
+obj-y  := clk.o intc.o
+
 obj-$(CONFIG_SUPERHYWAY)       += superhyway/
 obj-$(CONFIG_MAPLE)            += maple/
+
 obj-$(CONFIG_GENERIC_GPIO)     += pfc.o
-obj-$(CONFIG_SUPERH)           += clk.o
 obj-$(CONFIG_SH_CLK_CPG)       += clk-cpg.o
-obj-y                          += intc.o
index f5c80ba9ab1c762e27f1918f46c6dccb454a2213..8c024b984ed8b10f30ca7eb23c256122ac7f8393 100644 (file)
@@ -68,6 +68,39 @@ static unsigned long sh_clk_div6_recalc(struct clk *clk)
        return clk->freq_table[idx].frequency;
 }
 
+static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
+{
+       struct clk_div_mult_table *table = &sh_clk_div6_table;
+       u32 value;
+       int ret, i;
+
+       if (!clk->parent_table || !clk->parent_num)
+               return -EINVAL;
+
+       /* Search the parent */
+       for (i = 0; i < clk->parent_num; i++)
+               if (clk->parent_table[i] == parent)
+                       break;
+
+       if (i == clk->parent_num)
+               return -ENODEV;
+
+       ret = clk_reparent(clk, parent);
+       if (ret < 0)
+               return ret;
+
+       value = __raw_readl(clk->enable_reg) &
+               ~(((1 << clk->src_width) - 1) << clk->src_shift);
+
+       __raw_writel(value | (i << clk->src_shift), clk->enable_reg);
+
+       /* Rebuild the frequency table */
+       clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
+                            table, &clk->arch_flags);
+
+       return 0;
+}
+
 static int sh_clk_div6_set_rate(struct clk *clk,
                                unsigned long rate, int algo_id)
 {
@@ -117,7 +150,17 @@ static struct clk_ops sh_clk_div6_clk_ops = {
        .disable        = sh_clk_div6_disable,
 };
 
-int __init sh_clk_div6_register(struct clk *clks, int nr)
+static struct clk_ops sh_clk_div6_reparent_clk_ops = {
+       .recalc         = sh_clk_div6_recalc,
+       .round_rate     = sh_clk_div_round_rate,
+       .set_rate       = sh_clk_div6_set_rate,
+       .enable         = sh_clk_div6_enable,
+       .disable        = sh_clk_div6_disable,
+       .set_parent     = sh_clk_div6_set_parent,
+};
+
+static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
+                                          struct clk_ops *ops)
 {
        struct clk *clkp;
        void *freq_table;
@@ -136,7 +179,7 @@ int __init sh_clk_div6_register(struct clk *clks, int nr)
        for (k = 0; !ret && (k < nr); k++) {
                clkp = clks + k;
 
-               clkp->ops = &sh_clk_div6_clk_ops;
+               clkp->ops = ops;
                clkp->id = -1;
                clkp->freq_table = freq_table + (k * freq_table_size);
                clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
@@ -147,6 +190,17 @@ int __init sh_clk_div6_register(struct clk *clks, int nr)
        return ret;
 }
 
+int __init sh_clk_div6_register(struct clk *clks, int nr)
+{
+       return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops);
+}
+
+int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
+{
+       return sh_clk_div6_register_ops(clks, nr,
+                                       &sh_clk_div6_reparent_clk_ops);
+}
+
 static unsigned long sh_clk_div4_recalc(struct clk *clk)
 {
        struct clk_div4_table *d4t = clk->priv;
index 7b11ea68c80e86cbf85387d6ba39eb84cb0c700b..bbeee4ba248820daf449a0cea4c19a669241ec26 100644 (file)
@@ -1896,6 +1896,13 @@ config FB_W100
 
          If unsure, say N.
 
+config SH_MIPI_DSI
+       tristate
+       depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
+
+config SH_LCD_MIPI_DSI
+       bool
+
 config FB_SH_MOBILE_LCDC
        tristate "SuperH Mobile LCDC framebuffer support"
        depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
@@ -1904,9 +1911,17 @@ config FB_SH_MOBILE_LCDC
        select FB_SYS_IMAGEBLIT
        select FB_SYS_FOPS
        select FB_DEFERRED_IO
+       select SH_MIPI_DSI if SH_LCD_MIPI_DSI
        ---help---
          Frame buffer driver for the on-chip SH-Mobile LCD controller.
 
+config FB_SH_MOBILE_HDMI
+       tristate "SuperH Mobile HDMI controller support"
+       depends on FB_SH_MOBILE_LCDC
+       select FB_MODE_HELPERS
+       ---help---
+         Driver for the on-chip SH-Mobile HDMI controller.
+
 config FB_TMIO
        tristate "Toshiba Mobile IO FrameBuffer support"
        depends on FB && MFD_CORE
index f56a9cae2157407562bb04189332b9ce50b9b654..485e8ed1318c4bd0a055553f784b6c642ca6cf81 100644 (file)
@@ -123,6 +123,8 @@ obj-$(CONFIG_FB_IBM_GXT4500)          += gxt4500.o
 obj-$(CONFIG_FB_PS3)             += ps3fb.o
 obj-$(CONFIG_FB_SM501)            += sm501fb.o
 obj-$(CONFIG_FB_XILINX)           += xilinxfb.o
+obj-$(CONFIG_SH_MIPI_DSI)        += sh_mipi_dsi.o
+obj-$(CONFIG_FB_SH_MOBILE_HDMI)          += sh_mobile_hdmi.o
 obj-$(CONFIG_FB_SH_MOBILE_LCDC)          += sh_mobile_lcdcfb.o
 obj-$(CONFIG_FB_OMAP)             += omap/
 obj-y                             += omap2/
diff --git a/drivers/video/sh_mipi_dsi.c b/drivers/video/sh_mipi_dsi.c
new file mode 100644 (file)
index 0000000..5699ce0
--- /dev/null
@@ -0,0 +1,505 @@
+/*
+ * Renesas SH-mobile MIPI DSI support
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include <video/mipi_display.h>
+#include <video/sh_mipi_dsi.h>
+#include <video/sh_mobile_lcdc.h>
+
+#define CMTSRTCTR      0x80d0
+#define CMTSRTREQ      0x8070
+
+#define DSIINTE                0x0060
+
+/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
+#define MAX_SH_MIPI_DSI 2
+
+struct sh_mipi {
+       void __iomem    *base;
+       struct clk      *dsit_clk;
+       struct clk      *dsip_clk;
+};
+
+static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
+
+/* Protect the above array */
+static DEFINE_MUTEX(array_lock);
+
+static struct sh_mipi *sh_mipi_by_handle(int handle)
+{
+       if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
+               return NULL;
+
+       return mipi_dsi[handle];
+}
+
+static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
+                             u8 cmd, u8 param)
+{
+       u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
+       int cnt = 100;
+
+       /* transmit a short packet to LCD panel */
+       iowrite32(1 | data, mipi->base + 0x80d0); /* CMTSRTCTR */
+       iowrite32(1, mipi->base + 0x8070); /* CMTSRTREQ */
+
+       while ((ioread32(mipi->base + 0x8070) & 1) && --cnt)
+               udelay(1);
+
+       return cnt ? 0 : -ETIMEDOUT;
+}
+
+#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
+                               -EINVAL : (c) - 1)
+
+static int sh_mipi_dcs(int handle, u8 cmd)
+{
+       struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
+       if (!mipi)
+               return -ENODEV;
+       return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
+}
+
+static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
+{
+       struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
+       if (!mipi)
+               return -ENODEV;
+       return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
+                                 param);
+}
+
+static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
+{
+       /*
+        * enable LCDC data tx, transition to LPS after completion of each HS
+        * packet
+        */
+       iowrite32(0x00000002 | enable, mipi->base + 0x8000); /* DTCTR */
+}
+
+static void sh_mipi_shutdown(struct platform_device *pdev)
+{
+       struct sh_mipi *mipi = platform_get_drvdata(pdev);
+
+       sh_mipi_dsi_enable(mipi, false);
+}
+
+static void mipi_display_on(void *arg, struct fb_info *info)
+{
+       struct sh_mipi *mipi = arg;
+
+       sh_mipi_dsi_enable(mipi, true);
+}
+
+static void mipi_display_off(void *arg)
+{
+       struct sh_mipi *mipi = arg;
+
+       sh_mipi_dsi_enable(mipi, false);
+}
+
+static int __init sh_mipi_setup(struct sh_mipi *mipi,
+                               struct sh_mipi_dsi_info *pdata)
+{
+       void __iomem *base = mipi->base;
+       struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
+       u32 pctype, datatype, pixfmt;
+       u32 linelength;
+       bool yuv;
+
+       /* Select data format */
+       switch (pdata->data_format) {
+       case MIPI_RGB888:
+               pctype = 0;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
+               pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
+               linelength = ch->lcd_cfg.xres * 3;
+               yuv = false;
+               break;
+       case MIPI_RGB565:
+               pctype = 1;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
+               pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
+               linelength = ch->lcd_cfg.xres * 2;
+               yuv = false;
+               break;
+       case MIPI_RGB666_LP:
+               pctype = 2;
+               datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
+               pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
+               linelength = ch->lcd_cfg.xres * 3;
+               yuv = false;
+               break;
+       case MIPI_RGB666:
+               pctype = 3;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
+               pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
+               linelength = (ch->lcd_cfg.xres * 18 + 7) / 8;
+               yuv = false;
+               break;
+       case MIPI_BGR888:
+               pctype = 8;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
+               pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
+               linelength = ch->lcd_cfg.xres * 3;
+               yuv = false;
+               break;
+       case MIPI_BGR565:
+               pctype = 9;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
+               pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
+               linelength = ch->lcd_cfg.xres * 2;
+               yuv = false;
+               break;
+       case MIPI_BGR666_LP:
+               pctype = 0xa;
+               datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
+               pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
+               linelength = ch->lcd_cfg.xres * 3;
+               yuv = false;
+               break;
+       case MIPI_BGR666:
+               pctype = 0xb;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
+               pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
+               linelength = (ch->lcd_cfg.xres * 18 + 7) / 8;
+               yuv = false;
+               break;
+       case MIPI_YUYV:
+               pctype = 4;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
+               pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
+               linelength = ch->lcd_cfg.xres * 2;
+               yuv = true;
+               break;
+       case MIPI_UYVY:
+               pctype = 5;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
+               pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
+               linelength = ch->lcd_cfg.xres * 2;
+               yuv = true;
+               break;
+       case MIPI_YUV420_L:
+               pctype = 6;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
+               pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
+               linelength = (ch->lcd_cfg.xres * 12 + 7) / 8;
+               yuv = true;
+               break;
+       case MIPI_YUV420:
+               pctype = 7;
+               datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
+               pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
+               /* Length of U/V line */
+               linelength = (ch->lcd_cfg.xres + 1) / 2;
+               yuv = true;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if ((yuv && ch->interface_type != YUV422) ||
+           (!yuv && ch->interface_type != RGB24))
+               return -EINVAL;
+
+       /* reset DSI link */
+       iowrite32(0x00000001, base); /* SYSCTRL */
+       /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
+       udelay(50);
+       iowrite32(0x00000000, base); /* SYSCTRL */
+
+       /* setup DSI link */
+
+       /*
+        * Default = ULPS enable |
+        *      Contention detection enabled |
+        *      EoT packet transmission enable |
+        *      CRC check enable |
+        *      ECC check enable
+        * additionally enable first two lanes
+        */
+       iowrite32(0x00003703, base + 0x04); /* SYSCONF */
+       /*
+        * T_wakeup = 0x7000
+        * T_hs-trail = 3
+        * T_hs-prepare = 3
+        * T_clk-trail = 3
+        * T_clk-prepare = 2
+        */
+       iowrite32(0x70003332, base + 0x08); /* TIMSET */
+       /* no responses requested */
+       iowrite32(0x00000000, base + 0x18); /* RESREQSET0 */
+       /* request response to packets of type 0x28 */
+       iowrite32(0x00000100, base + 0x1c); /* RESREQSET1 */
+       /* High-speed transmission timeout, default 0xffffffff */
+       iowrite32(0x0fffffff, base + 0x20); /* HSTTOVSET */
+       /* LP reception timeout, default 0xffffffff */
+       iowrite32(0x0fffffff, base + 0x24); /* LPRTOVSET */
+       /* Turn-around timeout, default 0xffffffff */
+       iowrite32(0x0fffffff, base + 0x28); /* TATOVSET */
+       /* Peripheral reset timeout, default 0xffffffff */
+       iowrite32(0x0fffffff, base + 0x2c); /* PRTOVSET */
+       /* Enable timeout counters */
+       iowrite32(0x00000f00, base + 0x30); /* DSICTRL */
+       /* Interrupts not used, disable all */
+       iowrite32(0, base + DSIINTE);
+       /* DSI-Tx bias on */
+       iowrite32(0x00000001, base + 0x70); /* PHYCTRL */
+       udelay(200);
+       /* Deassert resets, power on, set multiplier */
+       iowrite32(0x03070b01, base + 0x70); /* PHYCTRL */
+
+       /* setup l-bridge */
+
+       /*
+        * Enable transmission of all packets,
+        * transmit LPS after each HS packet completion
+        */
+       iowrite32(0x00000006, base + 0x8000); /* DTCTR */
+       /* VSYNC width = 2 (<< 17) */
+       iowrite32(0x00040000 | (pctype << 12) | datatype, base + 0x8020); /* VMCTR1 */
+       /*
+        * Non-burst mode with sync pulses: VSE and HSE are output,
+        * HSA period allowed, no commands in LP
+        */
+       iowrite32(0x00e00000, base + 0x8024); /* VMCTR2 */
+       /*
+        * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
+        * sh_mobile_lcdc_info.ch[0].lcd_cfg.xres), HSALEN = 1 - default
+        * (unused, since VMCTR2[HSABM] = 0)
+        */
+       iowrite32(1 | (linelength << 16), base + 0x8028); /* VMLEN1 */
+
+       msleep(5);
+
+       /* setup LCD panel */
+
+       /* cf. drivers/video/omap/lcd_mipid.c */
+       sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
+       msleep(120);
+       /*
+        * [7] - Page Address Mode
+        * [6] - Column Address Mode
+        * [5] - Page / Column Address Mode
+        * [4] - Display Device Line Refresh Order
+        * [3] - RGB/BGR Order
+        * [2] - Display Data Latch Data Order
+        * [1] - Flip Horizontal
+        * [0] - Flip Vertical
+        */
+       sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
+       /* cf. set_data_lines() */
+       sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
+                         pixfmt << 4);
+       sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
+
+       return 0;
+}
+
+static int __init sh_mipi_probe(struct platform_device *pdev)
+{
+       struct sh_mipi *mipi;
+       struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       unsigned long rate, f_current;
+       int idx = pdev->id, ret;
+       char dsip_clk[] = "dsi.p_clk";
+
+       if (!res || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
+               return -ENODEV;
+
+       mutex_lock(&array_lock);
+       if (idx < 0)
+               for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
+                       ;
+
+       if (idx == ARRAY_SIZE(mipi_dsi)) {
+               ret = -EBUSY;
+               goto efindslot;
+       }
+
+       mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
+       if (!mipi) {
+               ret = -ENOMEM;
+               goto ealloc;
+       }
+
+       if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+               dev_err(&pdev->dev, "MIPI register region already claimed\n");
+               ret = -EBUSY;
+               goto ereqreg;
+       }
+
+       mipi->base = ioremap(res->start, resource_size(res));
+       if (!mipi->base) {
+               ret = -ENOMEM;
+               goto emap;
+       }
+
+       mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
+       if (IS_ERR(mipi->dsit_clk)) {
+               ret = PTR_ERR(mipi->dsit_clk);
+               goto eclktget;
+       }
+
+       f_current = clk_get_rate(mipi->dsit_clk);
+       /* 80MHz required by the datasheet */
+       rate = clk_round_rate(mipi->dsit_clk, 80000000);
+       if (rate > 0 && rate != f_current)
+               ret = clk_set_rate(mipi->dsit_clk, rate);
+       else
+               ret = rate;
+       if (ret < 0)
+               goto esettrate;
+
+       dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
+
+       sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
+       mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
+       if (IS_ERR(mipi->dsip_clk)) {
+               ret = PTR_ERR(mipi->dsip_clk);
+               goto eclkpget;
+       }
+
+       f_current = clk_get_rate(mipi->dsip_clk);
+       /* Between 10 and 50MHz */
+       rate = clk_round_rate(mipi->dsip_clk, 24000000);
+       if (rate > 0 && rate != f_current)
+               ret = clk_set_rate(mipi->dsip_clk, rate);
+       else
+               ret = rate;
+       if (ret < 0)
+               goto esetprate;
+
+       dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
+
+       msleep(10);
+
+       ret = clk_enable(mipi->dsit_clk);
+       if (ret < 0)
+               goto eclkton;
+
+       ret = clk_enable(mipi->dsip_clk);
+       if (ret < 0)
+               goto eclkpon;
+
+       mipi_dsi[idx] = mipi;
+
+       ret = sh_mipi_setup(mipi, pdata);
+       if (ret < 0)
+               goto emipisetup;
+
+       mutex_unlock(&array_lock);
+       platform_set_drvdata(pdev, mipi);
+
+       /* Set up LCDC callbacks */
+       pdata->lcd_chan->board_cfg.board_data = mipi;
+       pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
+       pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
+
+       return 0;
+
+emipisetup:
+       mipi_dsi[idx] = NULL;
+       clk_disable(mipi->dsip_clk);
+eclkpon:
+       clk_disable(mipi->dsit_clk);
+eclkton:
+esetprate:
+       clk_put(mipi->dsip_clk);
+eclkpget:
+esettrate:
+       clk_put(mipi->dsit_clk);
+eclktget:
+       iounmap(mipi->base);
+emap:
+       release_mem_region(res->start, resource_size(res));
+ereqreg:
+       kfree(mipi);
+ealloc:
+efindslot:
+       mutex_unlock(&array_lock);
+
+       return ret;
+}
+
+static int __exit sh_mipi_remove(struct platform_device *pdev)
+{
+       struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       struct sh_mipi *mipi = platform_get_drvdata(pdev);
+       int i, ret;
+
+       mutex_lock(&array_lock);
+
+       for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
+               ;
+
+       if (i == ARRAY_SIZE(mipi_dsi)) {
+               ret = -EINVAL;
+       } else {
+               ret = 0;
+               mipi_dsi[i] = NULL;
+       }
+
+       mutex_unlock(&array_lock);
+
+       if (ret < 0)
+               return ret;
+
+       pdata->lcd_chan->board_cfg.display_on = NULL;
+       pdata->lcd_chan->board_cfg.display_off = NULL;
+       pdata->lcd_chan->board_cfg.board_data = NULL;
+
+       clk_disable(mipi->dsip_clk);
+       clk_disable(mipi->dsit_clk);
+       clk_put(mipi->dsit_clk);
+       clk_put(mipi->dsip_clk);
+       iounmap(mipi->base);
+       if (res)
+               release_mem_region(res->start, resource_size(res));
+       platform_set_drvdata(pdev, NULL);
+       kfree(mipi);
+
+       return 0;
+}
+
+static struct platform_driver sh_mipi_driver = {
+       .remove         = __exit_p(sh_mipi_remove),
+       .shutdown       = sh_mipi_shutdown,
+       .driver = {
+               .name   = "sh-mipi-dsi",
+       },
+};
+
+static int __init sh_mipi_init(void)
+{
+       return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
+}
+module_init(sh_mipi_init);
+
+static void __exit sh_mipi_exit(void)
+{
+       platform_driver_unregister(&sh_mipi_driver);
+}
+module_exit(sh_mipi_exit);
+
+MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
+MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/sh_mobile_hdmi.c b/drivers/video/sh_mobile_hdmi.c
new file mode 100644 (file)
index 0000000..2fde08c
--- /dev/null
@@ -0,0 +1,1028 @@
+/*
+ * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
+ * for SLISHDMI13T and SLIPHDMIT IP cores
+ *
+ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include <video/sh_mobile_hdmi.h>
+#include <video/sh_mobile_lcdc.h>
+
+#define HDMI_SYSTEM_CTRL                       0x00 /* System control */
+#define HDMI_L_R_DATA_SWAP_CTRL_RPKT           0x01 /* L/R data swap control,
+                                                       bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
+#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8      0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
+#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0       0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
+#define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS         0x04 /* SPDIF audio sampling frequency,
+                                                       bits 19..16 of Internal CTS */
+#define HDMI_INTERNAL_CTS_15_8                 0x05 /* bits 15..8 of Internal CTS */
+#define HDMI_INTERNAL_CTS_7_0                  0x06 /* bits 7..0 of Internal CTS */
+#define HDMI_EXTERNAL_CTS_19_16                        0x07 /* External CTS */
+#define HDMI_EXTERNAL_CTS_15_8                 0x08 /* External CTS */
+#define HDMI_EXTERNAL_CTS_7_0                  0x09 /* External CTS */
+#define HDMI_AUDIO_SETTING_1                   0x0A /* Audio setting.1 */
+#define HDMI_AUDIO_SETTING_2                   0x0B /* Audio setting.2 */
+#define HDMI_I2S_AUDIO_SET                     0x0C /* I2S audio setting */
+#define HDMI_DSD_AUDIO_SET                     0x0D /* DSD audio setting */
+#define HDMI_DEBUG_MONITOR_1                   0x0E /* Debug monitor.1 */
+#define HDMI_DEBUG_MONITOR_2                   0x0F /* Debug monitor.2 */
+#define HDMI_I2S_INPUT_PIN_SWAP                        0x10 /* I2S input pin swap */
+#define HDMI_AUDIO_STATUS_BITS_SETTING_1       0x11 /* Audio status bits setting.1 */
+#define HDMI_AUDIO_STATUS_BITS_SETTING_2       0x12 /* Audio status bits setting.2 */
+#define HDMI_CATEGORY_CODE                     0x13 /* Category code */
+#define HDMI_SOURCE_NUM_AUDIO_WORD_LEN         0x14 /* Source number/Audio word length */
+#define HDMI_AUDIO_VIDEO_SETTING_1             0x15 /* Audio/Video setting.1 */
+#define HDMI_VIDEO_SETTING_1                   0x16 /* Video setting.1 */
+#define HDMI_DEEP_COLOR_MODES                  0x17 /* Deep Color Modes */
+
+/* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
+#define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
+
+#define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS     0x30 /* External video parameter settings */
+#define HDMI_EXTERNAL_H_TOTAL_7_0              0x31 /* External horizontal total (LSB) */
+#define HDMI_EXTERNAL_H_TOTAL_11_8             0x32 /* External horizontal total (MSB) */
+#define HDMI_EXTERNAL_H_BLANK_7_0              0x33 /* External horizontal blank (LSB) */
+#define HDMI_EXTERNAL_H_BLANK_9_8              0x34 /* External horizontal blank (MSB) */
+#define HDMI_EXTERNAL_H_DELAY_7_0              0x35 /* External horizontal delay (LSB) */
+#define HDMI_EXTERNAL_H_DELAY_9_8              0x36 /* External horizontal delay (MSB) */
+#define HDMI_EXTERNAL_H_DURATION_7_0           0x37 /* External horizontal duration (LSB) */
+#define HDMI_EXTERNAL_H_DURATION_9_8           0x38 /* External horizontal duration (MSB) */
+#define HDMI_EXTERNAL_V_TOTAL_7_0              0x39 /* External vertical total (LSB) */
+#define HDMI_EXTERNAL_V_TOTAL_9_8              0x3A /* External vertical total (MSB) */
+#define HDMI_AUDIO_VIDEO_SETTING_2             0x3B /* Audio/Video setting.2 */
+#define HDMI_EXTERNAL_V_BLANK                  0x3D /* External vertical blank */
+#define HDMI_EXTERNAL_V_DELAY                  0x3E /* External vertical delay */
+#define HDMI_EXTERNAL_V_DURATION               0x3F /* External vertical duration */
+#define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL      0x40 /* Control packet manual send control */
+#define HDMI_CTRL_PKT_AUTO_SEND                        0x41 /* Control packet auto send with VSYNC control */
+#define HDMI_AUTO_CHECKSUM_OPTION              0x42 /* Auto checksum option */
+#define HDMI_VIDEO_SETTING_2                   0x45 /* Video setting.2 */
+#define HDMI_OUTPUT_OPTION                     0x46 /* Output option */
+#define HDMI_SLIPHDMIT_PARAM_OPTION            0x51 /* SLIPHDMIT parameter option */
+#define HDMI_HSYNC_PMENT_AT_EMB_7_0            0x52 /* HSYNC placement at embedded sync (LSB) */
+#define HDMI_HSYNC_PMENT_AT_EMB_15_8           0x53 /* HSYNC placement at embedded sync (MSB) */
+#define HDMI_VSYNC_PMENT_AT_EMB_7_0            0x54 /* VSYNC placement at embedded sync (LSB) */
+#define HDMI_VSYNC_PMENT_AT_EMB_14_8           0x55 /* VSYNC placement at embedded sync (MSB) */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_1                0x56 /* SLIPHDMIT parameter settings.1 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_2                0x57 /* SLIPHDMIT parameter settings.2 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_3                0x58 /* SLIPHDMIT parameter settings.3 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_5                0x59 /* SLIPHDMIT parameter settings.5 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_6                0x5A /* SLIPHDMIT parameter settings.6 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_7                0x5B /* SLIPHDMIT parameter settings.7 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_8                0x5C /* SLIPHDMIT parameter settings.8 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_9                0x5D /* SLIPHDMIT parameter settings.9 */
+#define HDMI_SLIPHDMIT_PARAM_SETTINGS_10       0x5E /* SLIPHDMIT parameter settings.10 */
+#define HDMI_CTRL_PKT_BUF_INDEX                        0x5F /* Control packet buffer index */
+#define HDMI_CTRL_PKT_BUF_ACCESS_HB0           0x60 /* Control packet data buffer access window - HB0 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_HB1           0x61 /* Control packet data buffer access window - HB1 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_HB2           0x62 /* Control packet data buffer access window - HB2 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB0           0x63 /* Control packet data buffer access window - PB0 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB1           0x64 /* Control packet data buffer access window - PB1 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB2           0x65 /* Control packet data buffer access window - PB2 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB3           0x66 /* Control packet data buffer access window - PB3 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB4           0x67 /* Control packet data buffer access window - PB4 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB5           0x68 /* Control packet data buffer access window - PB5 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB6           0x69 /* Control packet data buffer access window - PB6 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB7           0x6A /* Control packet data buffer access window - PB7 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB8           0x6B /* Control packet data buffer access window - PB8 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB9           0x6C /* Control packet data buffer access window - PB9 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB10          0x6D /* Control packet data buffer access window - PB10 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB11          0x6E /* Control packet data buffer access window - PB11 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB12          0x6F /* Control packet data buffer access window - PB12 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB13          0x70 /* Control packet data buffer access window - PB13 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB14          0x71 /* Control packet data buffer access window - PB14 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB15          0x72 /* Control packet data buffer access window - PB15 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB16          0x73 /* Control packet data buffer access window - PB16 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB17          0x74 /* Control packet data buffer access window - PB17 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB18          0x75 /* Control packet data buffer access window - PB18 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB19          0x76 /* Control packet data buffer access window - PB19 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB20          0x77 /* Control packet data buffer access window - PB20 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB21          0x78 /* Control packet data buffer access window - PB21 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB22          0x79 /* Control packet data buffer access window - PB22 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB23          0x7A /* Control packet data buffer access window - PB23 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB24          0x7B /* Control packet data buffer access window - PB24 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB25          0x7C /* Control packet data buffer access window - PB25 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB26          0x7D /* Control packet data buffer access window - PB26 */
+#define HDMI_CTRL_PKT_BUF_ACCESS_PB27          0x7E /* Control packet data buffer access window - PB27 */
+#define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW       0x80 /* EDID/KSV FIFO access window */
+#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0      0x81 /* DDC bus access frequency control (LSB) */
+#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8     0x82 /* DDC bus access frequency control (MSB) */
+#define HDMI_INTERRUPT_MASK_1                  0x92 /* Interrupt mask.1 */
+#define HDMI_INTERRUPT_MASK_2                  0x93 /* Interrupt mask.2 */
+#define HDMI_INTERRUPT_STATUS_1                        0x94 /* Interrupt status.1 */
+#define HDMI_INTERRUPT_STATUS_2                        0x95 /* Interrupt status.2 */
+#define HDMI_INTERRUPT_MASK_3                  0x96 /* Interrupt mask.3 */
+#define HDMI_INTERRUPT_MASK_4                  0x97 /* Interrupt mask.4 */
+#define HDMI_INTERRUPT_STATUS_3                        0x98 /* Interrupt status.3 */
+#define HDMI_INTERRUPT_STATUS_4                        0x99 /* Interrupt status.4 */
+#define HDMI_SOFTWARE_HDCP_CONTROL_1           0x9A /* Software HDCP control.1 */
+#define HDMI_FRAME_COUNTER                     0x9C /* Frame counter */
+#define HDMI_FRAME_COUNTER_FOR_RI_CHECK                0x9D /* Frame counter for Ri check */
+#define HDMI_HDCP_CONTROL                      0xAF /* HDCP control */
+#define HDMI_RI_FRAME_COUNT_REGISTER           0xB2 /* Ri frame count register */
+#define HDMI_DDC_BUS_CONTROL                   0xB7 /* DDC bus control */
+#define HDMI_HDCP_STATUS                       0xB8 /* HDCP status */
+#define HDMI_SHA0                              0xB9 /* sha0 */
+#define HDMI_SHA1                              0xBA /* sha1 */
+#define HDMI_SHA2                              0xBB /* sha2 */
+#define HDMI_SHA3                              0xBC /* sha3 */
+#define HDMI_SHA4                              0xBD /* sha4 */
+#define HDMI_BCAPS_READ                                0xBE /* BCAPS read / debug */
+#define HDMI_AKSV_BKSV_7_0_MONITOR             0xBF /* AKSV/BKSV[7:0] monitor */
+#define HDMI_AKSV_BKSV_15_8_MONITOR            0xC0 /* AKSV/BKSV[15:8] monitor */
+#define HDMI_AKSV_BKSV_23_16_MONITOR           0xC1 /* AKSV/BKSV[23:16] monitor */
+#define HDMI_AKSV_BKSV_31_24_MONITOR           0xC2 /* AKSV/BKSV[31:24] monitor */
+#define HDMI_AKSV_BKSV_39_32_MONITOR           0xC3 /* AKSV/BKSV[39:32] monitor */
+#define HDMI_EDID_SEGMENT_POINTER              0xC4 /* EDID segment pointer */
+#define HDMI_EDID_WORD_ADDRESS                 0xC5 /* EDID word address */
+#define HDMI_EDID_DATA_FIFO_ADDRESS            0xC6 /* EDID data FIFO address */
+#define HDMI_NUM_OF_HDMI_DEVICES               0xC7 /* Number of HDMI devices */
+#define HDMI_HDCP_ERROR_CODE                   0xC8 /* HDCP error code */
+#define HDMI_100MS_TIMER_SET                   0xC9 /* 100ms timer setting */
+#define HDMI_5SEC_TIMER_SET                    0xCA /* 5sec timer setting */
+#define HDMI_RI_READ_COUNT                     0xCB /* Ri read count */
+#define HDMI_AN_SEED                           0xCC /* An seed */
+#define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED         0xCD /* Maximum number of receivers allowed */
+#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1      0xCE /* HDCP memory access control.1 */
+#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2      0xCF /* HDCP memory access control.2 */
+#define HDMI_HDCP_CONTROL_2                    0xD0 /* HDCP Control 2 */
+#define HDMI_HDCP_KEY_MEMORY_CONTROL           0xD2 /* HDCP Key Memory Control */
+#define HDMI_COLOR_SPACE_CONV_CONFIG_1         0xD3 /* Color space conversion configuration.1 */
+#define HDMI_VIDEO_SETTING_3                   0xD4 /* Video setting.3 */
+#define HDMI_RI_7_0                            0xD5 /* Ri[7:0] */
+#define HDMI_RI_15_8                           0xD6 /* Ri[15:8] */
+#define HDMI_PJ                                        0xD7 /* Pj */
+#define HDMI_SHA_RD                            0xD8 /* sha_rd */
+#define HDMI_RI_7_0_SAVED                      0xD9 /* Ri[7:0] saved */
+#define HDMI_RI_15_8_SAVED                     0xDA /* Ri[15:8] saved */
+#define HDMI_PJ_SAVED                          0xDB /* Pj saved */
+#define HDMI_NUM_OF_DEVICES                    0xDC /* Number of devices */
+#define HDMI_HOT_PLUG_MSENS_STATUS             0xDF /* Hot plug/MSENS status */
+#define HDMI_BCAPS_WRITE                       0xE0 /* bcaps */
+#define HDMI_BSTAT_7_0                         0xE1 /* bstat[7:0] */
+#define HDMI_BSTAT_15_8                                0xE2 /* bstat[15:8] */
+#define HDMI_BKSV_7_0                          0xE3 /* bksv[7:0] */
+#define HDMI_BKSV_15_8                         0xE4 /* bksv[15:8] */
+#define HDMI_BKSV_23_16                                0xE5 /* bksv[23:16] */
+#define HDMI_BKSV_31_24                                0xE6 /* bksv[31:24] */
+#define HDMI_BKSV_39_32                                0xE7 /* bksv[39:32] */
+#define HDMI_AN_7_0                            0xE8 /* An[7:0] */
+#define HDMI_AN_15_8                           0xE9 /* An [15:8] */
+#define HDMI_AN_23_16                          0xEA /* An [23:16] */
+#define HDMI_AN_31_24                          0xEB /* An [31:24] */
+#define HDMI_AN_39_32                          0xEC /* An [39:32] */
+#define HDMI_AN_47_40                          0xED /* An [47:40] */
+#define HDMI_AN_55_48                          0xEE /* An [55:48] */
+#define HDMI_AN_63_56                          0xEF /* An [63:56] */
+#define HDMI_PRODUCT_ID                                0xF0 /* Product ID */
+#define HDMI_REVISION_ID                       0xF1 /* Revision ID */
+#define HDMI_TEST_MODE                         0xFE /* Test mode */
+
+enum hotplug_state {
+       HDMI_HOTPLUG_DISCONNECTED,
+       HDMI_HOTPLUG_CONNECTED,
+       HDMI_HOTPLUG_EDID_DONE,
+};
+
+struct sh_hdmi {
+       void __iomem *base;
+       enum hotplug_state hp_state;
+       struct clk *hdmi_clk;
+       struct device *dev;
+       struct fb_info *info;
+       struct delayed_work edid_work;
+       struct fb_var_screeninfo var;
+};
+
+static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
+{
+       iowrite8(data, hdmi->base + reg);
+}
+
+static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
+{
+       return ioread8(hdmi->base + reg);
+}
+
+/* External video parameter settings */
+static void hdmi_external_video_param(struct sh_hdmi *hdmi)
+{
+       struct fb_var_screeninfo *var = &hdmi->var;
+       u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
+       u8 sync = 0;
+
+       htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
+
+       hdelay = var->hsync_len + var->left_margin;
+       hblank = var->right_margin + hdelay;
+
+       /*
+        * Vertical timing looks a bit different in Figure 18,
+        * but let's try the same first by setting offset = 0
+        */
+       vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
+
+       vdelay = var->vsync_len + var->upper_margin;
+       vblank = var->lower_margin + vdelay;
+       voffset = min(var->upper_margin / 2, 6U);
+
+       /*
+        * [3]: VSYNC polarity: Positive
+        * [2]: HSYNC polarity: Positive
+        * [1]: Interlace/Progressive: Progressive
+        * [0]: External video settings enable: used.
+        */
+       if (var->sync & FB_SYNC_HOR_HIGH_ACT)
+               sync |= 4;
+       if (var->sync & FB_SYNC_VERT_HIGH_ACT)
+               sync |= 8;
+
+       pr_debug("H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
+                htotal, hblank, hdelay, var->hsync_len,
+                vtotal, vblank, vdelay, var->vsync_len, sync);
+
+       hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
+
+       hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
+       hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
+
+       hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
+       hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
+
+       hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
+       hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
+
+       hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
+       hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
+
+       hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
+       hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
+
+       hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
+
+       hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
+
+       hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
+
+       /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for manual mode */
+}
+
+/**
+ * sh_hdmi_video_config()
+ */
+static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
+{
+       /*
+        * [7:4]: Audio sampling frequency: 48kHz
+        * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
+        * [0]: Internal/External DE select: internal
+        */
+       hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
+
+       /*
+        * [7:6]: Video output format: RGB 4:4:4
+        * [5:4]: Input video data width: 8 bit
+        * [3:1]: EAV/SAV location: channel 1
+        * [0]: Video input color space: RGB
+        */
+       hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
+
+       /*
+        * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
+        * left at 0 by default, this configures 24bpp and sets the Color Depth
+        * (CD) field in the General Control Packet
+        */
+       hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
+}
+
+/**
+ * sh_hdmi_audio_config()
+ */
+static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
+{
+       /*
+        * [7:4] L/R data swap control
+        * [3:0] appropriate N[19:16]
+        */
+       hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
+       /* appropriate N[15:8] */
+       hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
+       /* appropriate N[7:0] */
+       hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
+
+       /* [7:4] 48 kHz SPDIF not used */
+       hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
+
+       /*
+        * [6:5] set required down sampling rate if required
+        * [4:3] set required audio source
+        */
+       hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1);
+
+       /* [3:0] set sending channel number for channel status */
+       hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
+
+       /*
+        * [5:2] set valid I2S source input pin
+        * [1:0] set input I2S source mode
+        */
+       hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
+
+       /* [7:4] set valid DSD source input pin */
+       hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
+
+       /* [7:0] set appropriate I2S input pin swap settings if required */
+       hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
+
+       /*
+        * [7] set validity bit for channel status
+        * [3:0] set original sample frequency for channel status
+        */
+       hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
+
+       /*
+        * [7] set value for channel status
+        * [6] set value for channel status
+        * [5] set copyright bit for channel status
+        * [4:2] set additional information for channel status
+        * [1:0] set clock accuracy for channel status
+        */
+       hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
+
+       /* [7:0] set category code for channel status */
+       hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
+
+       /*
+        * [7:4] set source number for channel status
+        * [3:0] set word length for channel status
+        */
+       hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
+
+       /* [7:4] set sample frequency for channel status */
+       hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
+}
+
+/**
+ * sh_hdmi_phy_config()
+ */
+static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
+{
+       /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
+       hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
+       hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
+       hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
+       /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
+       hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
+       hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
+       hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
+       hdmi_write(hdmi, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
+       hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
+       hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
+}
+
+/**
+ * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
+ */
+static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
+{
+       /* AVI InfoFrame */
+       hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
+
+       /* Packet Type = 0x82 */
+       hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
+
+       /* Version = 0x02 */
+       hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
+
+       /* Length = 13 (0x0D) */
+       hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
+
+       /* N. A. Checksum */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
+
+       /*
+        * Y = RGB
+        * A0 = No Data
+        * B = Bar Data not valid
+        * S = No Data
+        */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
+
+       /*
+        * C = No Data
+        * M = 16:9 Picture Aspect Ratio
+        * R = Same as picture aspect ratio
+        */
+       hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
+
+       /*
+        * ITC = No Data
+        * EC = xvYCC601
+        * Q = Default (depends on video format)
+        * SC = No Known non_uniform Scaling
+        */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
+
+       /*
+        * VIC = 1280 x 720p: ignored if external config is used
+        * Send 2 for 720 x 480p, 16 for 1080p
+        */
+       hdmi_write(hdmi, 4, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
+
+       /* PR = No Repetition */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
+
+       /* Line Number of End of Top Bar (lower 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
+
+       /* Line Number of End of Top Bar (upper 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
+
+       /* Line Number of Start of Bottom Bar (lower 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
+
+       /* Line Number of Start of Bottom Bar (upper 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
+
+       /* Pixel Number of End of Left Bar (lower 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
+
+       /* Pixel Number of End of Left Bar (upper 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
+
+       /* Pixel Number of Start of Right Bar (lower 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
+
+       /* Pixel Number of Start of Right Bar (upper 8 bits) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
+}
+
+/**
+ * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
+ */
+static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
+{
+       /* Audio InfoFrame */
+       hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
+
+       /* Packet Type = 0x84 */
+       hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
+
+       /* Version Number = 0x01 */
+       hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
+
+       /* 0 Length = 10 (0x0A) */
+       hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
+
+       /* n. a. Checksum */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
+
+       /* Audio Channel Count = Refer to Stream Header */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
+
+       /* Refer to Stream Header */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
+
+       /* Format depends on coding type (i.e. CT0...CT3) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
+
+       /* Speaker Channel Allocation = Front Right + Front Left */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
+
+       /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
+
+       /* Reserved (0) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
+}
+
+/**
+ * sh_hdmi_gamut_metadata_setup() - Gamut Metadata Packet of CONTROL PACKET
+ */
+static void sh_hdmi_gamut_metadata_setup(struct sh_hdmi *hdmi)
+{
+       int i;
+
+       /* Gamut Metadata Packet */
+       hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_INDEX);
+
+       /* Packet Type = 0x0A */
+       hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
+       /* Gamut Packet is not used, so default value */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
+       /* Gamut Packet is not used, so default value */
+       hdmi_write(hdmi, 0x10, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
+
+       /* GBD bytes 0 through 27 */
+       for (i = 0; i <= 27; i++)
+               /* HDMI_CTRL_PKT_BUF_ACCESS_PB0_63H - PB27_7EH */
+               hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
+}
+
+/**
+ * sh_hdmi_acp_setup() - Audio Content Protection Packet (ACP)
+ */
+static void sh_hdmi_acp_setup(struct sh_hdmi *hdmi)
+{
+       int i;
+
+       /* Audio Content Protection Packet (ACP) */
+       hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_INDEX);
+
+       /* Packet Type = 0x04 */
+       hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
+       /* ACP_Type */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
+       /* Reserved (0) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
+
+       /* GBD bytes 0 through 27 */
+       for (i = 0; i <= 27; i++)
+               /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
+               hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
+}
+
+/**
+ * sh_hdmi_isrc1_setup() - ISRC1 Packet
+ */
+static void sh_hdmi_isrc1_setup(struct sh_hdmi *hdmi)
+{
+       int i;
+
+       /* ISRC1 Packet */
+       hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_INDEX);
+
+       /* Packet Type = 0x05 */
+       hdmi_write(hdmi, 0x05, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
+       /* ISRC_Cont, ISRC_Valid, Reserved (0), ISRC_Status */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
+       /* Reserved (0) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
+
+       /* PB0 UPC_EAN_ISRC_0-15 */
+       /* Bytes PB16-PB27 shall be set to a value of 0. */
+       for (i = 0; i <= 27; i++)
+               /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
+               hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
+}
+
+/**
+ * sh_hdmi_isrc2_setup() - ISRC2 Packet
+ */
+static void sh_hdmi_isrc2_setup(struct sh_hdmi *hdmi)
+{
+       int i;
+
+       /* ISRC2 Packet */
+       hdmi_write(hdmi, 0x03, HDMI_CTRL_PKT_BUF_INDEX);
+
+       /* HB0 Packet Type = 0x06 */
+       hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
+       /* Reserved (0) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
+       /* Reserved (0) */
+       hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
+
+       /* PB0 UPC_EAN_ISRC_16-31 */
+       /* Bytes PB16-PB27 shall be set to a value of 0. */
+       for (i = 0; i <= 27; i++)
+               /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
+               hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
+}
+
+/**
+ * sh_hdmi_configure() - Initialise HDMI for output
+ */
+static void sh_hdmi_configure(struct sh_hdmi *hdmi)
+{
+       /* Configure video format */
+       sh_hdmi_video_config(hdmi);
+
+       /* Configure audio format */
+       sh_hdmi_audio_config(hdmi);
+
+       /* Configure PHY */
+       sh_hdmi_phy_config(hdmi);
+
+       /* Auxiliary Video Information (AVI) InfoFrame */
+       sh_hdmi_avi_infoframe_setup(hdmi);
+
+       /* Audio InfoFrame */
+       sh_hdmi_audio_infoframe_setup(hdmi);
+
+       /* Gamut Metadata packet */
+       sh_hdmi_gamut_metadata_setup(hdmi);
+
+       /* Audio Content Protection (ACP) Packet */
+       sh_hdmi_acp_setup(hdmi);
+
+       /* ISRC1 Packet */
+       sh_hdmi_isrc1_setup(hdmi);
+
+       /* ISRC2 Packet */
+       sh_hdmi_isrc2_setup(hdmi);
+
+       /*
+        * Control packet auto send with VSYNC control: auto send
+        * General control, Gamut metadata, ISRC, and ACP packets
+        */
+       hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
+
+       /* FIXME */
+       msleep(10);
+
+       /* PS mode b->d, reset PLLA and PLLB */
+       hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
+
+       udelay(10);
+
+       hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
+}
+
+static void sh_hdmi_read_edid(struct sh_hdmi *hdmi)
+{
+       struct fb_var_screeninfo *var = &hdmi->var;
+       struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+       struct fb_videomode *lcd_cfg = &pdata->lcd_chan->lcd_cfg;
+       unsigned long height = var->height, width = var->width;
+       int i;
+       u8 edid[128];
+
+       /* Read EDID */
+       pr_debug("Read back EDID code:");
+       for (i = 0; i < 128; i++) {
+               edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
+#ifdef DEBUG
+               if ((i % 16) == 0) {
+                       printk(KERN_CONT "\n");
+                       printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
+               } else {
+                       printk(KERN_CONT " %02X", edid[i]);
+               }
+#endif
+       }
+#ifdef DEBUG
+       printk(KERN_CONT "\n");
+#endif
+       fb_parse_edid(edid, var);
+       pr_debug("%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
+                var->left_margin, var->xres, var->right_margin, var->hsync_len,
+                var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
+                PICOS2KHZ(var->pixclock));
+
+       /* FIXME: Use user-provided configuration instead of EDID */
+       var->width              = width;
+       var->xres               = lcd_cfg->xres;
+       var->xres_virtual       = lcd_cfg->xres;
+       var->left_margin        = lcd_cfg->left_margin;
+       var->right_margin       = lcd_cfg->right_margin;
+       var->hsync_len          = lcd_cfg->hsync_len;
+       var->height             = height;
+       var->yres               = lcd_cfg->yres;
+       var->yres_virtual       = lcd_cfg->yres * 2;
+       var->upper_margin       = lcd_cfg->upper_margin;
+       var->lower_margin       = lcd_cfg->lower_margin;
+       var->vsync_len          = lcd_cfg->vsync_len;
+       var->sync               = lcd_cfg->sync;
+       var->pixclock           = lcd_cfg->pixclock;
+
+       hdmi_external_video_param(hdmi);
+}
+
+static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
+{
+       struct sh_hdmi *hdmi = dev_id;
+       u8 status1, status2, mask1, mask2;
+
+       /* mode_b and PLLA and PLLB reset */
+       hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
+
+       /* How long shall reset be held? */
+       udelay(10);
+
+       /* mode_b and PLLA and PLLB reset release */
+       hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
+
+       status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
+       status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
+
+       mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
+       mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
+
+       /* Correct would be to ack only set bits, but the datasheet requires 0xff */
+       hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
+       hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
+
+       if (printk_ratelimit())
+               pr_debug("IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
+                        irq, status1, mask1, status2, mask2);
+
+       if (!((status1 & mask1) | (status2 & mask2))) {
+               return IRQ_NONE;
+       } else if (status1 & 0xc0) {
+               u8 msens;
+
+               /* Datasheet specifies 10ms... */
+               udelay(500);
+
+               msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
+               pr_debug("MSENS 0x%x\n", msens);
+               /* Check, if hot plug & MSENS pin status are both high */
+               if ((msens & 0xC0) == 0xC0) {
+                       /* Display plug in */
+                       hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
+
+                       /* Set EDID word address  */
+                       hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
+                       /* Set EDID segment pointer */
+                       hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
+                       /* Enable EDID interrupt */
+                       hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
+               } else if (!(status1 & 0x80)) {
+                       /* Display unplug, beware multiple interrupts */
+                       if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
+                               schedule_delayed_work(&hdmi->edid_work, 0);
+
+                       hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
+                       /* display_off will switch back to mode_a */
+               }
+       } else if (status1 & 2) {
+               /* EDID error interrupt: retry */
+               /* Set EDID word address  */
+               hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
+               /* Set EDID segment pointer */
+               hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
+       } else if (status1 & 4) {
+               /* Disable EDID interrupt */
+               hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
+               hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
+               schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
+       }
+
+       return IRQ_HANDLED;
+}
+
+static void hdmi_display_on(void *arg, struct fb_info *info)
+{
+       struct sh_hdmi *hdmi = arg;
+       struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+
+       if (info->var.xres != 1280 || info->var.yres != 720) {
+               dev_warn(info->device, "Unsupported framebuffer geometry %ux%u\n",
+                        info->var.xres, info->var.yres);
+               return;
+       }
+
+       pr_debug("%s(%p): state %x\n", __func__, pdata->lcd_dev, info->state);
+       /*
+        * FIXME: not a good place to store fb_info. And we cannot nullify it
+        * even on monitor disconnect. What should the lifecycle be?
+        */
+       hdmi->info = info;
+       switch (hdmi->hp_state) {
+       case HDMI_HOTPLUG_EDID_DONE:
+               /* PS mode d->e. All functions are active */
+               hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
+               pr_debug("HDMI running\n");
+               break;
+       case HDMI_HOTPLUG_DISCONNECTED:
+               info->state = FBINFO_STATE_SUSPENDED;
+       default:
+               hdmi->var = info->var;
+       }
+}
+
+static void hdmi_display_off(void *arg)
+{
+       struct sh_hdmi *hdmi = arg;
+       struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+
+       pr_debug("%s(%p)\n", __func__, pdata->lcd_dev);
+       /* PS mode e->a */
+       hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
+}
+
+/* Hotplug interrupt occurred, read EDID */
+static void edid_work_fn(struct work_struct *work)
+{
+       struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
+       struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+
+       pr_debug("%s(%p): begin, hotplug status %d\n", __func__,
+                pdata->lcd_dev, hdmi->hp_state);
+
+       if (!pdata->lcd_dev)
+               return;
+
+       if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
+               pm_runtime_get_sync(hdmi->dev);
+               /* A device has been plugged in */
+               sh_hdmi_read_edid(hdmi);
+               msleep(10);
+               sh_hdmi_configure(hdmi);
+               /* Switched to another (d) power-save mode */
+               msleep(10);
+
+               if (!hdmi->info)
+                       return;
+
+               acquire_console_sem();
+
+               /* HDMI plug in */
+               hdmi->info->var = hdmi->var;
+               if (hdmi->info->state != FBINFO_STATE_RUNNING)
+                       fb_set_suspend(hdmi->info, 0);
+               else
+                       hdmi_display_on(hdmi, hdmi->info);
+
+               release_console_sem();
+       } else {
+               if (!hdmi->info)
+                       return;
+
+               acquire_console_sem();
+
+               /* HDMI disconnect */
+               fb_set_suspend(hdmi->info, 1);
+
+               release_console_sem();
+               pm_runtime_put(hdmi->dev);
+       }
+
+       pr_debug("%s(%p): end\n", __func__, pdata->lcd_dev);
+}
+
+static int __init sh_hdmi_probe(struct platform_device *pdev)
+{
+       struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       int irq = platform_get_irq(pdev, 0), ret;
+       struct sh_hdmi *hdmi;
+       long rate;
+
+       if (!res || !pdata || irq < 0)
+               return -ENODEV;
+
+       hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
+       if (!hdmi) {
+               dev_err(&pdev->dev, "Cannot allocate device data\n");
+               return -ENOMEM;
+       }
+
+       hdmi->dev = &pdev->dev;
+
+       hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
+       if (IS_ERR(hdmi->hdmi_clk)) {
+               ret = PTR_ERR(hdmi->hdmi_clk);
+               dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
+               goto egetclk;
+       }
+
+       rate = PICOS2KHZ(pdata->lcd_chan->lcd_cfg.pixclock) * 1000;
+
+       rate = clk_round_rate(hdmi->hdmi_clk, rate);
+       if (rate < 0) {
+               ret = rate;
+               dev_err(&pdev->dev, "Cannot get suitable rate: %ld\n", rate);
+               goto erate;
+       }
+
+       ret = clk_set_rate(hdmi->hdmi_clk, rate);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "Cannot set rate %ld: %d\n", rate, ret);
+               goto erate;
+       }
+
+       pr_debug("HDMI set frequency %lu\n", rate);
+
+       ret = clk_enable(hdmi->hdmi_clk);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "Cannot enable clock: %d\n", ret);
+               goto eclkenable;
+       }
+
+       dev_info(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
+
+       if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
+               dev_err(&pdev->dev, "HDMI register region already claimed\n");
+               ret = -EBUSY;
+               goto ereqreg;
+       }
+
+       hdmi->base = ioremap(res->start, resource_size(res));
+       if (!hdmi->base) {
+               dev_err(&pdev->dev, "HDMI register region already claimed\n");
+               ret = -ENOMEM;
+               goto emap;
+       }
+
+       platform_set_drvdata(pdev, hdmi);
+
+#if 1
+       /* Product and revision IDs are 0 in sh-mobile version */
+       dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
+                hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
+#endif
+
+       /* Set up LCDC callbacks */
+       pdata->lcd_chan->board_cfg.board_data = hdmi;
+       pdata->lcd_chan->board_cfg.display_on = hdmi_display_on;
+       pdata->lcd_chan->board_cfg.display_off = hdmi_display_off;
+
+       INIT_DELAYED_WORK(&hdmi->edid_work, edid_work_fn);
+
+       pm_runtime_enable(&pdev->dev);
+       pm_runtime_resume(&pdev->dev);
+
+       ret = request_irq(irq, sh_hdmi_hotplug, 0,
+                         dev_name(&pdev->dev), hdmi);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
+               goto ereqirq;
+       }
+
+       return 0;
+
+ereqirq:
+       pm_runtime_disable(&pdev->dev);
+       iounmap(hdmi->base);
+emap:
+       release_mem_region(res->start, resource_size(res));
+ereqreg:
+       clk_disable(hdmi->hdmi_clk);
+eclkenable:
+erate:
+       clk_put(hdmi->hdmi_clk);
+egetclk:
+       kfree(hdmi);
+
+       return ret;
+}
+
+static int __exit sh_hdmi_remove(struct platform_device *pdev)
+{
+       struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
+       struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       int irq = platform_get_irq(pdev, 0);
+
+       pdata->lcd_chan->board_cfg.display_on = NULL;
+       pdata->lcd_chan->board_cfg.display_off = NULL;
+       pdata->lcd_chan->board_cfg.board_data = NULL;
+
+       free_irq(irq, hdmi);
+       pm_runtime_disable(&pdev->dev);
+       cancel_delayed_work_sync(&hdmi->edid_work);
+       clk_disable(hdmi->hdmi_clk);
+       clk_put(hdmi->hdmi_clk);
+       iounmap(hdmi->base);
+       release_mem_region(res->start, resource_size(res));
+       kfree(hdmi);
+
+       return 0;
+}
+
+static struct platform_driver sh_hdmi_driver = {
+       .remove         = __exit_p(sh_hdmi_remove),
+       .driver = {
+               .name   = "sh-mobile-hdmi",
+       },
+};
+
+static int __init sh_hdmi_init(void)
+{
+       return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
+}
+module_init(sh_hdmi_init);
+
+static void __exit sh_hdmi_exit(void)
+{
+       platform_driver_unregister(&sh_hdmi_driver);
+}
+module_exit(sh_hdmi_exit);
+
+MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
+MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
+MODULE_LICENSE("GPL v2");
index 12c451a711e935d767d74677923b1202f0ed629f..d72075a9f01c367ceb9e573f3a475774db6a4b80 100644 (file)
@@ -56,6 +56,7 @@ static int lcdc_shared_regs[] = {
 /* per-channel registers */
 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
        LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
+       LDHAJR,
        NR_CH_REGS };
 
 static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
@@ -74,6 +75,7 @@ static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
        [LDVLNR] = 0x450,
        [LDVSYNR] = 0x454,
        [LDPMR] = 0x460,
+       [LDHAJR] = 0x4a0,
 };
 
 static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
@@ -137,6 +139,7 @@ struct sh_mobile_lcdc_priv {
        struct clk *dot_clk;
        unsigned long lddckr;
        struct sh_mobile_lcdc_chan ch[2];
+       struct notifier_block notifier;
        unsigned long saved_shared_regs[NR_SHARED_REGS];
        int started;
 };
@@ -404,6 +407,56 @@ static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
                lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
 }
 
+static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
+{
+       struct fb_var_screeninfo *var = &ch->info->var;
+       unsigned long h_total, hsync_pos;
+       u32 tmp;
+
+       tmp = ch->ldmt1r_value;
+       tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
+       tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
+       tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
+       tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
+       tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
+       tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
+       tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
+       lcdc_write_chan(ch, LDMT1R, tmp);
+
+       /* setup SYS bus */
+       lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
+       lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
+
+       /* horizontal configuration */
+       h_total = var->xres + var->hsync_len +
+               var->left_margin + var->right_margin;
+       tmp = h_total / 8; /* HTCN */
+       tmp |= (var->xres / 8) << 16; /* HDCN */
+       lcdc_write_chan(ch, LDHCNR, tmp);
+
+       hsync_pos = var->xres + var->right_margin;
+       tmp = hsync_pos / 8; /* HSYNP */
+       tmp |= (var->hsync_len / 8) << 16; /* HSYNW */
+       lcdc_write_chan(ch, LDHSYNR, tmp);
+
+       /* vertical configuration */
+       tmp = var->yres + var->vsync_len +
+               var->upper_margin + var->lower_margin; /* VTLN */
+       tmp |= var->yres << 16; /* VDLN */
+       lcdc_write_chan(ch, LDVLNR, tmp);
+
+       tmp = var->yres + var->lower_margin; /* VSYNP */
+       tmp |= var->vsync_len << 16; /* VSYNW */
+       lcdc_write_chan(ch, LDVSYNR, tmp);
+
+       /* Adjust horizontal synchronisation for HDMI */
+       tmp = ((var->xres & 7) << 24) |
+               ((h_total & 7) << 16) |
+               ((var->hsync_len & 7) << 8) |
+               hsync_pos;
+       lcdc_write_chan(ch, LDHAJR, tmp);
+}
+
 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
 {
        struct sh_mobile_lcdc_chan *ch;
@@ -470,49 +523,11 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
                if (!ch->enabled)
                        continue;
 
-               tmp = ch->ldmt1r_value;
-               tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
-               tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
-               tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
-               tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
-               tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
-               tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
-               tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
-               lcdc_write_chan(ch, LDMT1R, tmp);
-
-               /* setup SYS bus */
-               lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
-               lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
-
-               /* horizontal configuration */
-               tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
-               tmp += lcd_cfg->left_margin;
-               tmp += lcd_cfg->right_margin;
-               tmp /= 8; /* HTCN */
-               tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
-               lcdc_write_chan(ch, LDHCNR, tmp);
-
-               tmp = lcd_cfg->xres;
-               tmp += lcd_cfg->right_margin;
-               tmp /= 8; /* HSYNP */
-               tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
-               lcdc_write_chan(ch, LDHSYNR, tmp);
+               sh_mobile_lcdc_geometry(ch);
 
                /* power supply */
                lcdc_write_chan(ch, LDPMR, 0);
 
-               /* vertical configuration */
-               tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
-               tmp += lcd_cfg->upper_margin;
-               tmp += lcd_cfg->lower_margin; /* VTLN */
-               tmp |= lcd_cfg->yres << 16; /* VDLN */
-               lcdc_write_chan(ch, LDVLNR, tmp);
-
-               tmp = lcd_cfg->yres;
-               tmp += lcd_cfg->lower_margin; /* VSYNP */
-               tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
-               lcdc_write_chan(ch, LDVSYNR, tmp);
-
                board_cfg = &ch->cfg.board_cfg;
                if (board_cfg->setup_sys)
                        ret = board_cfg->setup_sys(board_cfg->board_data, ch,
@@ -577,7 +592,7 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
 
                board_cfg = &ch->cfg.board_cfg;
                if (board_cfg->display_on)
-                       board_cfg->display_on(board_cfg->board_data);
+                       board_cfg->display_on(board_cfg->board_data, ch->info);
        }
 
        return 0;
@@ -943,6 +958,62 @@ static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
        .runtime_resume = sh_mobile_lcdc_runtime_resume,
 };
 
+static int sh_mobile_lcdc_notify(struct notifier_block *nb,
+                                unsigned long action, void *data)
+{
+       struct fb_event *event = data;
+       struct fb_info *info = event->info;
+       struct sh_mobile_lcdc_chan *ch = info->par;
+       struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
+       struct fb_var_screeninfo *var;
+
+       if (&ch->lcdc->notifier != nb)
+               return 0;
+
+       dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
+               __func__, action, event->data);
+
+       switch(action) {
+       case FB_EVENT_SUSPEND:
+               if (board_cfg->display_off)
+                       board_cfg->display_off(board_cfg->board_data);
+               pm_runtime_put(info->device);
+               break;
+       case FB_EVENT_RESUME:
+               var = &info->var;
+
+               /* HDMI must be enabled before LCDC configuration */
+               if (board_cfg->display_on)
+                       board_cfg->display_on(board_cfg->board_data, ch->info);
+
+               /* Check if the new display is not in our modelist */
+               if (ch->info->modelist.next &&
+                   !fb_match_mode(var, &ch->info->modelist)) {
+                       struct fb_videomode mode;
+                       int ret;
+
+                       /* Can we handle this display? */
+                       if (var->xres > ch->cfg.lcd_cfg.xres ||
+                           var->yres > ch->cfg.lcd_cfg.yres)
+                               return -ENOMEM;
+
+                       /* Add to the modelist */
+                       fb_var_to_videomode(&mode, var);
+                       ret = fb_add_videomode(&mode, &ch->info->modelist);
+                       if (ret < 0)
+                               return ret;
+               }
+
+               pm_runtime_get_sync(info->device);
+
+               sh_mobile_lcdc_geometry(ch);
+
+               break;
+       }
+
+       return 0;
+}
+
 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
 
 static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
@@ -1020,15 +1091,19 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                goto err1;
        }
 
+       priv->base = ioremap_nocache(res->start, resource_size(res));
+       if (!priv->base)
+               goto err1;
+
        error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
        if (error) {
                dev_err(&pdev->dev, "unable to setup clocks\n");
                goto err1;
        }
 
-       priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
-
        for (i = 0; i < j; i++) {
+               struct fb_var_screeninfo *var;
+               struct fb_videomode *lcd_cfg;
                cfg = &priv->ch[i].cfg;
 
                priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
@@ -1039,22 +1114,33 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                }
 
                info = priv->ch[i].info;
+               var = &info->var;
+               lcd_cfg = &cfg->lcd_cfg;
                info->fbops = &sh_mobile_lcdc_ops;
-               info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
-               info->var.yres = cfg->lcd_cfg.yres;
+               var->xres = var->xres_virtual = lcd_cfg->xres;
+               var->yres = lcd_cfg->yres;
                /* Default Y virtual resolution is 2x panel size */
-               info->var.yres_virtual = info->var.yres * 2;
-               info->var.width = cfg->lcd_size_cfg.width;
-               info->var.height = cfg->lcd_size_cfg.height;
-               info->var.activate = FB_ACTIVATE_NOW;
-               error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
+               var->yres_virtual = var->yres * 2;
+               var->width = cfg->lcd_size_cfg.width;
+               var->height = cfg->lcd_size_cfg.height;
+               var->activate = FB_ACTIVATE_NOW;
+               var->left_margin = lcd_cfg->left_margin;
+               var->right_margin = lcd_cfg->right_margin;
+               var->upper_margin = lcd_cfg->upper_margin;
+               var->lower_margin = lcd_cfg->lower_margin;
+               var->hsync_len = lcd_cfg->hsync_len;
+               var->vsync_len = lcd_cfg->vsync_len;
+               var->sync = lcd_cfg->sync;
+               var->pixclock = lcd_cfg->pixclock;
+
+               error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
                if (error)
                        break;
 
                info->fix = sh_mobile_lcdc_fix;
-               info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
+               info->fix.line_length = lcd_cfg->xres * (cfg->bpp / 8);
                info->fix.smem_len = info->fix.line_length *
-                       info->var.yres_virtual;
+                       var->yres_virtual;
 
                buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
                                         &priv->ch[i].dma_handle, GFP_KERNEL);
@@ -1119,10 +1205,14 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
                         ch->cfg.bpp);
 
                /* deferred io mode: disable clock to save power */
-               if (info->fbdefio)
+               if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
                        sh_mobile_lcdc_clk_off(priv);
        }
 
+       /* Failure ignored */
+       priv->notifier.notifier_call = sh_mobile_lcdc_notify;
+       fb_register_client(&priv->notifier);
+
        return 0;
 err1:
        sh_mobile_lcdc_remove(pdev);
@@ -1136,6 +1226,8 @@ static int sh_mobile_lcdc_remove(struct platform_device *pdev)
        struct fb_info *info;
        int i;
 
+       fb_unregister_client(&priv->notifier);
+
        for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
                if (priv->ch[i].info && priv->ch[i].info->dev)
                        unregister_framebuffer(priv->ch[i].info);
index f10db6e5f3b59f82cacb7303cd7e856d101acdcf..522832023a698369c87916a5844e39046245eb22 100644 (file)
 #define PORT_ALTERA_JTAGUART   91
 #define PORT_ALTERA_UART       92
 
+/* SH-SCI */
+#define PORT_SCIFB     93
+
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
index 1636d1e2a5f1b9ef73fd22bf5181a41e22ef2775..875ce50719a952d3f42e69badf9ede21f2743ac0 100644 (file)
@@ -25,6 +25,10 @@ struct clk {
        int                     id;
 
        struct clk              *parent;
+       struct clk              **parent_table; /* list of parents to */
+       unsigned short          parent_num;     /* choose between */
+       unsigned char           src_shift;      /* source clock field in the */
+       unsigned char           src_width;      /* configuration register */
        struct clk_ops          *ops;
 
        struct list_head        children;
@@ -138,13 +142,22 @@ int sh_clk_div4_enable_register(struct clk *clks, int nr,
 int sh_clk_div4_reparent_register(struct clk *clks, int nr,
                         struct clk_div4_table *table);
 
-#define SH_CLK_DIV6(_parent, _reg, _flags)     \
-{                                              \
-       .parent = _parent,                      \
-       .enable_reg = (void __iomem *)_reg,     \
-       .flags = _flags,                        \
+#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents,       \
+                       _num_parents, _src_shift, _src_width)   \
+{                                                              \
+       .parent = _parent,                                      \
+       .enable_reg = (void __iomem *)_reg,                     \
+       .flags = _flags,                                        \
+       .parent_table = _parents,                               \
+       .parent_num = _num_parents,                             \
+       .src_shift = _src_shift,                                \
+       .src_width = _src_width,                                \
 }
 
+#define SH_CLK_DIV6(_parent, _reg, _flags)                     \
+       SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)
+
 int sh_clk_div6_register(struct clk *clks, int nr);
+int sh_clk_div6_reparent_register(struct clk *clks, int nr);
 
 #endif /* __SH_CLOCK_H */
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
new file mode 100644 (file)
index 0000000..ddcc8ca
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * Defines for Mobile Industry Processor Interface (MIPI(R))
+ * Display Working Group standards: DSI, DCS, DBI, DPI
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright (C) 2006 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef MIPI_DISPLAY_H
+#define MIPI_DISPLAY_H
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+       MIPI_DSI_V_SYNC_START                           = 0x01,
+       MIPI_DSI_V_SYNC_END                             = 0x11,
+       MIPI_DSI_H_SYNC_START                           = 0x21,
+       MIPI_DSI_H_SYNC_END                             = 0x31,
+
+       MIPI_DSI_COLOR_MODE_OFF                         = 0x02,
+       MIPI_DSI_COLOR_MODE_ON                          = 0x12,
+       MIPI_DSI_SHUTDOWN_PERIPHERAL                    = 0x22,
+       MIPI_DSI_TURN_ON_PERIPHERAL                     = 0x32,
+
+       MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM            = 0x03,
+       MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM            = 0x13,
+       MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM            = 0x23,
+
+       MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM           = 0x04,
+       MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM           = 0x14,
+       MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM           = 0x24,
+
+       MIPI_DSI_DCS_SHORT_WRITE                        = 0x05,
+       MIPI_DSI_DCS_SHORT_WRITE_PARAM                  = 0x15,
+
+       MIPI_DSI_DCS_READ                               = 0x06,
+
+       MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE         = 0x37,
+
+       MIPI_DSI_END_OF_TRANSMISSION                    = 0x08,
+
+       MIPI_DSI_NULL_PACKET                            = 0x09,
+       MIPI_DSI_BLANKING_PACKET                        = 0x19,
+       MIPI_DSI_GENERIC_LONG_WRITE                     = 0x29,
+       MIPI_DSI_DCS_LONG_WRITE                         = 0x39,
+
+       MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20    = 0x0c,
+       MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24            = 0x1c,
+       MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16            = 0x2c,
+
+       MIPI_DSI_PACKED_PIXEL_STREAM_30                 = 0x0d,
+       MIPI_DSI_PACKED_PIXEL_STREAM_36                 = 0x1d,
+       MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12            = 0x3d,
+
+       MIPI_DSI_PACKED_PIXEL_STREAM_16                 = 0x0e,
+       MIPI_DSI_PACKED_PIXEL_STREAM_18                 = 0x1e,
+       MIPI_DSI_PIXEL_STREAM_3BYTE_18                  = 0x2e,
+       MIPI_DSI_PACKED_PIXEL_STREAM_24                 = 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+       MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT        = 0x02,
+       MIPI_DSI_RX_END_OF_TRANSMISSION                 = 0x08,
+       MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE   = 0x11,
+       MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE   = 0x12,
+       MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE          = 0x1a,
+       MIPI_DSI_RX_DCS_LONG_READ_RESPONSE              = 0x1c,
+       MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE       = 0x21,
+       MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE       = 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+       MIPI_DCS_NOP                    = 0x00,
+       MIPI_DCS_SOFT_RESET             = 0x01,
+       MIPI_DCS_GET_DISPLAY_ID         = 0x04,
+       MIPI_DCS_GET_RED_CHANNEL        = 0x06,
+       MIPI_DCS_GET_GREEN_CHANNEL      = 0x07,
+       MIPI_DCS_GET_BLUE_CHANNEL       = 0x08,
+       MIPI_DCS_GET_DISPLAY_STATUS     = 0x09,
+       MIPI_DCS_GET_POWER_MODE         = 0x0A,
+       MIPI_DCS_GET_ADDRESS_MODE       = 0x0B,
+       MIPI_DCS_GET_PIXEL_FORMAT       = 0x0C,
+       MIPI_DCS_GET_DISPLAY_MODE       = 0x0D,
+       MIPI_DCS_GET_SIGNAL_MODE        = 0x0E,
+       MIPI_DCS_GET_DIAGNOSTIC_RESULT  = 0x0F,
+       MIPI_DCS_ENTER_SLEEP_MODE       = 0x10,
+       MIPI_DCS_EXIT_SLEEP_MODE        = 0x11,
+       MIPI_DCS_ENTER_PARTIAL_MODE     = 0x12,
+       MIPI_DCS_ENTER_NORMAL_MODE      = 0x13,
+       MIPI_DCS_EXIT_INVERT_MODE       = 0x20,
+       MIPI_DCS_ENTER_INVERT_MODE      = 0x21,
+       MIPI_DCS_SET_GAMMA_CURVE        = 0x26,
+       MIPI_DCS_SET_DISPLAY_OFF        = 0x28,
+       MIPI_DCS_SET_DISPLAY_ON         = 0x29,
+       MIPI_DCS_SET_COLUMN_ADDRESS     = 0x2A,
+       MIPI_DCS_SET_PAGE_ADDRESS       = 0x2B,
+       MIPI_DCS_WRITE_MEMORY_START     = 0x2C,
+       MIPI_DCS_WRITE_LUT              = 0x2D,
+       MIPI_DCS_READ_MEMORY_START      = 0x2E,
+       MIPI_DCS_SET_PARTIAL_AREA       = 0x30,
+       MIPI_DCS_SET_SCROLL_AREA        = 0x33,
+       MIPI_DCS_SET_TEAR_OFF           = 0x34,
+       MIPI_DCS_SET_TEAR_ON            = 0x35,
+       MIPI_DCS_SET_ADDRESS_MODE       = 0x36,
+       MIPI_DCS_SET_SCROLL_START       = 0x37,
+       MIPI_DCS_EXIT_IDLE_MODE         = 0x38,
+       MIPI_DCS_ENTER_IDLE_MODE        = 0x39,
+       MIPI_DCS_SET_PIXEL_FORMAT       = 0x3A,
+       MIPI_DCS_WRITE_MEMORY_CONTINUE  = 0x3C,
+       MIPI_DCS_READ_MEMORY_CONTINUE   = 0x3E,
+       MIPI_DCS_SET_TEAR_SCANLINE      = 0x44,
+       MIPI_DCS_GET_SCANLINE           = 0x45,
+       MIPI_DCS_READ_DDB_START         = 0xA1,
+       MIPI_DCS_READ_DDB_CONTINUE      = 0xA8,
+};
+
+/* MIPI DCS pixel formats */
+#define MIPI_DCS_PIXEL_FMT_24BIT       7
+#define MIPI_DCS_PIXEL_FMT_18BIT       6
+#define MIPI_DCS_PIXEL_FMT_16BIT       5
+#define MIPI_DCS_PIXEL_FMT_12BIT       3
+#define MIPI_DCS_PIXEL_FMT_8BIT                2
+#define MIPI_DCS_PIXEL_FMT_3BIT                1
+
+#endif
diff --git a/include/video/sh_mipi_dsi.h b/include/video/sh_mipi_dsi.h
new file mode 100644 (file)
index 0000000..18bca08
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Public SH-mobile MIPI DSI header
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef VIDEO_SH_MIPI_DSI_H
+#define VIDEO_SH_MIPI_DSI_H
+
+enum sh_mipi_dsi_data_fmt {
+       MIPI_RGB888,
+       MIPI_RGB565,
+       MIPI_RGB666_LP,
+       MIPI_RGB666,
+       MIPI_BGR888,
+       MIPI_BGR565,
+       MIPI_BGR666_LP,
+       MIPI_BGR666,
+       MIPI_YUYV,
+       MIPI_UYVY,
+       MIPI_YUV420_L,
+       MIPI_YUV420,
+};
+
+struct sh_mobile_lcdc_chan_cfg;
+
+struct sh_mipi_dsi_info {
+       enum sh_mipi_dsi_data_fmt       data_format;
+       struct sh_mobile_lcdc_chan_cfg  *lcd_chan;
+};
+
+#endif
diff --git a/include/video/sh_mobile_hdmi.h b/include/video/sh_mobile_hdmi.h
new file mode 100644 (file)
index 0000000..577cf18
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * SH-Mobile High-Definition Multimedia Interface (HDMI)
+ *
+ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef SH_MOBILE_HDMI_H
+#define SH_MOBILE_HDMI_H
+
+struct sh_mobile_lcdc_chan_cfg;
+struct device;
+
+struct sh_mobile_hdmi_info {
+       struct sh_mobile_lcdc_chan_cfg  *lcd_chan;
+       struct device                   *lcd_dev;
+};
+
+#endif
index 288205457713bab6191e42e7a8f99bd01861ec51..55d700e8566e6fe1dcb8f1c6ec3e35ff37678c7f 100644 (file)
@@ -3,24 +3,27 @@
 
 #include <linux/fb.h>
 
-enum { RGB8,   /* 24bpp, 8:8:8 */
-       RGB9,   /* 18bpp, 9:9 */
-       RGB12A, /* 24bpp, 12:12 */
-       RGB12B, /* 12bpp */
-       RGB16,  /* 16bpp */
-       RGB18,  /* 18bpp */
-       RGB24,  /* 24bpp */
-       SYS8A,  /* 24bpp, 8:8:8 */
-       SYS8B,  /* 18bpp, 8:8:2 */
-       SYS8C,  /* 18bpp, 2:8:8 */
-       SYS8D,  /* 16bpp, 8:8 */
-       SYS9,   /* 18bpp, 9:9 */
-       SYS12,  /* 24bpp, 12:12 */
-       SYS16A, /* 16bpp */
-       SYS16B, /* 18bpp, 16:2 */
-       SYS16C, /* 18bpp, 2:16 */
-       SYS18,  /* 18bpp */
-       SYS24 };/* 24bpp */
+enum {
+       RGB8,   /* 24bpp, 8:8:8 */
+       RGB9,   /* 18bpp, 9:9 */
+       RGB12A, /* 24bpp, 12:12 */
+       RGB12B, /* 12bpp */
+       RGB16,  /* 16bpp */
+       RGB18,  /* 18bpp */
+       RGB24,  /* 24bpp */
+       YUV422, /* 16bpp */
+       SYS8A,  /* 24bpp, 8:8:8 */
+       SYS8B,  /* 18bpp, 8:8:2 */
+       SYS8C,  /* 18bpp, 2:8:8 */
+       SYS8D,  /* 16bpp, 8:8 */
+       SYS9,   /* 18bpp, 9:9 */
+       SYS12,  /* 24bpp, 12:12 */
+       SYS16A, /* 16bpp */
+       SYS16B, /* 18bpp, 16:2 */
+       SYS16C, /* 18bpp, 2:16 */
+       SYS18,  /* 18bpp */
+       SYS24,  /* 24bpp */
+};
 
 enum { LCDC_CHAN_DISABLED = 0,
        LCDC_CHAN_MAINLCD,
@@ -52,7 +55,7 @@ struct sh_mobile_lcdc_board_cfg {
                         struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
        void (*start_transfer)(void *board_data, void *sys_ops_handle,
                               struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
-       void (*display_on)(void *board_data);
+       void (*display_on)(void *board_data, struct fb_info *info);
        void (*display_off)(void *board_data);
 };