MIPS: Make various locks static.
authorRalf Baechle <ralf@linux-mips.org>
Sat, 27 Feb 2010 11:53:30 +0000 (12:53 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 27 Feb 2010 11:53:30 +0000 (12:53 +0100)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/cavium-octeon/octeon-irq.c
arch/mips/dec/kn01-berr.c
arch/mips/include/asm/dec/kn01.h
arch/mips/oprofile/op_model_loongson2.c
arch/mips/pci/ops-pmcmsp.c
arch/mips/sgi-ip27/ip27-nmi.c
arch/mips/sibyte/bcm1480/irq.c
arch/mips/sibyte/sb1250/irq.c
arch/mips/sni/rm200.c

index 0bc79dcede2601ae5abe305e6ea987df79cda8e0..5070e960addeb4571feb85878de040e42d1d92a2 100644 (file)
@@ -15,7 +15,6 @@
 
 DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
 DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
-DEFINE_SPINLOCK(octeon_irq_msi_lock);
 
 static int octeon_coreid_for_cpu(int cpu)
 {
@@ -545,6 +544,8 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
 
 #ifdef CONFIG_PCI_MSI
 
+static DEFINE_SPINLOCK(octeon_irq_msi_lock);
+
 static void octeon_irq_msi_ack(unsigned int irq)
 {
        if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
index b0dc6d53edd61fbb88283b8e4f18dae73ad5aacf..b9bdc6f8ba7ffcf524e669eeb6203916af79aaa0 100644 (file)
@@ -46,7 +46,7 @@
  * There is no default value -- it has to be initialized.
  */
 u16 cached_kn01_csr;
-DEFINE_SPINLOCK(kn01_lock);
+static DEFINE_SPINLOCK(kn01_lock);
 
 
 static inline void dec_kn01_be_ack(void)
index 28fa717ac423fb169177436027843f6058a720db..88d9ffd742588b41c99975943c7769fb75f18d25 100644 (file)
@@ -80,7 +80,6 @@
 struct pt_regs;
 
 extern u16 cached_kn01_csr;
-extern spinlock_t kn01_lock;
 
 extern void dec_kn01_be_init(void);
 extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
index c25fb9b2073e51ea21166565c00b5ab2a5e33cc1..f7f9a32c722a4f062db8908b576e53530c4fb52b 100644 (file)
@@ -47,7 +47,7 @@ static struct loongson2_register_config {
        int cnt1_enabled, cnt2_enabled;
 } reg;
 
-DEFINE_SPINLOCK(sample_lock);
+static DEFINE_SPINLOCK(sample_lock);
 
 static char *oprofid = "LoongsonPerf";
 static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
index 32548b5d68d6738ec7bf5709cf0a26f6055da3f4..04b31478a6d7d6631ad3faa684be6f41e66e2a09 100644 (file)
@@ -206,7 +206,7 @@ static void pci_proc_init(void)
 }
 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
 
-DEFINE_SPINLOCK(bpci_lock);
+static DEFINE_SPINLOCK(bpci_lock);
 
 /*****************************************************************************
  *
index 6c5a630566f93d77997839577fbc5386c5830c97..8682784abfcf3bc70902b59ab7430633cef31dd3 100644 (file)
@@ -21,7 +21,7 @@
 
 typedef unsigned long machreg_t;
 
-DEFINE_SPINLOCK(nmi_lock);
+static DEFINE_SPINLOCK(nmi_lock);
 
 /*
  * Lets see what else we need to do here. Set up sp, gp?
index 4070268aa769826c46bb3c5328f398a71abc0283..fbea5e65c7acd3e97b7401551269731e8a70fffe 100644 (file)
@@ -73,7 +73,7 @@ static struct irq_chip bcm1480_irq_type = {
 /* Store the CPU id (not the logical number) */
 int bcm1480_irq_owner[BCM1480_NR_IRQS];
 
-DEFINE_SPINLOCK(bcm1480_imr_lock);
+static DEFINE_SPINLOCK(bcm1480_imr_lock);
 
 void bcm1480_mask_irq(int cpu, int irq)
 {
index 5e7f2016cceb77bc543b1c0396fef16b918cadb4..5dae2ecb83ffde36f3e74eaa8fed389ea2567f9e 100644 (file)
@@ -72,7 +72,7 @@ static struct irq_chip sb1250_irq_type = {
 /* Store the CPU id (not the logical number) */
 int sb1250_irq_owner[SB1250_NR_IRQS];
 
-DEFINE_SPINLOCK(sb1250_imr_lock);
+static DEFINE_SPINLOCK(sb1250_imr_lock);
 
 void sb1250_mask_irq(int cpu, int irq)
 {
index 31e2583ec622a0b4c48c23da98905e5a35b4ad80..c4778e47efa465cfc976a899dc7f40a5569074c6 100644 (file)
@@ -132,7 +132,7 @@ device_initcall(snirm_setup_devinit);
  * readb/writeb to access them
  */
 
-DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
+static DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
 #define PIC_CMD    0x00
 #define PIC_IMR    0x01
 #define PIC_ISR    PIC_CMD