net: systemport: Correctly set TSB endian for host
authorFlorian Fainelli <f.fainelli@gmail.com>
Sat, 2 Sep 2017 00:32:34 +0000 (17:32 -0700)
committerDavid S. Miller <davem@davemloft.net>
Sat, 2 Sep 2017 03:19:32 +0000 (20:19 -0700)
Similarly to how we configure the RSB (Receive Status Block) we also
need to set the TSB (Transmit Status Block) based on the host endian.
This was missing from the commit indicated below.

Fixes: 389a06bc534e ("net: systemport: Set correct RSB endian bits based on host")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/broadcom/bcmsysport.c
drivers/net/ethernet/broadcom/bcmsysport.h

index eec77fae12a14c5c1c1f1136dd3f286968f57069..a6572b51435aef4fd630a3868b546a35b7e500cf 100644 (file)
@@ -1392,6 +1392,19 @@ static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
        tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index));
        tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
 
+       /* Do not use tdma_control_bit() here because TSB_SWAP1 collides
+        * with the original definition of ACB_ALGO
+        */
+       reg = tdma_readl(priv, TDMA_CONTROL);
+       if (priv->is_lite)
+               reg &= ~BIT(TSB_SWAP1);
+       /* Set a correct TSB format based on host endian */
+       if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+               reg |= tdma_control_bit(priv, TSB_SWAP0);
+       else
+               reg &= ~tdma_control_bit(priv, TSB_SWAP0);
+       tdma_writel(priv, reg, TDMA_CONTROL);
+
        /* Program the number of descriptors as MAX_THRESHOLD and half of
         * its size for the hysteresis trigger
         */
index 80b4ffff63b7d4373d83af28d974a821c9b5b155..82e401df199e44f8028bcd2aebd8952961941a79 100644 (file)
@@ -449,7 +449,8 @@ struct bcm_rsb {
 /* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we
  * keep the SYSTEMPORT layout here and adjust with tdma_control_bit()
  */
-#define  TSB_SWAP                      2
+#define  TSB_SWAP0                     2
+#define  TSB_SWAP1                     3
 #define  ACB_ALGO                      3
 #define  BUF_DATA_OFFSET_SHIFT         4
 #define  BUF_DATA_OFFSET_MASK          0x3ff