u8 cs_polarity;
};
----- static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
+++++ static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
bool active)
{
u32 reg;
static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
struct spi_device *spi, int hz)
{
----- unsigned profile = spi->chip_select;
+++++ unsigned int profile = spi->chip_select;
u32 reg;
reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
{
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
----- unsigned chip_select = spi->chip_select;
+++++ unsigned int chip_select = spi->chip_select;
u16 opcode = 0;
int pending = t->len;
int step_size = HSSPI_BUFFER_LEN;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
---- - dev_err(dev, "no irq\n");
---- - return -ENXIO;
++++ + dev_err(dev, "no irq: %d\n", irq);
++++ + return irq;
}
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);