Merge tag 'davinci-fixes-for-v4.13' of git://git.kernel.org/pub/scm/linux/kernel...
authorArnd Bergmann <arnd@arndb.de>
Fri, 4 Aug 2017 11:22:33 +0000 (13:22 +0200)
committerArnd Bergmann <arnd@arndb.de>
Fri, 4 Aug 2017 11:22:33 +0000 (13:22 +0200)
Pull "DaVinci fixes for v4.13" from Sekhar Nori:

Drop unused VPIF endpoints from device-tree.
They should be used only when an actual
remote-endpoint is connected.

* tag 'davinci-fixes-for-v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: dts: da850-lcdk: drop unused VPIF endpoints
  ARM: dts: da850-evm: drop unused VPIF endpoints

44 files changed:
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
arch/arm/Kconfig
arch/arm/boot/dts/armada-388-gp.dts
arch/arm/boot/dts/dm8168-evm.dts
arch/arm/boot/dts/dm816x.dtsi
arch/arm/boot/dts/dra71-evm.dts
arch/arm/boot/dts/exynos4.dtsi
arch/arm/boot/dts/rk3288.dtsi
arch/arm/boot/dts/sun8i-a83t.dtsi
arch/arm/boot/dts/sunxi-h3-h5.dtsi
arch/arm/boot/dts/tango4-vantage-1172.dts
arch/arm/mach-davinci/board-da850-evm.c
arch/arm/mach-davinci/clock.c
arch/arm/mach-ep93xx/clock.c
arch/arm/mach-ixp4xx/include/mach/io.h
arch/arm/mach-mmp/devices.c
arch/arm/mach-mvebu/platsmp.c
arch/arm/mach-omap1/board-ams-delta.c
arch/arm/mach-omap1/board-osk.c
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/io.c
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-omap2/prm3xxx.c
arch/arm/mach-omap2/prm44xx.c
arch/arm/mach-prima2/common.c
arch/arm/mach-pxa/Kconfig
arch/arm/mach-pxa/include/mach/mtd-xip.h
arch/arm/mach-rpc/include/mach/hardware.h
arch/arm/mach-sa1100/clock.c
arch/arm/mach-sa1100/include/mach/mtd-xip.h
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
arch/arm/mach-w90x900/clock.c
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
arch/arm64/boot/dts/renesas/salvator-common.dtsi
arch/arm64/boot/dts/renesas/ulcb.dtsi
arch/arm64/configs/defconfig
drivers/bus/uniphier-system-bus.c
drivers/soc/zte/Kconfig

index d3b6e1a4713a58d00692ab8bf2ae74f1956a40e3..5aa5926029ee7286c4cd2e41a446574c13102021 100644 (file)
@@ -40,7 +40,7 @@ Optional properties:
 Example for a Mali-T760:
 
 gpu@ffa30000 {
-       compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
+       compatible = "rockchip,rk3288-mali", "arm,mali-t760";
        reg = <0xffa30000 0x10000>;
        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
index a208bfe367b55574e2ca4a901de8b3a2862aee2e..61a0cb15067ea653eaa9631fe64276385e3de064 100644 (file)
@@ -380,7 +380,7 @@ config ARCH_EP93XX
        bool "EP93xx-based"
        select ARCH_HAS_HOLES_MEMORYMODEL
        select ARM_AMBA
-       select ARM_PATCH_PHYS_VIRT
+       imply ARM_PATCH_PHYS_VIRT
        select ARM_VIC
        select AUTO_ZRELADDR
        select CLKDEV_LOOKUP
index 895fa6cfa15a9ee1c56c5827f5f5fe2f8e512196..563901e0ec071f0c66a4590b17fe5c3f6cfcbd69 100644 (file)
@@ -75,7 +75,7 @@
                                        pinctrl-names = "default";
                                        pinctrl-0 = <&pca0_pins>;
                                        interrupt-parent = <&gpio0>;
-                                       interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                                       interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        interrupt-controller;
@@ -87,7 +87,7 @@
                                        compatible = "nxp,pca9555";
                                        pinctrl-names = "default";
                                        interrupt-parent = <&gpio0>;
-                                       interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+                                       interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
                                        gpio-controller;
                                        #gpio-cells = <2>;
                                        interrupt-controller;
index 1865976db5f9a3e11aad03cdd951d2f3af83c78d..c72a2132aa823b053c5ab9450a92faf266c85878 100644 (file)
                        DM816X_IOPAD(0x0d08, MUX_MODE0)                 /* USB1_DRVVBUS */
                >;
        };
+
+       nandflash_pins: nandflash_pins {
+               pinctrl-single,pins = <
+                       DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0)               /* PINCTRL207 GPMC_CS0*/
+                       DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0)              /* PINCTRL217 GPMC_ADV_ALE */
+                       DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0)    /* PINCTRL214 GPMC_OE_RE */
+                       DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0)              /* PINCTRL215 GPMC_BE0_CLE */
+                       DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0)               /* PINCTRL213 GPMC_WE */
+                       DM816X_IOPAD(0x0b6c, MUX_MODE0)                         /* PINCTRL220 GPMC_WAIT */
+                       DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0)              /* PINCTRL250 GPMC_CLK */
+                       DM816X_IOPAD(0x0ba4, MUX_MODE0)                         /* PINCTRL234 GPMC_D0 */
+                       DM816X_IOPAD(0x0ba8, MUX_MODE0)                         /* PINCTRL234 GPMC_D1 */
+                       DM816X_IOPAD(0x0bac, MUX_MODE0)                         /* PINCTRL234 GPMC_D2 */
+                       DM816X_IOPAD(0x0bb0, MUX_MODE0)                         /* PINCTRL234 GPMC_D3 */
+                       DM816X_IOPAD(0x0bb4, MUX_MODE0)                         /* PINCTRL234 GPMC_D4 */
+                       DM816X_IOPAD(0x0bb8, MUX_MODE0)                         /* PINCTRL234 GPMC_D5 */
+                       DM816X_IOPAD(0x0bbc, MUX_MODE0)                         /* PINCTRL234 GPMC_D6 */
+                       DM816X_IOPAD(0x0bc0, MUX_MODE0)                         /* PINCTRL234 GPMC_D7 */
+                       DM816X_IOPAD(0x0bc4, MUX_MODE0)                         /* PINCTRL234 GPMC_D8 */
+                       DM816X_IOPAD(0x0bc8, MUX_MODE0)                         /* PINCTRL234 GPMC_D9 */
+                       DM816X_IOPAD(0x0bcc, MUX_MODE0)                         /* PINCTRL234 GPMC_D10 */
+                       DM816X_IOPAD(0x0bd0, MUX_MODE0)                         /* PINCTRL234 GPMC_D11 */
+                       DM816X_IOPAD(0x0bd4, MUX_MODE0)                         /* PINCTRL234 GPMC_D12 */
+                       DM816X_IOPAD(0x0bd8, MUX_MODE0)                         /* PINCTRL234 GPMC_D13 */
+                       DM816X_IOPAD(0x0bdc, MUX_MODE0)                         /* PINCTRL234 GPMC_D14 */
+                       DM816X_IOPAD(0x0be0, MUX_MODE0)                         /* PINCTRL234 GPMC_D15 */
+               >;
+       };
 };
 
 &i2c1 {
 
 &gpmc {
        ranges = <0 0 0x04000000 0x01000000>;   /* CS0: 16MB for NAND */
+       pinctrl-names = "default";
+       pinctrl-0 = <&nandflash_pins>;
 
        nand@0,0 {
                compatible = "ti,omap2-nand";
                interrupt-parent = <&gpmc>;
                interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                             <1 IRQ_TYPE_NONE>; /* termcount */
+               rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                #address-cells = <1>;
                #size-cells = <1>;
                ti,nand-ecc-opt = "bch8";
+               ti,elm-id = <&elm>;
                nand-bus-width = <16>;
                gpmc,device-width = <2>;
                gpmc,sync-clk-ps = <0>;
        vmmc-supply = <&vmmcsd_fixed>;
        bus-width = <4>;
        cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
-       wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 };
 
 /* At least dm8168-evm rev c won't support multipoint, later may */
index 59cbf958fcc3178c4b56aad647c340e40a63c098..566b2a8c8b96853da331571c233dc786d8adc187 100644 (file)
                };
 
                elm: elm@48080000 {
-                       compatible = "ti,816-elm";
+                       compatible = "ti,am3352-elm";
                        ti,hwmods = "elm";
                        reg = <0x48080000 0x2000>;
                        interrupts = <4>;
index 4d57a55473afd1f563667d948b49269e11028697..a6298eb56978710c24291fc05d17770fefccd188 100644 (file)
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-               ti,impedance-control = <0x1f>;
+               ti,min-output-impedance;
        };
 
        dp83867_1: ethernet-phy@3 {
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
                ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
-               ti,impedance-control = <0x1f>;
+               ti,min-output-impedance;
        };
 };
 
index 497a9470c8881bca6e49800f90c0f5d20dd3d84a..5739389f5bb877ef7b29455a1bcd47328d7223ed 100644 (file)
@@ -59,6 +59,9 @@
                compatible = "samsung,exynos4210-audss-clock";
                reg = <0x03810000 0x0C>;
                #clock-cells = <1>;
+               clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                        <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
+               clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
        };
 
        i2s0: i2s@03830000 {
index 2484f11761ea24f3bfa44a81e7309442399367d9..858e1fed762a1df80f33bac4576b5d900e021bcf 100644 (file)
                };
        };
 
-       gpu: mali@ffa30000 {
-               compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
+       gpu: gpu@ffa30000 {
+               compatible = "rockchip,rk3288-mali", "arm,mali-t760";
                reg = <0xffa30000 0x10000>;
                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
index 8923ba625b76f156f27fde9c66f1f72ad044405a..19a8f4fcfab50ef5300360d980f1738d99345a94 100644 (file)
@@ -44,7 +44,9 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
 #include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-a83t-ccu.h>
 
 / {
        interrupt-parent = <&gic>;
                        compatible = "allwinner,sun8i-a83t-dma";
                        reg = <0x01c02000 0x1000>;
                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 21>;
-                       resets = <&ccu 7>;
+                       clocks = <&ccu CLK_BUS_DMA>;
+                       resets = <&ccu RST_BUS_DMA>;
                        #dma-cells = <1>;
                };
 
                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                        reg = <0x01c20800 0x400>;
-                       clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+                       clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
                        clock-names = "apb", "hosc", "losc";
                        gpio-controller;
                        interrupt-controller;
                                     "allwinner,sun8i-h3-spdif";
                        reg = <0x01c21000 0x400>;
                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu 44>, <&ccu 76>;
-                       resets = <&ccu 32>;
+                       clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+                       resets = <&ccu RST_BUS_SPDIF>;
                        clock-names = "apb", "spdif";
                        dmas = <&dma 2>;
                        dma-names = "tx";
                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
-                       clocks = <&ccu 53>;
-                       resets = <&ccu 40>;
+                       clocks = <&ccu CLK_BUS_UART0>;
+                       resets = <&ccu RST_BUS_UART0>;
                        status = "disabled";
                };
 
index 6f2162608006770896df2adcc258a4ed2a3b63a9..d38282b9e5d442cbf1709e38f8a64ee9bfacce1c 100644 (file)
                emac: ethernet@1c30000 {
                        compatible = "allwinner,sun8i-h3-emac";
                        syscon = <&syscon>;
-                       reg = <0x01c30000 0x104>;
+                       reg = <0x01c30000 0x10000>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
                        resets = <&ccu RST_BUS_EMAC>;
index 86d8df98802fdf66a651adb04de5c4be49af3fcc..13bcc460bcb2adf2ab17775bc0aa2c01bc694aed 100644 (file)
@@ -22,7 +22,7 @@
 };
 
 &eth0 {
-       phy-connection-type = "rgmii";
+       phy-connection-type = "rgmii-id";
        phy-handle = <&eth0_phy>;
        #address-cells = <1>;
        #size-cells = <0>;
index b5625d0092881bbbbb1022de2664c51f2a304844..e568c8c6f69cb67bf423db51f25d6315a15fbc96 100644 (file)
@@ -1166,7 +1166,7 @@ static struct tvp514x_platform_data tvp5146_pdata = {
 
 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
 
-static const struct vpif_input da850_ch0_inputs[] = {
+static struct vpif_input da850_ch0_inputs[] = {
        {
                .input = {
                        .index = 0,
@@ -1181,7 +1181,7 @@ static const struct vpif_input da850_ch0_inputs[] = {
        },
 };
 
-static const struct vpif_input da850_ch1_inputs[] = {
+static struct vpif_input da850_ch1_inputs[] = {
        {
                .input = {
                        .index = 0,
index f5dce9b4e617df833cd210bac2fe65ac4a93b788..f77a4f7660505fe949af782e50b99c08b12a5570 100644 (file)
@@ -218,6 +218,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 }
 EXPORT_SYMBOL(clk_set_parent);
 
+struct clk *clk_get_parent(struct clk *clk)
+{
+       if (!clk)
+               return NULL;
+
+       return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
 int clk_register(struct clk *clk)
 {
        if (clk == NULL || IS_ERR(clk))
index 39ef3b613912f8888013c30d591e4ad4f0cd8095..beec5f16443a29fb5a62f6deb8969ea33cff5b6d 100644 (file)
@@ -475,6 +475,26 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL(clk_set_rate);
 
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+       return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
 
 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
index 7a0c13bf42694b724e0fcb35439070eefde0a646..844e8ac593e270125980df3ecced92b6d6322f5e 100644 (file)
@@ -95,8 +95,10 @@ static inline void __indirect_writeb(u8 value, volatile void __iomem *p)
 }
 
 static inline void __indirect_writesb(volatile void __iomem *bus_addr,
-                                     const u8 *vaddr, int count)
+                                     const void *p, int count)
 {
+       const u8 *vaddr = p;
+
        while (count--)
                writeb(*vaddr++, bus_addr);
 }
@@ -118,8 +120,10 @@ static inline void __indirect_writew(u16 value, volatile void __iomem *p)
 }
 
 static inline void __indirect_writesw(volatile void __iomem *bus_addr,
-                                     const u16 *vaddr, int count)
+                                     const void *p, int count)
 {
+       const u16 *vaddr = p;
+
        while (count--)
                writew(*vaddr++, bus_addr);
 }
@@ -137,8 +141,9 @@ static inline void __indirect_writel(u32 value, volatile void __iomem *p)
 }
 
 static inline void __indirect_writesl(volatile void __iomem *bus_addr,
-                                     const u32 *vaddr, int count)
+                                     const void *p, int count)
 {
+       const u32 *vaddr = p;
        while (count--)
                writel(*vaddr++, bus_addr);
 }
@@ -160,8 +165,10 @@ static inline u8 __indirect_readb(const volatile void __iomem *p)
 }
 
 static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
-                                    u8 *vaddr, u32 count)
+                                    void *p, u32 count)
 {
+       u8 *vaddr = p;
+
        while (count--)
                *vaddr++ = readb(bus_addr);
 }
@@ -183,8 +190,10 @@ static inline u16 __indirect_readw(const volatile void __iomem *p)
 }
 
 static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
-                                    u16 *vaddr, u32 count)
+                                    void *p, u32 count)
 {
+       u16 *vaddr = p;
+
        while (count--)
                *vaddr++ = readw(bus_addr);
 }
@@ -204,8 +213,10 @@ static inline u32 __indirect_readl(const volatile void __iomem *p)
 }
 
 static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
-                                    u32 *vaddr, u32 count)
+                                    void *p, u32 count)
 {
+       u32 *vaddr = p;
+
        while (count--)
                *vaddr++ = readl(bus_addr);
 }
@@ -523,8 +534,15 @@ static inline void iowrite32_rep(void __iomem *addr, const void *vaddr,
 #endif
 }
 
-#define        ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
-#define        ioport_unmap(addr)
+#define ioport_map(port, nr) ioport_map(port, nr)
+static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+       return ((void __iomem*)((port) + PIO_OFFSET));
+}
+#define        ioport_unmap(addr) ioport_unmap(addr)
+static inline void ioport_unmap(void __iomem *addr)
+{
+}
 #endif /* CONFIG_PCI */
 
 #endif /* __ASM_ARM_ARCH_IO_H */
index 3330ac7cfbefc78388b78ad06a47ab102a9d9a79..671c7a09ab3d65a43b1effae5fd3bffbcb9c22cb 100644 (file)
@@ -238,7 +238,7 @@ void pxa_usb_phy_deinit(void __iomem *phy_reg)
 #endif
 
 #if IS_ENABLED(CONFIG_USB_SUPPORT)
-static u64 usb_dma_mask = ~(u32)0;
+static u64 __maybe_unused usb_dma_mask = ~(u32)0;
 
 #if IS_ENABLED(CONFIG_USB_MV_UDC)
 struct resource pxa168_u2o_resources[] = {
index e62273aacb43681f2bd8ab0c7e95d82d2c32020f..4ffbbd217e8286e18181fac98487a8860ead6372 100644 (file)
@@ -211,7 +211,7 @@ static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
                return PTR_ERR(base);
 
        writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
-       writel(virt_to_phys(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
+       writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
 
        iounmap(base);
 
index 6613a6ff5dbc9e35512ac94fd84904ddf2a63ee1..6cbc69c92913dbc4074a65e269bb5243e9193cdb 100644 (file)
@@ -510,6 +510,7 @@ static void __init ams_delta_init(void)
 static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
 {
        struct modem_private_data *priv = port->private_data;
+       int ret;
 
        if (IS_ERR(priv->regulator))
                return;
@@ -518,9 +519,16 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
                return;
 
        if (state == 0)
-               regulator_enable(priv->regulator);
+               ret = regulator_enable(priv->regulator);
        else if (old == 0)
-               regulator_disable(priv->regulator);
+               ret = regulator_disable(priv->regulator);
+       else
+               ret = 0;
+
+       if (ret)
+               dev_warn(port->dev,
+                        "ams_delta modem_pm: failed to %sable regulator: %d\n",
+                        state ? "dis" : "en", ret);
 }
 
 static struct plat_serial8250_port ams_delta_modem_ports[] = {
index 4dfb995048103b8bff965b6119f3665e54887a40..95ac1929aede4d3f82cabcf627ccf548d369b6c6 100644 (file)
@@ -441,13 +441,11 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
        .chip_select            = 0,
 } };
 
-#ifdef CONFIG_PM
 static irqreturn_t
 osk_mistral_wake_interrupt(int irq, void *ignored)
 {
        return IRQ_HANDLED;
 }
-#endif
 
 static void __init osk_mistral_init(void)
 {
@@ -515,7 +513,6 @@ static void __init osk_mistral_init(void)
 
                gpio_direction_input(OMAP_MPUIO(2));
                irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
-#ifdef CONFIG_PM
                /* share the IRQ in case someone wants to use the
                 * button for more than wakeup from system sleep.
                 */
@@ -529,7 +526,6 @@ static void __init osk_mistral_init(void)
                                ret);
                } else
                        enable_irq_wake(irq);
-#endif
        } else
                printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");
 
index dc9e34e670a26f280bdfe7947fa8709ee750465f..b1e661bb5521e4281a487c25cbfea12c0b29f91f 100644 (file)
@@ -28,7 +28,7 @@ static const struct of_device_id omap_dt_match_table[] __initconst = {
        { }
 };
 
-static void __init omap_generic_init(void)
+static void __init __maybe_unused omap_generic_init(void)
 {
        pdata_quirks_init(omap_dt_match_table);
 
index 1d739d1a0a657aec9ee73450154ff5b5197f8939..1cd20e4d56b06fe2afb4ce7d79bc310446e07762 100644 (file)
@@ -410,7 +410,7 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
        return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 }
 
-static void __init omap_hwmod_init_postsetup(void)
+static void __init __maybe_unused omap_hwmod_init_postsetup(void)
 {
        u8 postsetup_state;
 
index d44e0e2f11063134e9dd031c0a55b523dd76befa..841ba19d64a69b153a38ef594220d1a4054d7e59 100644 (file)
@@ -486,7 +486,6 @@ int __init omap3_pm_init(void)
        ret = request_irq(omap_prcm_event_to_irq("io"),
                _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
                omap3_pm_init);
-       enable_irq(omap_prcm_event_to_irq("io"));
 
        if (ret) {
                pr_err("pm: Failed to request pm_io irq\n");
index 382e236fbfd9a188a91aba9e731436dfca86dd02..64f6451499a795de85fd451903de1d9aef59ba7a 100644 (file)
@@ -692,7 +692,6 @@ static int omap3xxx_prm_late_init(void)
 {
        struct device_node *np;
        int irq_num;
-       int ret;
 
        if (!(prm_features & PRM_HAS_IO_WAKEUP))
                return 0;
@@ -712,12 +711,8 @@ static int omap3xxx_prm_late_init(void)
        }
 
        omap3xxx_prm_enable_io_wakeup();
-       ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
-       if (!ret)
-               irq_set_status_flags(omap_prcm_event_to_irq("io"),
-                                    IRQ_NOAUTOEN);
 
-       return ret;
+       return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
 }
 
 static void __exit omap3xxx_prm_exit(void)
index 87e86a4a9eadd7f6a544fb04e228a791268e6d73..3ab5df1ce900b26f91b8b582a36188bd281c6c3c 100644 (file)
@@ -336,6 +336,27 @@ static void omap44xx_prm_reconfigure_io_chain(void)
        return;
 }
 
+/**
+ * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O wakeups
+ * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
+ * omap44xx_prm_reconfigure_io_chain() must be called.  No return value.
+ */
+static void __init omap44xx_prm_enable_io_wakeup(void)
+{
+       s32 inst = omap4_prmst_get_prm_dev_inst();
+
+       if (inst == PRM_INSTANCE_UNKNOWN)
+               return;
+
+       omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+                                   OMAP4430_GLOBAL_WUEN_MASK,
+                                   inst,
+                                   omap4_prcm_irq_setup.pm_ctrl);
+}
+
 /**
  * omap44xx_prm_read_reset_sources - return the last SoC reset source
  *
@@ -668,6 +689,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
        .pwrdm_has_voltdm       = omap4_check_vcvp,
 };
 
+static int omap44xx_prm_late_init(void);
+
 /*
  * XXX document
  */
@@ -675,6 +698,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
        .read_reset_sources = &omap44xx_prm_read_reset_sources,
        .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
        .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
+       .late_init = &omap44xx_prm_late_init,
        .assert_hardreset       = omap4_prminst_assert_hardreset,
        .deassert_hardreset     = omap4_prminst_deassert_hardreset,
        .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
@@ -711,6 +735,37 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
        return prm_register(&omap44xx_prm_ll_data);
 }
 
+static int omap44xx_prm_late_init(void)
+{
+       int irq_num;
+
+       if (!(prm_features & PRM_HAS_IO_WAKEUP))
+               return 0;
+
+       irq_num = of_irq_get(prm_init_data->np, 0);
+       /*
+        * Already have OMAP4 IRQ num. For all other platforms, we need
+        * IRQ numbers from DT
+        */
+       if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
+               if (irq_num == -EPROBE_DEFER)
+                       return irq_num;
+
+               /* Have nothing to do */
+               return 0;
+       }
+
+       /* Once OMAP4 DT is filled as well */
+       if (irq_num >= 0) {
+               omap4_prcm_irq_setup.irq = irq_num;
+               omap4_prcm_irq_setup.xlate_irq = NULL;
+       }
+
+       omap44xx_prm_enable_io_wakeup();
+
+       return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+}
+
 static void __exit omap44xx_prm_exit(void)
 {
        prm_unregister(&omap44xx_prm_ll_data);
index 8cadb302a7d2f54a3bbcddaf7296606293d69e4e..ffe05c27087e88340c40f3a302f87aae19e1d81e 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/of_platform.h>
 #include "common.h"
 
-static void __init sirfsoc_init_late(void)
+static void __init __maybe_unused sirfsoc_init_late(void)
 {
        sirfsoc_pm_init();
 }
index 76fbc115ec33f7bc620e462a01f80fd915e864c1..ce7d97babb0f9428803df53cae836e437ed08118 100644 (file)
@@ -566,6 +566,7 @@ config MACH_ICONTROL
 config ARCH_PXA_ESERIES
        bool "PXA based Toshiba e-series PDAs"
        select FB_W100
+       select FB
        select PXA25x
 
 config MACH_E330
index 990d2bf2fb45e6451226afe25a4699a14ff5f53a..9bf4ea6a6f7446b830a6bfadf5156ff9cf5aed0c 100644 (file)
 
 #include <mach/regs-ost.h>
 
-#define xip_irqpending()       (ICIP & ICMR)
+/* restored July 2017, this did not build since 2011! */
+
+#define ICIP                   io_p2v(0x40d00000)
+#define ICMR                   io_p2v(0x40d00004)
+#define xip_irqpending()       (readl(ICIP) & readl(ICMR))
 
 /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime()         (OSCR)
-#define xip_elapsed_since(x)   (signed)((OSCR - (x)) / 4)
+#define xip_currtime()         readl(OSCR)
+#define xip_elapsed_since(x)   (signed)((readl(OSCR) - (x)) / 4)
 
 /*
  * xip_cpu_idle() is used when waiting for a delay equal or larger than
index aa79fa47373ac8d3e605592cbe40e574cc9b3966..622d4e5df0293b48c697bb355a52a11613e7a629 100644 (file)
@@ -25,8 +25,8 @@
  *  *_SIZE  is the size of the region
  *  *_BASE  is the virtual address
  */
-#define RAM_SIZE               0x10000000
-#define RAM_START              0x10000000
+#define RPC_RAM_SIZE           0x10000000
+#define RPC_RAM_START          0x10000000
 
 #define EASI_SIZE              0x08000000      /* EASI I/O */
 #define EASI_START             0x08000000
index 0db46895c82a4729d40b6c94c62482cd00ae1c9b..7d52cd97d96e4091adbcff105f9a0dc8db86c83e 100644 (file)
@@ -35,6 +35,31 @@ struct clk clk_##_name = {                           \
 
 static DEFINE_SPINLOCK(clocks_lock);
 
+/* Dummy clk routine to build generic kernel parts that may be using them */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       return clk_get_rate(clk);
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+       return NULL;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
 static void clk_gpio27_enable(struct clk *clk)
 {
        /*
index b3d684098fbf545c033e56793935cee7da3e2bf0..cb76096a2e36b4ea4ccf02f983244a97919ff243 100644 (file)
@@ -20,7 +20,7 @@
 #define xip_irqpending()       (ICIP & ICMR)
 
 /* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
-#define xip_currtime()         (OSCR)
-#define xip_elapsed_since(x)   (signed)((OSCR - (x)) / 4)
+#define xip_currtime()         readl_relaxed(OSCR)
+#define xip_elapsed_since(x)   (signed)((readl_relaxed(OSCR) - (x)) / 4)
 
 #endif /* __ARCH_SA1100_MTD_XIP_H__ */
index 73e3adbc133096eca9cdf652d37ff110f5e35850..44438f344dc80f9c5073502fbe2019270d8df24a 100644 (file)
@@ -67,8 +67,12 @@ static int regulator_quirk_notify(struct notifier_block *nb,
 {
        struct device *dev = data;
        struct i2c_client *client;
+       static bool done;
        u32 mon;
 
+       if (done)
+               return 0;
+
        mon = ioread32(irqc + IRQC_MONITOR);
        dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
        if (mon & REGULATOR_IRQ_MASK)
@@ -99,7 +103,7 @@ static int regulator_quirk_notify(struct notifier_block *nb,
 remove:
        dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
 
-       bus_unregister_notifier(&i2c_bus_type, nb);
+       done = true;
        iounmap(irqc);
        return 0;
 }
index ac6fd1a2cb59fb43897d00581d18e53aa354ca80..3f93fac98d973dc9a952d40a98f33b9343545e8e 100644 (file)
@@ -93,3 +93,32 @@ void nuc900_subclk_enable(struct clk *clk, int enable)
 
        __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
 }
+
+/* dummy functions, should not be called */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       WARN_ON(clk);
+       return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+       WARN_ON(clk);
+       return NULL;
+}
+EXPORT_SYMBOL(clk_get_parent);
index 9d00622ce8453820441e9c3c26980cab35c3dcd8..bd0f33b77f5728781f558414eebf1eb02055a78d 100644 (file)
                emac: ethernet@1c30000 {
                        compatible = "allwinner,sun50i-a64-emac";
                        syscon = <&syscon>;
-                       reg = <0x01c30000 0x100>;
+                       reg = <0x01c30000 0x10000>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "macirq";
                        resets = <&ccu RST_BUS_EMAC>;
index 35b8c88c3220c84c76ce1b22c8440ad8fdcbaa10..738ed689ff692b0f16b9add648f9f32dd514d010 100644 (file)
                        };
 
                        pwm_AO_ab: pwm@550 {
-                               compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
+                               compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
                                reg = <0x0 0x00550 0x0 0x10>;
                                #pwm-cells = <3>;
                                status = "disabled";
index 72c5a9f64ca8499fe83a11bdbb17c1c95c4206c6..94567eb178759c18162c276baa4ba481f903c064 100644 (file)
        status = "okay";
        pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
        pinctrl-names = "default";
-       clocks = <&clkc CLKID_FCLK_DIV4>;
-       clock-names = "clkin0";
+       clocks = <&xtal> , <&xtal>;
+       clock-names = "clkin0", "clkin1" ;
 };
 
 &pwm_ef {
index 890821d6e52b2d01a00e06d03ded2b49e091857a..266fbcf3e47f5640b565c09fae289003b7b9e679 100644 (file)
 
 #include <dt-bindings/input/input.h>
 
-#include "meson-gxl-s905x-p212.dtsi"
+#include "meson-gxl-s905x.dtsi"
 
 / {
        compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
        model = "Libre Technology CC";
 
+       aliases {
+               serial0 = &uart_AO;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
        cvbs-connector {
                compatible = "composite-video-connector";
 
                };
        };
 
+       emmc_pwrseq: emmc-pwrseq {
+               compatible = "mmc-pwrseq-emmc";
+               reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+       };
+
        hdmi-connector {
                compatible = "hdmi-connector";
                type = "a";
                        linux,default-trigger = "heartbeat";
                };
        };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+
+       vcc_3v3: regulator-vcc_3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "VCC_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       vcc_card: regulator-vcc-card {
+               compatible = "regulator-gpio";
+
+               regulator-name = "VCC_CARD";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+               gpios-states = <0>;
+
+               states = <3300000 0>,
+                        <1800000 1>;
+       };
+
+       vddio_boot: regulator-vddio_boot {
+               compatible = "regulator-fixed";
+               regulator-name = "VDDIO_BOOT";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
 };
 
 &cvbs_vdac_port {
        };
 };
 
+&ethmac {
+       status = "okay";
+};
+
+&ir {
+       status = "okay";
+       pinctrl-0 = <&remote_input_ao_pins>;
+       pinctrl-names = "default";
+};
+
 &hdmi_tx {
        status = "okay";
        pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
        };
 };
 
-/*
- * The following devices exists but are exposed on the general
- * purpose GPIO header. End user may well decide to use those pins
- * for another purpose
- */
+/* SD card */
+&sd_emmc_b {
+       status = "okay";
+       pinctrl-0 = <&sdcard_pins>;
+       pinctrl-names = "default";
+
+       bus-width = <4>;
+       cap-sd-highspeed;
+       max-frequency = <100000000>;
+       disable-wp;
+
+       cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+       cd-inverted;
 
-&sd_emmc_a {
-       status = "disabled";
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vcc_card>;
 };
 
-&uart_A {
-       status = "disabled";
+/* eMMC */
+&sd_emmc_c {
+       status = "okay";
+       pinctrl-0 = <&emmc_pins>;
+       pinctrl-names = "default";
+
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       max-frequency = <50000000>;
+       non-removable;
+       disable-wp;
+
+       mmc-pwrseq = <&emmc_pwrseq>;
+       vmmc-supply = <&vcc_3v3>;
+       vqmmc-supply = <&vddio_boot>;
 };
 
-&wifi32k {
-       status = "disabled";
+&uart_AO {
+       status = "okay";
+       pinctrl-0 = <&uart_ao_a_pins>;
+       pinctrl-names = "default";
 };
index dbcc3d4e2ed523e72bc8cd68dbf2c52503b7332f..51763d674050cb27c32b0909c62a62724d5d429d 100644 (file)
                                reg = <0x18800 0x100>, <0x18C00 0x20>;
                                gpiosb: gpio {
                                        #gpio-cells = <2>;
-                                       gpio-ranges = <&pinctrl_sb 0 0 29>;
+                                       gpio-ranges = <&pinctrl_sb 0 0 30>;
                                        gpio-controller;
                                        interrupts =
                                        <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
index 726528ce54e9650fe2b0ebfc085b0f0753e876d8..4c68605675a83db1639c0efed23788379c4d9e17 100644 (file)
                                interrupt-names = "mem", "ring0", "ring1",
                                "ring2", "ring3", "eip";
                                clocks = <&cpm_clk 1 26>;
+                               dma-coherent;
                        };
                };
 
index 95f8e5f607f608d2ec1bd258e1eec76f0d4b8528..923f354b02f00d199db276f60adffb013d688186 100644 (file)
@@ -64,7 +64,7 @@
                                compatible = "marvell,armada-8k-rtc";
                                reg = <0x284000 0x20>, <0x284080 0x24>;
                                reg-names = "rtc", "rtc-soc";
-                               interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
                        };
 
                        cps_ethernet: ethernet@0 {
                                interrupt-names = "mem", "ring0", "ring1",
                                                  "ring2", "ring3", "eip";
                                clocks = <&cps_clk 1 26>;
+                               dma-coherent;
                                /*
                                 * The cryptographic engine found on the cp110
                                 * master is enabled by default at the SoC
index aef35e0b685a3a8599f33d1b227f31d0e5f551ea..a451996f590a5173a3e9dbe56831a623e3c0639a 100644 (file)
 
        /* audio_clkout0/1/2/3 */
        #clock-cells = <1>;
-       clock-frequency = <11289600 12288000>;
+       clock-frequency = <12288000 11289600>;
 
        status = "okay";
 
index b5c6ee07d7f91d84d4b5b8e612fcc4f4304bc4c2..d1a3f3b7a0ab0b97aff29a898813a023a7d5bd3d 100644 (file)
 
        /* audio_clkout0/1/2/3 */
        #clock-cells = <1>;
-       clock-frequency = <11289600 12288000>;
+       clock-frequency = <12288000 11289600>;
 
        status = "okay";
 
index 6c7d147eed54de4cc19678ce8f318987406b0521..b4ca115b3be1c0a25121517e1e9e598d26c7c0b1 100644 (file)
@@ -476,6 +476,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_MSM_GCC_8916=y
 CONFIG_MSM_GCC_8994=y
 CONFIG_MSM_MMCC_8996=y
+CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_ARM_MHU=y
 CONFIG_PLATFORM_MHU=y
index 1e6e0269edcc18ed9f7c8e4cc65e6ce6595c8683..f76be6bd6eb3dfd52bac8c847f3a93e5c3f7777c 100644 (file)
@@ -256,10 +256,23 @@ static int uniphier_system_bus_probe(struct platform_device *pdev)
 
        uniphier_system_bus_set_reg(priv);
 
+       platform_set_drvdata(pdev, priv);
+
        /* Now, the bus is configured.  Populate platform_devices below it */
        return of_platform_default_populate(dev->of_node, NULL, dev);
 }
 
+static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
+{
+       uniphier_system_bus_set_reg(dev_get_drvdata(dev));
+
+       return 0;
+}
+
+static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
+       SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
+};
+
 static const struct of_device_id uniphier_system_bus_match[] = {
        { .compatible = "socionext,uniphier-system-bus" },
        { /* sentinel */ }
@@ -271,6 +284,7 @@ static struct platform_driver uniphier_system_bus_driver = {
        .driver = {
                .name   = "uniphier-system-bus",
                .of_match_table = uniphier_system_bus_match,
+               .pm = &uniphier_system_bus_pm_ops,
        },
 };
 module_platform_driver(uniphier_system_bus_driver);
index 20bde38ce2f912f547f07874b2b91789c9ee7215..e9d750c510cd9c90a5ac1bb22ddbc89e29c6024f 100644 (file)
@@ -2,6 +2,7 @@
 # ZTE SoC drivers
 #
 menuconfig SOC_ZTE
+       depends on ARCH_ZX || COMPILE_TEST
        bool "ZTE SoC driver support"
 
 if SOC_ZTE