Merge tag 'v5.3-rc3' into drm-next-5.4
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Aug 2019 18:07:28 +0000 (13:07 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Aug 2019 18:07:28 +0000 (13:07 -0500)
Linux 5.3-rc3

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
263 files changed:
MAINTAINERS
drivers/gpu/drm/amd/amdgpu/Makefile
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
drivers/gpu/drm/amd/amdgpu/arct_reg_init.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/dce_virtual.c
drivers/gpu/drm/amd/amdgpu/df_v3_6.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/nv.h
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
drivers/gpu/drm/amd/amdgpu/si.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/amdgpu/soc15.h
drivers/gpu/drm/amd/amdgpu/soc15_common.h
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/umc_v6_1.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
drivers/gpu/drm/amd/amdgpu/vi.c
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
drivers/gpu/drm/amd/amdkfd/kfd_device.c
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
drivers/gpu/drm/amd/display/dc/calcs/Makefile
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
drivers/gpu/drm/amd/display/dc/core/dc.c
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
drivers/gpu/drm/amd/display/dc/core/dc_link.c
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
drivers/gpu/drm/amd/display/dc/dc.h
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
drivers/gpu/drm/amd/display/dc/dc_link.h
drivers/gpu/drm/amd/display/dc/dc_types.h
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
drivers/gpu/drm/amd/display/dc/dcn20/Makefile
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
drivers/gpu/drm/amd/display/dc/dm_services.h
drivers/gpu/drm/amd/display/dc/dml/Makefile
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
drivers/gpu/drm/amd/display/dc/dsc/Makefile
drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
drivers/gpu/drm/amd/display/dc/gpio/Makefile
drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h [new file with mode: 0644]
drivers/gpu/drm/amd/display/dc/inc/core_status.h
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
drivers/gpu/drm/amd/display/include/audio_types.h
drivers/gpu/drm/amd/display/include/dal_asic_id.h
drivers/gpu/drm/amd/display/include/gpio_service_interface.h
drivers/gpu/drm/amd/display/include/link_service_types.h
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
drivers/gpu/drm/amd/display/modules/color/color_gamma.h
drivers/gpu/drm/amd/include/arct_ip_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/atomfirmware.h
drivers/gpu/drm/amd/include/kgd_pp_interface.h
drivers/gpu/drm/amd/include/navi12_ip_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/navi14_ip_offset.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/soc15_ih_clientid.h
drivers/gpu/drm/amd/include/v9_structs.h
drivers/gpu/drm/amd/powerplay/Makefile
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/arcturus_ppt.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/inc/smu_types.h [new file with mode: 0644]
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_drv.c
drivers/gpu/drm/ttm/ttm_bo.c
include/drm/amd_asic_type.h
include/drm/ttm/ttm_bo_driver.h
include/uapi/drm/amdgpu_drm.h

index a2c343ee3b2ca13e4cbe7257a9e4a58d69a11285..e0f9d247497362fd338ebec2958f1b646e84123f 100644 (file)
@@ -829,17 +829,11 @@ F:        drivers/iommu/amd_iommu*.[ch]
 F:     include/linux/amd-iommu.h
 
 AMD KFD
-M:     Oded Gabbay <oded.gabbay@gmail.com>
-L:     dri-devel@lists.freedesktop.org
-T:     git git://people.freedesktop.org/~gabbayo/linux.git
-S:     Supported
-F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
-F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
-F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
-F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
-F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
-F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
-F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+M:     Felix Kuehling <Felix.Kuehling@amd.com>
+L:     amd-gfx@lists.freedesktop.org
+T:     git git://people.freedesktop.org/~agd5f/linux
+S:     Supported
+F:     drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
 F:     drivers/gpu/drm/amd/amdkfd/
 F:     drivers/gpu/drm/amd/include/cik_structs.h
 F:     drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 56e084367b93896a83b94a5c7f083cd22a8f66b2..8afa0bceb4603cad09d4335c8fbe6311ed3c975f 100644 (file)
@@ -66,7 +66,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
 
 amdgpu-y += \
        vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
-       vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o
+       vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
+       arct_reg_init.o navi12_reg_init.o
 
 # add DF block
 amdgpu-y += \
@@ -77,9 +78,13 @@ amdgpu-y += \
 amdgpu-y += \
        gmc_v7_0.o \
        gmc_v8_0.o \
-       gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \
+       gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
        gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o
 
+# add UMC block
+amdgpu-y += \
+       umc_v6_1.o
+
 # add IH block
 amdgpu-y += \
        amdgpu_irq.o \
@@ -144,7 +149,8 @@ amdgpu-y += \
 amdgpu-y += \
        amdgpu_vcn.o \
        vcn_v1_0.o \
-       vcn_v2_0.o
+       vcn_v2_0.o \
+       vcn_v2_5.o
 
 # add ATHUB block
 amdgpu-y += \
@@ -162,6 +168,7 @@ amdgpu-y += \
         amdgpu_amdkfd_gpuvm.o \
         amdgpu_amdkfd_gfx_v8.o \
         amdgpu_amdkfd_gfx_v9.o \
+        amdgpu_amdkfd_arcturus.o \
         amdgpu_amdkfd_gfx_v10.o
 
 ifneq ($(CONFIG_DRM_AMDGPU_CIK),)
index 8199d201b43a477a8460f63452a5494ca403b554..f85e7174babbf1e18feccae09f0035cec7f3cfa0 100644 (file)
@@ -86,6 +86,7 @@
 #include "amdgpu_smu.h"
 #include "amdgpu_discovery.h"
 #include "amdgpu_mes.h"
+#include "amdgpu_umc.h"
 
 #define MAX_GPU_INSTANCE               16
 
@@ -532,6 +533,14 @@ struct amdgpu_allowed_register_entry {
        bool grbm_indexed;
 };
 
+enum amd_reset_method {
+       AMD_RESET_METHOD_LEGACY = 0,
+       AMD_RESET_METHOD_MODE0,
+       AMD_RESET_METHOD_MODE1,
+       AMD_RESET_METHOD_MODE2,
+       AMD_RESET_METHOD_BACO
+};
+
 /*
  * ASIC specific functions.
  */
@@ -543,6 +552,7 @@ struct amdgpu_asic_funcs {
                             u32 sh_num, u32 reg_offset, u32 *value);
        void (*set_vga_state)(struct amdgpu_device *adev, bool state);
        int (*reset)(struct amdgpu_device *adev);
+       enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
        /* get the reference clock */
        u32 (*get_xclk)(struct amdgpu_device *adev);
        /* MM block clocks */
@@ -627,6 +637,9 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 
+typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
+typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
+
 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
 
@@ -648,6 +661,12 @@ struct nbio_hdp_flush_reg {
        u32 ref_and_mask_cp9;
        u32 ref_and_mask_sdma0;
        u32 ref_and_mask_sdma1;
+       u32 ref_and_mask_sdma2;
+       u32 ref_and_mask_sdma3;
+       u32 ref_and_mask_sdma4;
+       u32 ref_and_mask_sdma5;
+       u32 ref_and_mask_sdma6;
+       u32 ref_and_mask_sdma7;
 };
 
 struct amdgpu_mmio_remap {
@@ -668,7 +687,7 @@ struct amdgpu_nbio_funcs {
        void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
                        bool use_doorbell, int doorbell_index, int doorbell_size);
        void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
-                       int doorbell_index);
+                                  int doorbell_index, int instance);
        void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
                                         bool enable);
        void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
@@ -705,6 +724,9 @@ struct amdgpu_df_funcs {
                                         int is_disable);
        void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
                                         uint64_t *count);
+       uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
+       void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
+                        uint32_t ficadl_val, uint32_t ficadh_val);
 };
 /* Define the HW IP blocks will be used in driver , add more if necessary */
 enum amd_hw_ip_block_type {
@@ -712,6 +734,12 @@ enum amd_hw_ip_block_type {
        HDP_HWIP,
        SDMA0_HWIP,
        SDMA1_HWIP,
+       SDMA2_HWIP,
+       SDMA3_HWIP,
+       SDMA4_HWIP,
+       SDMA5_HWIP,
+       SDMA6_HWIP,
+       SDMA7_HWIP,
        MMHUB_HWIP,
        ATHUB_HWIP,
        NBIO_HWIP,
@@ -728,10 +756,12 @@ enum amd_hw_ip_block_type {
        NBIF_HWIP,
        THM_HWIP,
        CLK_HWIP,
+       UMC_HWIP,
+       RSMU_HWIP,
        MAX_HWIP
 };
 
-#define HWIP_MAX_INSTANCE      6
+#define HWIP_MAX_INSTANCE      8
 
 struct amd_powerplay {
        void *pp_handle;
@@ -803,6 +833,8 @@ struct amdgpu_device {
        amdgpu_wreg_t                   pcie_wreg;
        amdgpu_rreg_t                   pciep_rreg;
        amdgpu_wreg_t                   pciep_wreg;
+       amdgpu_rreg64_t                 pcie_rreg64;
+       amdgpu_wreg64_t                 pcie_wreg64;
        /* protects concurrent UVD register access */
        spinlock_t uvd_ctx_idx_lock;
        amdgpu_rreg_t                   uvd_ctx_rreg;
@@ -836,6 +868,7 @@ struct amdgpu_device {
        dma_addr_t                      dummy_page_addr;
        struct amdgpu_vm_manager        vm_manager;
        struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
+       unsigned                        num_vmhubs;
 
        /* memory management */
        struct amdgpu_mman              mman;
@@ -915,6 +948,9 @@ struct amdgpu_device {
        /* KFD */
        struct amdgpu_kfd_dev           kfd;
 
+       /* UMC */
+       struct amdgpu_umc               umc;
+
        /* display related functionality */
        struct amdgpu_display_manager dm;
 
@@ -965,6 +1001,7 @@ struct amdgpu_device {
        /* record last mm index being written through WREG32*/
        unsigned long last_mm_index;
        bool                            in_gpu_reset;
+       enum pp_mp1_state               mp1_state;
        struct mutex  lock_reset;
        struct amdgpu_doorbell_index doorbell_index;
 
@@ -1033,6 +1070,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
+#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
+#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
@@ -1093,6 +1132,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
  */
 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
+#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
index 9fa4f25a3745ad9889a87afe704dda1d0577b960..07eb29885372ae2457fd0ddfc9ded3fc56e2e368 100644 (file)
@@ -87,7 +87,12 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
        case CHIP_RAVEN:
                kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
                break;
+       case CHIP_ARCTURUS:
+               kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
+               break;
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();
                break;
        default:
@@ -651,8 +656,12 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 
-       if (adev->powerplay.pp_funcs &&
-           adev->powerplay.pp_funcs->switch_power_profile)
+       if (is_support_sw_smu(adev))
+               smu_switch_power_profile(&adev->smu,
+                                        PP_SMC_POWER_PROFILE_COMPUTE,
+                                        !idle);
+       else if (adev->powerplay.pp_funcs &&
+                adev->powerplay.pp_funcs->switch_power_profile)
                amdgpu_dpm_switch_power_profile(adev,
                                                PP_SMC_POWER_PROFILE_COMPUTE,
                                                !idle);
@@ -715,6 +724,11 @@ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
        return NULL;
 }
 
+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
+{
+       return NULL;
+}
+
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)
 {
        return NULL;
index b6076d19e4429c1b304563e44cbea8e1f4f40567..e519df3fd2b6fd1d706e58300f2f6e23aa56c257 100644 (file)
@@ -140,6 +140,7 @@ bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void);
+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void);
 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void);
 
 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
new file mode 100644 (file)
index 0000000..c79aaeb
--- /dev/null
@@ -0,0 +1,323 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#undef pr_fmt
+#define pr_fmt(fmt) "kfd2kgd: " fmt
+
+#include <linux/module.h>
+#include <linux/fdtable.h>
+#include <linux/uaccess.h>
+#include <linux/mmu_context.h>
+#include <linux/firmware.h>
+#include "amdgpu.h"
+#include "amdgpu_amdkfd.h"
+#include "sdma0/sdma0_4_2_2_offset.h"
+#include "sdma0/sdma0_4_2_2_sh_mask.h"
+#include "sdma1/sdma1_4_2_2_offset.h"
+#include "sdma1/sdma1_4_2_2_sh_mask.h"
+#include "sdma2/sdma2_4_2_2_offset.h"
+#include "sdma2/sdma2_4_2_2_sh_mask.h"
+#include "sdma3/sdma3_4_2_2_offset.h"
+#include "sdma3/sdma3_4_2_2_sh_mask.h"
+#include "sdma4/sdma4_4_2_2_offset.h"
+#include "sdma4/sdma4_4_2_2_sh_mask.h"
+#include "sdma5/sdma5_4_2_2_offset.h"
+#include "sdma5/sdma5_4_2_2_sh_mask.h"
+#include "sdma6/sdma6_4_2_2_offset.h"
+#include "sdma6/sdma6_4_2_2_sh_mask.h"
+#include "sdma7/sdma7_4_2_2_offset.h"
+#include "sdma7/sdma7_4_2_2_sh_mask.h"
+#include "v9_structs.h"
+#include "soc15.h"
+#include "soc15d.h"
+#include "amdgpu_amdkfd_gfx_v9.h"
+
+#define HQD_N_REGS 56
+#define DUMP_REG(addr) do {                            \
+               if (WARN_ON_ONCE(i >= HQD_N_REGS))      \
+                       break;                          \
+               (*dump)[i][0] = (addr) << 2;            \
+               (*dump)[i++][1] = RREG32(addr);         \
+       } while (0)
+
+static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
+{
+       return (struct amdgpu_device *)kgd;
+}
+
+static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
+{
+       return (struct v9_sdma_mqd *)mqd;
+}
+
+static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
+                               unsigned int engine_id,
+                               unsigned int queue_id)
+{
+       uint32_t base[8] = {
+               SOC15_REG_OFFSET(SDMA0, 0,
+                                mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
+               SOC15_REG_OFFSET(SDMA1, 0,
+                                mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL,
+               SOC15_REG_OFFSET(SDMA2, 0,
+                                mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL,
+               SOC15_REG_OFFSET(SDMA3, 0,
+                                mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL,
+               SOC15_REG_OFFSET(SDMA4, 0,
+                                mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL,
+               SOC15_REG_OFFSET(SDMA5, 0,
+                                mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL,
+               SOC15_REG_OFFSET(SDMA6, 0,
+                                mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL,
+               SOC15_REG_OFFSET(SDMA7, 0,
+                                mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
+       };
+       uint32_t retval;
+
+       retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
+                                              mmSDMA0_RLC0_RB_CNTL);
+
+       pr_debug("sdma base address: 0x%x\n", retval);
+
+       return retval;
+}
+
+static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+               u32 instance, u32 offset)
+{
+       switch (instance) {
+       case 0:
+               return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
+       case 1:
+               return (adev->reg_offset[SDMA1_HWIP][0][1] + offset);
+       case 2:
+               return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
+       case 3:
+               return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
+       case 4:
+               return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
+       case 5:
+               return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
+       case 6:
+               return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
+       case 7:
+               return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
+       default:
+               break;
+       }
+       return 0;
+}
+
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+                            uint32_t __user *wptr, struct mm_struct *mm)
+{
+       struct amdgpu_device *adev = get_amdgpu_device(kgd);
+       struct v9_sdma_mqd *m;
+       uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
+       unsigned long end_jiffies;
+       uint32_t data;
+       uint64_t data64;
+       uint64_t __user *wptr64 = (uint64_t __user *)wptr;
+
+       m = get_sdma_mqd(mqd);
+       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+                                           m->sdma_queue_id);
+       sdmax_gfx_context_cntl = sdma_v4_0_get_reg_offset(adev,
+                       m->sdma_engine_id, mmSDMA0_GFX_CONTEXT_CNTL);
+
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+               m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+
+       end_jiffies = msecs_to_jiffies(2000) + jiffies;
+       while (true) {
+               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+                       break;
+               if (time_after(jiffies, end_jiffies))
+                       return -ETIME;
+               usleep_range(500, 1000);
+       }
+       data = RREG32(sdmax_gfx_context_cntl);
+       data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+                            RESUME_CTX, 0);
+       WREG32(sdmax_gfx_context_cntl, data);
+
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
+              m->sdmax_rlcx_doorbell_offset);
+
+       data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+                            ENABLE, 1);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
+                               m->sdmax_rlcx_rb_rptr_hi);
+
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
+       if (read_user_wptr(mm, wptr64, data64)) {
+               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+                      lower_32_bits(data64));
+               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+                      upper_32_bits(data64));
+       } else {
+               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+                      m->sdmax_rlcx_rb_rptr);
+               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
+                      m->sdmax_rlcx_rb_rptr_hi);
+       }
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
+
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+                       m->sdmax_rlcx_rb_base_hi);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+                       m->sdmax_rlcx_rb_rptr_addr_lo);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+                       m->sdmax_rlcx_rb_rptr_addr_hi);
+
+       data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
+                            RB_ENABLE, 1);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+
+       return 0;
+}
+
+static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
+                            uint32_t engine_id, uint32_t queue_id,
+                            uint32_t (**dump)[2], uint32_t *n_regs)
+{
+       struct amdgpu_device *adev = get_amdgpu_device(kgd);
+       uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
+       uint32_t i = 0, reg;
+#undef HQD_N_REGS
+#define HQD_N_REGS (19+6+7+10)
+
+       *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
+       if (*dump == NULL)
+               return -ENOMEM;
+
+       for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
+               DUMP_REG(sdma_base_addr + reg);
+       for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
+               DUMP_REG(sdma_base_addr + reg);
+       for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
+            reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
+               DUMP_REG(sdma_base_addr + reg);
+       for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
+            reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
+               DUMP_REG(sdma_base_addr + reg);
+
+       WARN_ON_ONCE(i != HQD_N_REGS);
+       *n_regs = i;
+
+       return 0;
+}
+
+static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
+{
+       struct amdgpu_device *adev = get_amdgpu_device(kgd);
+       struct v9_sdma_mqd *m;
+       uint32_t sdma_base_addr;
+       uint32_t sdma_rlc_rb_cntl;
+
+       m = get_sdma_mqd(mqd);
+       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+                                           m->sdma_queue_id);
+
+       sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+
+       if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
+               return true;
+
+       return false;
+}
+
+static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
+                               unsigned int utimeout)
+{
+       struct amdgpu_device *adev = get_amdgpu_device(kgd);
+       struct v9_sdma_mqd *m;
+       uint32_t sdma_base_addr;
+       uint32_t temp;
+       unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
+
+       m = get_sdma_mqd(mqd);
+       sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
+                                           m->sdma_queue_id);
+
+       temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
+       temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
+
+       while (true) {
+               temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+               if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+                       break;
+               if (time_after(jiffies, end_jiffies))
+                       return -ETIME;
+               usleep_range(500, 1000);
+       }
+
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
+       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+               SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
+
+       m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+       m->sdmax_rlcx_rb_rptr_hi =
+               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
+
+       return 0;
+}
+
+static const struct kfd2kgd_calls kfd2kgd = {
+       .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
+       .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
+       .init_interrupts = kgd_gfx_v9_init_interrupts,
+       .hqd_load = kgd_gfx_v9_hqd_load,
+       .hqd_sdma_load = kgd_hqd_sdma_load,
+       .hqd_dump = kgd_gfx_v9_hqd_dump,
+       .hqd_sdma_dump = kgd_hqd_sdma_dump,
+       .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
+       .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
+       .hqd_destroy = kgd_gfx_v9_hqd_destroy,
+       .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
+       .address_watch_disable = kgd_gfx_v9_address_watch_disable,
+       .address_watch_execute = kgd_gfx_v9_address_watch_execute,
+       .wave_control_execute = kgd_gfx_v9_wave_control_execute,
+       .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
+       .get_atc_vmid_pasid_mapping_pasid =
+                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
+       .get_atc_vmid_pasid_mapping_valid =
+                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
+       .set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
+       .get_tile_config = kgd_gfx_v9_get_tile_config,
+       .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
+       .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+       .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
+       .get_hive_id = amdgpu_amdkfd_get_hive_id,
+};
+
+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
+{
+       return (struct kfd2kgd_calls *)&kfd2kgd;
+}
+
index 0723f800e8155b89a00eb32ecd96fd5ed6ad7bc2..7c03a7fcd0117863057dbffbf18449023cedfd6d 100644 (file)
@@ -27,7 +27,6 @@
 #include <linux/uaccess.h>
 #include <linux/firmware.h>
 #include <linux/mmu_context.h>
-#include <drm/drmP.h>
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_ucode.h"
index 85395f2d83a65fcfe27f81863afc8abfb21e86db..9d153cf395811aa9a001ef018a7c7b46320423b3 100644 (file)
@@ -47,6 +47,7 @@
 #include "soc15d.h"
 #include "mmhub_v1_0.h"
 #include "gfxhub_v1_0.h"
+#include "gmc_v9_0.h"
 
 
 #define V9_PIPE_PER_MEC                (4)
@@ -58,66 +59,11 @@ enum hqd_dequeue_request_type {
        RESET_WAVES
 };
 
-/*
- * Register access functions
- */
-
-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
-               uint32_t sh_mem_config,
-               uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
-               uint32_t sh_mem_bases);
-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
-               unsigned int vmid);
-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
-                       uint32_t queue_id, uint32_t __user *wptr,
-                       uint32_t wptr_shift, uint32_t wptr_mask,
-                       struct mm_struct *mm);
-static int kgd_hqd_dump(struct kgd_dev *kgd,
-                       uint32_t pipe_id, uint32_t queue_id,
-                       uint32_t (**dump)[2], uint32_t *n_regs);
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
-                            uint32_t __user *wptr, struct mm_struct *mm);
-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
-                            uint32_t engine_id, uint32_t queue_id,
-                            uint32_t (**dump)[2], uint32_t *n_regs);
-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
-               uint32_t pipe_id, uint32_t queue_id);
-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
-                               enum kfd_preempt_type reset_type,
-                               unsigned int utimeout, uint32_t pipe_id,
-                               uint32_t queue_id);
-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
-                               unsigned int utimeout);
-static int kgd_address_watch_disable(struct kgd_dev *kgd);
-static int kgd_address_watch_execute(struct kgd_dev *kgd,
-                                       unsigned int watch_point_id,
-                                       uint32_t cntl_val,
-                                       uint32_t addr_hi,
-                                       uint32_t addr_lo);
-static int kgd_wave_control_execute(struct kgd_dev *kgd,
-                                       uint32_t gfx_index_val,
-                                       uint32_t sq_cmd);
-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
-                                       unsigned int watch_point_id,
-                                       unsigned int reg_offset);
-
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-               uint8_t vmid);
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-               uint8_t vmid);
-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
-               uint64_t page_table_base);
-static void set_scratch_backing_va(struct kgd_dev *kgd,
-                                       uint64_t va, uint32_t vmid);
-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
 
 /* Because of REG_GET_FIELD() being used, we put this function in the
  * asic specific file.
  */
-static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
+int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
                struct tile_config *config)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
@@ -135,39 +81,6 @@ static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
        return 0;
 }
 
-static const struct kfd2kgd_calls kfd2kgd = {
-       .program_sh_mem_settings = kgd_program_sh_mem_settings,
-       .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
-       .init_interrupts = kgd_init_interrupts,
-       .hqd_load = kgd_hqd_load,
-       .hqd_sdma_load = kgd_hqd_sdma_load,
-       .hqd_dump = kgd_hqd_dump,
-       .hqd_sdma_dump = kgd_hqd_sdma_dump,
-       .hqd_is_occupied = kgd_hqd_is_occupied,
-       .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
-       .hqd_destroy = kgd_hqd_destroy,
-       .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
-       .address_watch_disable = kgd_address_watch_disable,
-       .address_watch_execute = kgd_address_watch_execute,
-       .wave_control_execute = kgd_wave_control_execute,
-       .address_watch_get_offset = kgd_address_watch_get_offset,
-       .get_atc_vmid_pasid_mapping_pasid =
-                       get_atc_vmid_pasid_mapping_pasid,
-       .get_atc_vmid_pasid_mapping_valid =
-                       get_atc_vmid_pasid_mapping_valid,
-       .set_scratch_backing_va = set_scratch_backing_va,
-       .get_tile_config = amdgpu_amdkfd_get_tile_config,
-       .set_vm_context_page_table_base = set_vm_context_page_table_base,
-       .invalidate_tlbs = invalidate_tlbs,
-       .invalidate_tlbs_vmid = invalidate_tlbs_vmid,
-       .get_hive_id = amdgpu_amdkfd_get_hive_id,
-};
-
-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
-{
-       return (struct kfd2kgd_calls *)&kfd2kgd;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
@@ -215,7 +128,7 @@ static void release_queue(struct kgd_dev *kgd)
        unlock_srbm(kgd);
 }
 
-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
+void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
                                        uint32_t sh_mem_config,
                                        uint32_t sh_mem_ape1_base,
                                        uint32_t sh_mem_ape1_limit,
@@ -232,7 +145,7 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
        unlock_srbm(kgd);
 }
 
-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
+int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
                                        unsigned int vmid)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -293,7 +206,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  * but still works
  */
 
-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
+int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
        uint32_t mec;
@@ -343,7 +256,7 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
        return (struct v9_sdma_mqd *)mqd;
 }
 
-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
+int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
                        uint32_t queue_id, uint32_t __user *wptr,
                        uint32_t wptr_shift, uint32_t wptr_mask,
                        struct mm_struct *mm)
@@ -438,7 +351,7 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
        return 0;
 }
 
-static int kgd_hqd_dump(struct kgd_dev *kgd,
+int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd,
                        uint32_t pipe_id, uint32_t queue_id,
                        uint32_t (**dump)[2], uint32_t *n_regs)
 {
@@ -575,7 +488,7 @@ static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
        return 0;
 }
 
-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
+bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
                                uint32_t pipe_id, uint32_t queue_id)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -616,7 +529,7 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
        return false;
 }
 
-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
+int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd,
                                enum kfd_preempt_type reset_type,
                                unsigned int utimeout, uint32_t pipe_id,
                                uint32_t queue_id)
@@ -704,7 +617,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
        return 0;
 }
 
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
                                                        uint8_t vmid)
 {
        uint32_t reg;
@@ -715,7 +628,7 @@ static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
        return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
 }
 
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
                                                                uint8_t vmid)
 {
        uint32_t reg;
@@ -754,7 +667,7 @@ static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid,
        return 0;
 }
 
-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
+int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
        int vmid;
@@ -773,8 +686,8 @@ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
        for (vmid = 0; vmid < 16; vmid++) {
                if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
                        continue;
-               if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
-                       if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
+               if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
+                       if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
                                == pasid) {
                                amdgpu_gmc_flush_gpu_tlb(adev, vmid,
                                                         flush_type);
@@ -786,7 +699,7 @@ static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
        return 0;
 }
 
-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
+int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 
@@ -814,12 +727,12 @@ static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
        return 0;
 }
 
-static int kgd_address_watch_disable(struct kgd_dev *kgd)
+int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd)
 {
        return 0;
 }
 
-static int kgd_address_watch_execute(struct kgd_dev *kgd,
+int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd,
                                        unsigned int watch_point_id,
                                        uint32_t cntl_val,
                                        uint32_t addr_hi,
@@ -828,7 +741,7 @@ static int kgd_address_watch_execute(struct kgd_dev *kgd,
        return 0;
 }
 
-static int kgd_wave_control_execute(struct kgd_dev *kgd,
+int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd,
                                        uint32_t gfx_index_val,
                                        uint32_t sq_cmd)
 {
@@ -853,14 +766,14 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
        return 0;
 }
 
-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
+uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
                                        unsigned int watch_point_id,
                                        unsigned int reg_offset)
 {
        return 0;
 }
 
-static void set_scratch_backing_va(struct kgd_dev *kgd,
+void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
                                        uint64_t va, uint32_t vmid)
 {
        /* No longer needed on GFXv9. The scratch base address is
@@ -869,7 +782,7 @@ static void set_scratch_backing_va(struct kgd_dev *kgd,
         */
 }
 
-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
                uint64_t page_table_base)
 {
        struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -884,7 +797,45 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
         * now, all processes share the same address space size, like
         * on GFX8 and older.
         */
-       mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
+       if (adev->asic_type == CHIP_ARCTURUS) {
+               /* Two MMHUBs */
+               mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base);
+               mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base);
+       } else
+               mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
 
        gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
 }
+
+static const struct kfd2kgd_calls kfd2kgd = {
+       .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
+       .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
+       .init_interrupts = kgd_gfx_v9_init_interrupts,
+       .hqd_load = kgd_gfx_v9_hqd_load,
+       .hqd_sdma_load = kgd_hqd_sdma_load,
+       .hqd_dump = kgd_gfx_v9_hqd_dump,
+       .hqd_sdma_dump = kgd_hqd_sdma_dump,
+       .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
+       .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
+       .hqd_destroy = kgd_gfx_v9_hqd_destroy,
+       .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
+       .address_watch_disable = kgd_gfx_v9_address_watch_disable,
+       .address_watch_execute = kgd_gfx_v9_address_watch_execute,
+       .wave_control_execute = kgd_gfx_v9_wave_control_execute,
+       .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
+       .get_atc_vmid_pasid_mapping_pasid =
+                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
+       .get_atc_vmid_pasid_mapping_valid =
+                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
+       .set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
+       .get_tile_config = kgd_gfx_v9_get_tile_config,
+       .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
+       .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
+       .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
+       .get_hive_id = amdgpu_amdkfd_get_hive_id,
+};
+
+struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
+{
+       return (struct kfd2kgd_calls *)&kfd2kgd;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
new file mode 100644 (file)
index 0000000..26d8879
--- /dev/null
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+
+void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
+               uint32_t sh_mem_config,
+               uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
+               uint32_t sh_mem_bases);
+int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
+               unsigned int vmid);
+int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
+int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
+                       uint32_t queue_id, uint32_t __user *wptr,
+                       uint32_t wptr_shift, uint32_t wptr_mask,
+                       struct mm_struct *mm);
+int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd,
+                       uint32_t pipe_id, uint32_t queue_id,
+                       uint32_t (**dump)[2], uint32_t *n_regs);
+bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
+               uint32_t pipe_id, uint32_t queue_id);
+int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd,
+                               enum kfd_preempt_type reset_type,
+                               unsigned int utimeout, uint32_t pipe_id,
+                               uint32_t queue_id);
+int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd);
+int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd,
+                                       unsigned int watch_point_id,
+                                       uint32_t cntl_val,
+                                       uint32_t addr_hi,
+                                       uint32_t addr_lo);
+int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd,
+                                       uint32_t gfx_index_val,
+                                       uint32_t sq_cmd);
+uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
+                                       unsigned int watch_point_id,
+                                       unsigned int reg_offset);
+
+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
+               uint8_t vmid);
+uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
+               uint8_t vmid);
+void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
+               uint64_t page_table_base);
+void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
+                                       uint64_t va, uint32_t vmid);
+int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
+int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
+int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
+               struct tile_config *config);
index 6a5c96e519b15983bc3fb1ff1037727245245511..14d9c250b3d31472794ae1e42b42e18f8d0d1987 100644 (file)
@@ -1090,7 +1090,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
         */
        if (flags & ALLOC_MEM_FLAGS_VRAM) {
                domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
-               alloc_flags = AMDGPU_GEM_CREATE_VRAM_CLEARED;
+               alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
                alloc_flags |= (flags & ALLOC_MEM_FLAGS_PUBLIC) ?
                        AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
                        AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
index f539a2a927747add782a608796775299128bd184..ec311de86fba6c871dab8f03272740b972e44cce 100644 (file)
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
                           struct amdgpu_ctx *ctx)
 {
        unsigned num_entities = amdgput_ctx_total_num_entities();
-       unsigned i, j;
+       unsigned i, j, k;
        int r;
 
        if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -123,7 +123,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
        for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
                struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
                struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
-               unsigned num_rings;
+               unsigned num_rings = 0;
                unsigned num_rqs = 0;
 
                switch (i) {
@@ -154,16 +154,26 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
                        num_rings = 1;
                        break;
                case AMDGPU_HW_IP_VCN_DEC:
-                       rings[0] = &adev->vcn.ring_dec;
-                       num_rings = 1;
+                       for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
+                               if (adev->vcn.harvest_config & (1 << j))
+                                       continue;
+                               rings[num_rings++] = &adev->vcn.inst[j].ring_dec;
+                       }
                        break;
                case AMDGPU_HW_IP_VCN_ENC:
-                       rings[0] = &adev->vcn.ring_enc[0];
-                       num_rings = 1;
+                       for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
+                               if (adev->vcn.harvest_config & (1 << j))
+                                       continue;
+                               for (k = 0; k < adev->vcn.num_enc_rings; ++k)
+                                       rings[num_rings++] = &adev->vcn.inst[j].ring_enc[k];
+                       }
                        break;
                case AMDGPU_HW_IP_VCN_JPEG:
-                       rings[0] = &adev->vcn.ring_jpeg;
-                       num_rings = 1;
+                       for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
+                               if (adev->vcn.harvest_config & (1 << j))
+                                       continue;
+                               rings[num_rings++] = &adev->vcn.inst[j].ring_jpeg;
+                       }
                        break;
                }
 
index 5a7f893cf72448d9a4d6e9c12b0d3827d3e7bdcb..682833f90fddfc1fad1d9658ce4e61dad99ae123 100644 (file)
@@ -70,7 +70,10 @@ MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS               2000
 
@@ -98,7 +101,10 @@ static const char *amdgpu_asic_name[] = {
        "VEGA12",
        "VEGA20",
        "RAVEN",
+       "ARCTURUS",
        "NAVI10",
+       "NAVI14",
+       "NAVI12",
        "LAST",
 };
 
@@ -412,6 +418,40 @@ static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32
        BUG();
 }
 
+/**
+ * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
+ *
+ * @adev: amdgpu device pointer
+ * @reg: offset of register
+ *
+ * Dummy register read function.  Used for register blocks
+ * that certain asics don't have (all asics).
+ * Returns the value in the register.
+ */
+static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
+{
+       DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
+       BUG();
+       return 0;
+}
+
+/**
+ * amdgpu_invalid_wreg64 - dummy reg write function
+ *
+ * @adev: amdgpu device pointer
+ * @reg: offset of register
+ * @v: value to write to the register
+ *
+ * Dummy register read function.  Used for register blocks
+ * that certain asics don't have (all asics).
+ */
+static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
+{
+       DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
+                 reg, v);
+       BUG();
+}
+
 /**
  * amdgpu_block_invalid_rreg - dummy reg read function
  *
@@ -1384,9 +1424,18 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
                else
                        chip_name = "raven";
                break;
+       case CHIP_ARCTURUS:
+               chip_name = "arcturus";
+               break;
        case CHIP_NAVI10:
                chip_name = "navi10";
                break;
+       case CHIP_NAVI14:
+               chip_name = "navi14";
+               break;
+       case CHIP_NAVI12:
+               chip_name = "navi12";
+               break;
        }
 
        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -1529,6 +1578,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
        case CHIP_VEGA12:
        case CHIP_VEGA20:
        case CHIP_RAVEN:
+       case CHIP_ARCTURUS:
                if (adev->asic_type == CHIP_RAVEN)
                        adev->family = AMDGPU_FAMILY_RV;
                else
@@ -1539,6 +1589,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
                        return r;
                break;
        case  CHIP_NAVI10:
+       case  CHIP_NAVI14:
+       case  CHIP_NAVI12:
                adev->family = AMDGPU_FAMILY_NV;
 
                r = nv_set_ip_blocks(adev);
@@ -1560,9 +1612,6 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
                r = amdgpu_virt_request_full_gpu(adev, true);
                if (r)
                        return -EAGAIN;
-
-               /* query the reg access mode at the very beginning */
-               amdgpu_virt_init_reg_access_mode(adev);
        }
 
        adev->pm.pp_feature = amdgpu_pp_feature_mask;
@@ -1665,28 +1714,34 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
 
        if (adev->asic_type >= CHIP_VEGA10) {
                for (i = 0; i < adev->num_ip_blocks; i++) {
-                       if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
-                               if (adev->in_gpu_reset || adev->in_suspend) {
-                                       if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
-                                               break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
-                                       r = adev->ip_blocks[i].version->funcs->resume(adev);
-                                       if (r) {
-                                               DRM_ERROR("resume of IP block <%s> failed %d\n",
+                       if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
+                               continue;
+
+                       /* no need to do the fw loading again if already done*/
+                       if (adev->ip_blocks[i].status.hw == true)
+                               break;
+
+                       if (adev->in_gpu_reset || adev->in_suspend) {
+                               r = adev->ip_blocks[i].version->funcs->resume(adev);
+                               if (r) {
+                                       DRM_ERROR("resume of IP block <%s> failed %d\n",
                                                          adev->ip_blocks[i].version->funcs->name, r);
-                                               return r;
-                                       }
-                               } else {
-                                       r = adev->ip_blocks[i].version->funcs->hw_init(adev);
-                                       if (r) {
-                                               DRM_ERROR("hw_init of IP block <%s> failed %d\n",
-                                                 adev->ip_blocks[i].version->funcs->name, r);
-                                               return r;
-                                       }
+                                       return r;
+                               }
+                       } else {
+                               r = adev->ip_blocks[i].version->funcs->hw_init(adev);
+                               if (r) {
+                                       DRM_ERROR("hw_init of IP block <%s> failed %d\n",
+                                                         adev->ip_blocks[i].version->funcs->name, r);
+                                       return r;
                                }
-                               adev->ip_blocks[i].status.hw = true;
                        }
+
+                       adev->ip_blocks[i].status.hw = true;
+                       break;
                }
        }
+
        r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
 
        return r;
@@ -2128,7 +2183,9 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
                        if (r) {
                                DRM_ERROR("suspend of IP block <%s> failed %d\n",
                                          adev->ip_blocks[i].version->funcs->name, r);
+                               return r;
                        }
+                       adev->ip_blocks[i].status.hw = false;
                }
        }
 
@@ -2163,6 +2220,25 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
                        DRM_ERROR("suspend of IP block <%s> failed %d\n",
                                  adev->ip_blocks[i].version->funcs->name, r);
                }
+               adev->ip_blocks[i].status.hw = false;
+               /* handle putting the SMC in the appropriate state */
+               if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
+                       if (is_support_sw_smu(adev)) {
+                               /* todo */
+                       } else if (adev->powerplay.pp_funcs &&
+                                          adev->powerplay.pp_funcs->set_mp1_state) {
+                               r = adev->powerplay.pp_funcs->set_mp1_state(
+                                       adev->powerplay.pp_handle,
+                                       adev->mp1_state);
+                               if (r) {
+                                       DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
+                                                 adev->mp1_state, r);
+                                       return r;
+                               }
+                       }
+               }
+
+               adev->ip_blocks[i].status.hw = false;
        }
 
        return 0;
@@ -2215,6 +2291,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
                for (j = 0; j < adev->num_ip_blocks; j++) {
                        block = &adev->ip_blocks[j];
 
+                       block->status.hw = false;
                        if (block->version->type != ip_order[i] ||
                                !block->status.valid)
                                continue;
@@ -2223,6 +2300,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
                        DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
                        if (r)
                                return r;
+                       block->status.hw = true;
                }
        }
 
@@ -2250,13 +2328,15 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
                        block = &adev->ip_blocks[j];
 
                        if (block->version->type != ip_order[i] ||
-                               !block->status.valid)
+                               !block->status.valid ||
+                               block->status.hw)
                                continue;
 
                        r = block->version->funcs->hw_init(adev);
                        DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
                        if (r)
                                return r;
+                       block->status.hw = true;
                }
        }
 
@@ -2280,17 +2360,19 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
        int i, r;
 
        for (i = 0; i < adev->num_ip_blocks; i++) {
-               if (!adev->ip_blocks[i].status.valid)
+               if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
                        continue;
                if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
                    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
                    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
+
                        r = adev->ip_blocks[i].version->funcs->resume(adev);
                        if (r) {
                                DRM_ERROR("resume of IP block <%s> failed %d\n",
                                          adev->ip_blocks[i].version->funcs->name, r);
                                return r;
                        }
+                       adev->ip_blocks[i].status.hw = true;
                }
        }
 
@@ -2315,7 +2397,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
        int i, r;
 
        for (i = 0; i < adev->num_ip_blocks; i++) {
-               if (!adev->ip_blocks[i].status.valid)
+               if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
                        continue;
                if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
                    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
@@ -2328,6 +2410,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
                                  adev->ip_blocks[i].version->funcs->name, r);
                        return r;
                }
+               adev->ip_blocks[i].status.hw = true;
        }
 
        return 0;
@@ -2426,6 +2509,8 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 #endif
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
 #endif
                return amdgpu_dc != 0;
 #endif
@@ -2509,6 +2594,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        adev->pcie_wreg = &amdgpu_invalid_wreg;
        adev->pciep_rreg = &amdgpu_invalid_rreg;
        adev->pciep_wreg = &amdgpu_invalid_wreg;
+       adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
+       adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
        adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
        adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
        adev->didt_rreg = &amdgpu_invalid_rreg;
@@ -3627,6 +3714,17 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
 
        atomic_inc(&adev->gpu_reset_counter);
        adev->in_gpu_reset = 1;
+       switch (amdgpu_asic_reset_method(adev)) {
+       case AMD_RESET_METHOD_MODE1:
+               adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
+               break;
+       case AMD_RESET_METHOD_MODE2:
+               adev->mp1_state = PP_MP1_STATE_RESET;
+               break;
+       default:
+               adev->mp1_state = PP_MP1_STATE_NONE;
+               break;
+       }
        /* Block kfd: SRIOV would do it separately */
        if (!amdgpu_sriov_vf(adev))
                 amdgpu_amdkfd_pre_reset(adev);
@@ -3640,6 +3738,7 @@ static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
        if (!amdgpu_sriov_vf(adev))
                 amdgpu_amdkfd_post_reset(adev);
        amdgpu_vf_error_trans_all(adev);
+       adev->mp1_state = PP_MP1_STATE_NONE;
        adev->in_gpu_reset = 0;
        mutex_unlock(&adev->lock_reset);
 }
index 535650967b1a596c46e119867d25f3b493b908c1..dc65592f41b43166d7841bae1213bc9a949bd09a 100644 (file)
@@ -191,7 +191,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
        }
 
        if (!adev->enable_virtual_display) {
-               r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
+               r = amdgpu_bo_pin(new_abo,
+                                 amdgpu_display_supported_domains(adev, new_abo->flags));
                if (unlikely(r != 0)) {
                        DRM_ERROR("failed to pin new abo buffer before flip\n");
                        goto unreserve;
@@ -495,13 +496,25 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
        .create_handle = drm_gem_fb_create_handle,
 };
 
-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
+                                         uint64_t bo_flags)
 {
        uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 
 #if defined(CONFIG_DRM_AMD_DC)
-       if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
-           adev->flags & AMD_IS_APU &&
+       /*
+        * if amdgpu_bo_support_uswc returns false it means that USWC mappings
+        * is not supported for this board. But this mapping is required
+        * to avoid hang caused by placement of scanout BO in GTT on certain
+        * APUs. So force the BO placement to VRAM in case this architecture
+        * will not allow USWC mappings.
+        * Also, don't allow GTT domain if the BO doens't have USWC falg set.
+        */
+       if (adev->asic_type >= CHIP_CARRIZO &&
+           adev->asic_type <= CHIP_RAVEN &&
+           (adev->flags & AMD_IS_APU) &&
+           (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
+           amdgpu_bo_support_uswc(bo_flags) &&
            amdgpu_device_asic_has_dc_support(adev->asic_type))
                domain |= AMDGPU_GEM_DOMAIN_GTT;
 #endif
index 06b922fe0d42529223a8e9920711a208b5da0ecf..3620b24785e17779570cb6a07f54b4cad281dd99 100644 (file)
@@ -38,7 +38,8 @@
 int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
                                  struct drm_file *filp);
 void amdgpu_display_update_priority(struct amdgpu_device *adev);
-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
+                                         uint64_t bo_flags);
 struct drm_framebuffer *
 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
                                       struct drm_file *file_priv,
index 489041df1f45636da40966578799e5cecf39bcb5..974472fdfc6d4da19601101188e6385a35d1875f 100644 (file)
@@ -299,7 +299,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
        struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
        struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
        struct ttm_operation_ctx ctx = { true, false };
-       u32 domain = amdgpu_display_supported_domains(adev);
+       u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
        int ret;
        bool reads = (direction == DMA_BIDIRECTIONAL ||
                      direction == DMA_FROM_DEVICE);
index 790263dcc06447df16c710bfe0245afbe5c9ac62..3fa18003d4d63e4d2012fceaa5835dc3cc1f01d6 100644 (file)
@@ -130,13 +130,18 @@ typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
        AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,
        /* MMSCH: 392~407
         * overlap the doorbell assignment with VCN as they are  mutually exclusive
-        * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
+        * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
         */
-       AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
+       AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* VNC0 */
        AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,
        AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,
        AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,
 
+       AMDGPU_VEGA20_DOORBELL64_VCN8_9                  = 0x18C, /* VNC1 */
+       AMDGPU_VEGA20_DOORBELL64_VCNa_b                  = 0x18D,
+       AMDGPU_VEGA20_DOORBELL64_VCNc_d                  = 0x18E,
+       AMDGPU_VEGA20_DOORBELL64_VCNe_f                  = 0x18F,
+
        AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,
        AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,
        AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,
index 5376328d3fd0af4c8f5aeae321913d01fa03cb92..e3e09e6d7f4223ad6990690989415b2b8633ee6e 100644 (file)
@@ -996,6 +996,10 @@ static const struct pci_device_id pciidlist[] = {
        /* Raven */
        {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
        {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
+       /* Arcturus */
+       {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
+       {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
+       {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
        /* Navi10 */
        {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
        {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
@@ -1092,21 +1096,21 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
         * unfortunately we can't detect certain
         * hypervisors so just do this all the time.
         */
+       adev->mp1_state = PP_MP1_STATE_UNLOAD;
        amdgpu_device_ip_suspend(adev);
+       adev->mp1_state = PP_MP1_STATE_NONE;
 }
 
 static int amdgpu_pmops_suspend(struct device *dev)
 {
-       struct pci_dev *pdev = to_pci_dev(dev);
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
 
-       struct drm_device *drm_dev = pci_get_drvdata(pdev);
        return amdgpu_device_suspend(drm_dev, true, true);
 }
 
 static int amdgpu_pmops_resume(struct device *dev)
 {
-       struct pci_dev *pdev = to_pci_dev(dev);
-       struct drm_device *drm_dev = pci_get_drvdata(pdev);
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
 
        /* GPU comes up enabled by the bios on resume */
        if (amdgpu_device_is_px(drm_dev)) {
@@ -1120,33 +1124,29 @@ static int amdgpu_pmops_resume(struct device *dev)
 
 static int amdgpu_pmops_freeze(struct device *dev)
 {
-       struct pci_dev *pdev = to_pci_dev(dev);
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
 
-       struct drm_device *drm_dev = pci_get_drvdata(pdev);
        return amdgpu_device_suspend(drm_dev, false, true);
 }
 
 static int amdgpu_pmops_thaw(struct device *dev)
 {
-       struct pci_dev *pdev = to_pci_dev(dev);
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
 
-       struct drm_device *drm_dev = pci_get_drvdata(pdev);
        return amdgpu_device_resume(drm_dev, false, true);
 }
 
 static int amdgpu_pmops_poweroff(struct device *dev)
 {
-       struct pci_dev *pdev = to_pci_dev(dev);
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
 
-       struct drm_device *drm_dev = pci_get_drvdata(pdev);
        return amdgpu_device_suspend(drm_dev, true, true);
 }
 
 static int amdgpu_pmops_restore(struct device *dev)
 {
-       struct pci_dev *pdev = to_pci_dev(dev);
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
 
-       struct drm_device *drm_dev = pci_get_drvdata(pdev);
        return amdgpu_device_resume(drm_dev, false, true);
 }
 
@@ -1205,8 +1205,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
 
 static int amdgpu_pmops_runtime_idle(struct device *dev)
 {
-       struct pci_dev *pdev = to_pci_dev(dev);
-       struct drm_device *drm_dev = pci_get_drvdata(pdev);
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
        struct drm_crtc *crtc;
 
        if (!amdgpu_device_is_px(drm_dev)) {
index eb3569b46c1e112bd3b4dcf8e7e442221565ac0f..143753d237e7c697d51259724259177fe293a2cf 100644 (file)
@@ -131,6 +131,10 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
        int aligned_size, size;
        int height = mode_cmd->height;
        u32 cpp;
+       u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |
+                              AMDGPU_GEM_CREATE_VRAM_CLEARED        |
+                              AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 
        info = drm_get_format_info(adev->ddev, mode_cmd);
        cpp = info->cpp[0];
@@ -138,15 +142,11 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
        /* need to align pitch with crtc limits */
        mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
                                                  fb_tiled);
-       domain = amdgpu_display_supported_domains(adev);
-
+       domain = amdgpu_display_supported_domains(adev, flags);
        height = ALIGN(mode_cmd->height, 8);
        size = mode_cmd->pitches[0] * height;
        aligned_size = ALIGN(size, PAGE_SIZE);
-       ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
-                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
-                                      AMDGPU_GEM_CREATE_VRAM_CLEARED,
+       ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
                                       ttm_bo_type_kernel, NULL, &gobj);
        if (ret) {
                pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
@@ -168,7 +168,6 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
                        dev_err(adev->dev, "FB failed to set tiling flags\n");
        }
 
-
        ret = amdgpu_bo_pin(abo, domain);
        if (ret) {
                amdgpu_bo_unreserve(abo);
index 939f8305511b89ebebc2721b7ed420992311e95d..ddb07e9a71ca10d16fe1f5c2f7963c0fbc40fc82 100644 (file)
@@ -747,7 +747,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
        struct amdgpu_device *adev = dev->dev_private;
        struct drm_gem_object *gobj;
        uint32_t handle;
-       u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+       u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+                   AMDGPU_GEM_CREATE_CPU_GTT_USWC;
        u32 domain;
        int r;
 
@@ -764,7 +765,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
        args->size = (u64)args->pitch * args->height;
        args->size = ALIGN(args->size, PAGE_SIZE);
        domain = amdgpu_bo_get_preferred_pin_domain(adev,
-                               amdgpu_display_supported_domains(adev));
+                               amdgpu_display_supported_domains(adev, flags));
        r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
                                     ttm_bo_type_device, NULL, &gobj);
        if (r)
index 74066e1466f7b7907cdd72857b00aad4ef6a5ebc..f9bef3154b99833eff9a5f595c39a9a269176a79 100644 (file)
@@ -389,7 +389,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
                                dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
        }
 
-       if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
+       if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
                /* create MQD for each KGQ */
                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                        ring = &adev->gfx.gfx_ring[i];
@@ -437,7 +437,7 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
        struct amdgpu_ring *ring = NULL;
        int i;
 
-       if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
+       if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                        ring = &adev->gfx.gfx_ring[i];
                        kfree(adev->gfx.me.mqd_backup[i]);
@@ -456,7 +456,7 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
        }
 
        ring = &adev->gfx.kiq.ring;
-       if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring)
+       if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring)
                kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
        kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
        amdgpu_bo_free_kernel(&ring->mqd_obj,
index 1199b5828b90964f69059ebedef7e5b7e7de4f91..554a59b3c4a65cf964bbaf6d0635ddb1f6fc0106 100644 (file)
@@ -196,6 +196,8 @@ struct amdgpu_gfx_funcs {
                                uint32_t *dst);
        void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
                                 u32 queue, u32 vmid);
+       int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
+       int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
 };
 
 struct amdgpu_ngg_buf {
index 57b3d8a9bef3175d1b07394c67fa9d1acf05a393..529065b83885faaf892ffdf457ccf9aefafcd838 100644 (file)
@@ -368,7 +368,8 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm,
                 * are broken on Navi10 and Navi14.
                 */
                if (needs_flush && (adev->asic_type < CHIP_VEGA10 ||
-                                   adev->asic_type == CHIP_NAVI10))
+                                   adev->asic_type == CHIP_NAVI10 ||
+                                   adev->asic_type == CHIP_NAVI14))
                        continue;
 
                /* Good, we can use this VMID. Remember this submission as
index 0cf7e8606fd3d8e6df5f43cc15d33536e512d4bb..60ad1a9d56bb3a2bbf4fd35ecaa74963e58efdbe 100644 (file)
@@ -408,23 +408,38 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
                break;
        case AMDGPU_HW_IP_VCN_DEC:
                type = AMD_IP_BLOCK_TYPE_VCN;
-               if (adev->vcn.ring_dec.sched.ready)
-                       ++num_rings;
+               for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+                       if (adev->uvd.harvest_config & (1 << i))
+                               continue;
+
+                       if (adev->vcn.inst[i].ring_dec.sched.ready)
+                               ++num_rings;
+               }
                ib_start_alignment = 16;
                ib_size_alignment = 16;
                break;
        case AMDGPU_HW_IP_VCN_ENC:
                type = AMD_IP_BLOCK_TYPE_VCN;
-               for (i = 0; i < adev->vcn.num_enc_rings; i++)
-                       if (adev->vcn.ring_enc[i].sched.ready)
-                               ++num_rings;
+               for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+                       if (adev->uvd.harvest_config & (1 << i))
+                               continue;
+
+                       for (j = 0; j < adev->vcn.num_enc_rings; j++)
+                               if (adev->vcn.inst[i].ring_enc[j].sched.ready)
+                                       ++num_rings;
+               }
                ib_start_alignment = 64;
                ib_size_alignment = 1;
                break;
        case AMDGPU_HW_IP_VCN_JPEG:
                type = AMD_IP_BLOCK_TYPE_VCN;
-               if (adev->vcn.ring_jpeg.sched.ready)
-                       ++num_rings;
+               for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+                       if (adev->uvd.harvest_config & (1 << i))
+                               continue;
+
+                       if (adev->vcn.inst[i].ring_jpeg.sched.ready)
+                               ++num_rings;
+               }
                ib_start_alignment = 16;
                ib_size_alignment = 16;
                break;
index bea6f298dfdc5b47132abdba12a2b4999f693ac0..0c0a8e83ab8322d2014299313544b0d58eaeeecf 100644 (file)
@@ -80,9 +80,6 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
        if (bo->pin_count > 0)
                amdgpu_bo_subtract_pin_size(bo);
 
-       if (bo->kfd_bo)
-               amdgpu_amdkfd_unreserve_memory_limit(bo);
-
        amdgpu_bo_kunmap(bo);
 
        if (bo->gem_base.import_attach)
@@ -413,6 +410,40 @@ fail:
        return false;
 }
 
+bool amdgpu_bo_support_uswc(u64 bo_flags)
+{
+
+#ifdef CONFIG_X86_32
+       /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
+        * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
+        */
+       return false;
+#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
+       /* Don't try to enable write-combining when it can't work, or things
+        * may be slow
+        * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
+        */
+
+#ifndef CONFIG_COMPILE_TEST
+#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
+        thanks to write-combining
+#endif
+
+       if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
+               DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
+                             "better performance thanks to write-combining\n");
+       return false;
+#else
+       /* For architectures that don't support WC memory,
+        * mask out the WC flag from the BO
+        */
+       if (!drm_arch_can_wc_memory())
+               return false;
+
+       return true;
+#endif
+}
+
 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
                               struct amdgpu_bo_param *bp,
                               struct amdgpu_bo **bo_ptr)
@@ -466,33 +497,8 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 
        bo->flags = bp->flags;
 
-#ifdef CONFIG_X86_32
-       /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
-        * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
-        */
-       bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
-       /* Don't try to enable write-combining when it can't work, or things
-        * may be slow
-        * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
-        */
-
-#ifndef CONFIG_COMPILE_TEST
-#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
-        thanks to write-combining
-#endif
-
-       if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
-               DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
-                             "better performance thanks to write-combining\n");
-       bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-#else
-       /* For architectures that don't support WC memory,
-        * mask out the WC flag from the BO
-        */
-       if (!drm_arch_can_wc_memory())
+       if (!amdgpu_bo_support_uswc(bo->flags))
                bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-#endif
 
        bo->tbo.bdev = &adev->mman.bdev;
        if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
@@ -1211,6 +1217,42 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
        trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 }
 
+/**
+ * amdgpu_bo_move_notify - notification about a BO being released
+ * @bo: pointer to a buffer object
+ *
+ * Wipes VRAM buffers whose contents should not be leaked before the
+ * memory is released.
+ */
+void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
+{
+       struct dma_fence *fence = NULL;
+       struct amdgpu_bo *abo;
+       int r;
+
+       if (!amdgpu_bo_is_amdgpu_bo(bo))
+               return;
+
+       abo = ttm_to_amdgpu_bo(bo);
+
+       if (abo->kfd_bo)
+               amdgpu_amdkfd_unreserve_memory_limit(abo);
+
+       if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
+           !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
+               return;
+
+       reservation_object_lock(bo->resv, NULL);
+
+       r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->resv, &fence);
+       if (!WARN_ON(r)) {
+               amdgpu_bo_fence(abo, fence, false);
+               dma_fence_put(fence);
+       }
+
+       reservation_object_unlock(bo->resv);
+}
+
 /**
  * amdgpu_bo_fault_reserve_notify - notification about a memory fault
  * @bo: pointer to a buffer object
index d60593cc436e2727b1897ff8664dce85be711148..5a3c1779e20097194cae80b1f127501eb76b9b2a 100644 (file)
@@ -265,6 +265,7 @@ int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
                           bool evict,
                           struct ttm_mem_reg *new_mem);
+void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
                     bool shared);
@@ -308,5 +309,7 @@ void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
                                         struct seq_file *m);
 #endif
 
+bool amdgpu_bo_support_uswc(u64 bo_flags);
+
 
 #endif
index 2b546567853b45ee155fcc9faa9592b46d38066c..39998f203b493f648babe05e7f51b03275a8fb92 100644 (file)
@@ -325,13 +325,6 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
                return -EINVAL;
 
-       if (!amdgpu_sriov_vf(adev)) {
-               if (is_support_sw_smu(adev))
-                       current_level = smu_get_performance_level(&adev->smu);
-               else if (adev->powerplay.pp_funcs->get_performance_level)
-                       current_level = amdgpu_dpm_get_performance_level(adev);
-       }
-
        if (strncmp("low", buf, strlen("low")) == 0) {
                level = AMD_DPM_FORCED_LEVEL_LOW;
        } else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -355,17 +348,23 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
                goto fail;
        }
 
-        if (amdgpu_sriov_vf(adev)) {
-                if (amdgim_is_hwperf(adev) &&
-                    adev->virt.ops->force_dpm_level) {
-                        mutex_lock(&adev->pm.mutex);
-                        adev->virt.ops->force_dpm_level(adev, level);
-                        mutex_unlock(&adev->pm.mutex);
-                        return count;
-                } else {
-                        return -EINVAL;
+       /* handle sriov case here */
+       if (amdgpu_sriov_vf(adev)) {
+               if (amdgim_is_hwperf(adev) &&
+                   adev->virt.ops->force_dpm_level) {
+                       mutex_lock(&adev->pm.mutex);
+                       adev->virt.ops->force_dpm_level(adev, level);
+                       mutex_unlock(&adev->pm.mutex);
+                       return count;
+               } else {
+                       return -EINVAL;
                }
-        }
+       }
+
+       if (is_support_sw_smu(adev))
+               current_level = smu_get_performance_level(&adev->smu);
+       else if (adev->powerplay.pp_funcs->get_performance_level)
+               current_level = amdgpu_dpm_get_performance_level(adev);
 
        if (current_level == level)
                return count;
@@ -746,10 +745,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }
 
 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -761,7 +760,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
                struct device_attribute *attr,
                const char *buf,
                size_t count)
@@ -778,7 +777,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
        pr_debug("featuremask = 0x%llx\n", featuremask);
 
        if (is_support_sw_smu(adev)) {
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
                if (ret)
                        return -EINVAL;
        } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -790,7 +789,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
        return count;
 }
 
-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
                struct device_attribute *attr,
                char *buf)
 {
@@ -798,7 +797,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
        struct amdgpu_device *adev = ddev->dev_private;
 
        if (is_support_sw_smu(adev)) {
-               return smu_get_ppfeature_status(&adev->smu, buf);
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
        } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
                return amdgpu_dpm_get_ppfeature_status(adev, buf);
 
@@ -1458,9 +1457,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
                amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-               amdgpu_get_ppfeature_status,
-               amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_feature_status,
+               amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
 
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -1625,20 +1624,16 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
             (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
                return -EINVAL;
 
-       if (is_support_sw_smu(adev)) {
-               err = kstrtoint(buf, 10, &value);
-               if (err)
-                       return err;
+       err = kstrtoint(buf, 10, &value);
+       if (err)
+               return err;
 
+       if (is_support_sw_smu(adev)) {
                smu_set_fan_control_mode(&adev->smu, value);
        } else {
                if (!adev->powerplay.pp_funcs->set_fan_control_mode)
                        return -EINVAL;
 
-               err = kstrtoint(buf, 10, &value);
-               if (err)
-                       return err;
-
                amdgpu_dpm_set_fan_control_mode(adev, value);
        }
 
@@ -2058,16 +2053,18 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
                return err;
 
        value = value / 1000000; /* convert to Watt */
+
        if (is_support_sw_smu(adev)) {
-               adev->smu.funcs->set_power_limit(&adev->smu, value);
+               err = smu_set_power_limit(&adev->smu, value);
        } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
                err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
-               if (err)
-                       return err;
        } else {
-               return -EINVAL;
+               err = -EINVAL;
        }
 
+       if (err)
+               return err;
+
        return count;
 }
 
@@ -2917,10 +2914,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
        if ((adev->asic_type >= CHIP_VEGA10) &&
            !(adev->flags & AMD_IS_APU)) {
                ret = device_create_file(adev->dev,
-                               &dev_attr_ppfeatures);
+                               &dev_attr_pp_features);
                if (ret) {
                        DRM_ERROR("failed to create device file "
-                                       "ppfeatures\n");
+                                       "pp_features\n");
                        return ret;
                }
        }
@@ -2974,7 +2971,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
                device_remove_file(adev->dev, &dev_attr_unique_id);
        if ((adev->asic_type >= CHIP_VEGA10) &&
            !(adev->flags & AMD_IS_APU))
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);
+               device_remove_file(adev->dev, &dev_attr_pp_features);
 }
 
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
index c027e5e7713ef821297d78127e035fff8e3732d8..51fb890e2d3bc9cdada75c5ac62007dbc8b69316 100644 (file)
@@ -53,10 +53,13 @@ static int psp_early_init(void *handle)
                psp->autoload_supported = false;
                break;
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
                psp_v11_0_set_psp_funcs(psp);
                psp->autoload_supported = false;
                break;
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                psp_v11_0_set_psp_funcs(psp);
                psp->autoload_supported = true;
                break;
@@ -162,8 +165,8 @@ psp_cmd_submit_buf(struct psp_context *psp,
                if (ucode)
                        DRM_WARN("failed to load ucode id (%d) ",
                                  ucode->ucode_id);
-               DRM_WARN("psp command failed and response status is (%d)\n",
-                         psp->cmd_buf_mem->resp.status);
+               DRM_WARN("psp command failed and response status is (0x%X)\n",
+                         psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
                if (!timeout) {
                        mutex_unlock(&psp->mutex);
                        return -EINVAL;
@@ -831,7 +834,6 @@ static int psp_hw_start(struct psp_context *psp)
                                "XGMI: Failed to initialize XGMI session\n");
        }
 
-
        if (psp->adev->psp.ta_fw) {
                ret = psp_ras_initialize(psp);
                if (ret)
@@ -852,6 +854,24 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
        case AMDGPU_UCODE_ID_SDMA1:
                *type = GFX_FW_TYPE_SDMA1;
                break;
+       case AMDGPU_UCODE_ID_SDMA2:
+               *type = GFX_FW_TYPE_SDMA2;
+               break;
+       case AMDGPU_UCODE_ID_SDMA3:
+               *type = GFX_FW_TYPE_SDMA3;
+               break;
+       case AMDGPU_UCODE_ID_SDMA4:
+               *type = GFX_FW_TYPE_SDMA4;
+               break;
+       case AMDGPU_UCODE_ID_SDMA5:
+               *type = GFX_FW_TYPE_SDMA5;
+               break;
+       case AMDGPU_UCODE_ID_SDMA6:
+               *type = GFX_FW_TYPE_SDMA6;
+               break;
+       case AMDGPU_UCODE_ID_SDMA7:
+               *type = GFX_FW_TYPE_SDMA7;
+               break;
        case AMDGPU_UCODE_ID_CP_CE:
                *type = GFX_FW_TYPE_CP_CE;
                break;
@@ -980,12 +1000,20 @@ out:
                if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
                    (psp_smu_reload_quirk(psp) || psp->autoload_supported))
                        continue;
+
                if (amdgpu_sriov_vf(adev) &&
                   (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
                    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
+                   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
+                   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
+                   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
+                   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
+                   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
+                   || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
                    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
                        /*skip ucode loading in SRIOV VF */
                        continue;
+
                if (psp->autoload_supported &&
                    (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
                     ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
@@ -997,7 +1025,8 @@ out:
                        return ret;
 
                /* Start rlc autoload after psp recieved all the gfx firmware */
-               if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
+               if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM ||
+                   (adev->asic_type == CHIP_NAVI12 && ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) {
                        ret = psp_rlc_autoload(psp);
                        if (ret) {
                                DRM_ERROR("Failed to start rlc autoload\n");
index fac7aa2c244fa9f80776165e193313d543fb9082..523f43732deeb52e4d299d44d3867925f02fc051 100644 (file)
 #include "amdgpu_ras.h"
 #include "amdgpu_atomfirmware.h"
 
-struct ras_ih_data {
-       /* interrupt bottom half */
-       struct work_struct ih_work;
-       int inuse;
-       /* IP callback */
-       ras_ih_cb cb;
-       /* full of entries */
-       unsigned char *ring;
-       unsigned int ring_size;
-       unsigned int element_size;
-       unsigned int aligned_element_size;
-       unsigned int rptr;
-       unsigned int wptr;
-};
-
-struct ras_fs_data {
-       char sysfs_name[32];
-       char debugfs_name[32];
-};
-
-struct ras_err_data {
-       unsigned long ue_count;
-       unsigned long ce_count;
-};
-
-struct ras_err_handler_data {
-       /* point to bad pages array */
-       struct {
-               unsigned long bp;
-               struct amdgpu_bo *bo;
-       } *bps;
-       /* the count of entries */
-       int count;
-       /* the space can place new entries */
-       int space_left;
-       /* last reserved entry's index + 1 */
-       int last_reserved;
-};
-
-struct ras_manager {
-       struct ras_common_if head;
-       /* reference count */
-       int use;
-       /* ras block link */
-       struct list_head node;
-       /* the device */
-       struct amdgpu_device *adev;
-       /* debugfs */
-       struct dentry *ent;
-       /* sysfs */
-       struct device_attribute sysfs_attr;
-       int attr_inuse;
-
-       /* fs node name */
-       struct ras_fs_data fs_data;
-
-       /* IH data */
-       struct ras_ih_data ih_data;
-
-       struct ras_err_data err_data;
-};
-
-struct ras_badpage {
-       unsigned int bp;
-       unsigned int size;
-       unsigned int flags;
-};
-
 const char *ras_error_string[] = {
        "none",
        "parity",
@@ -130,6 +62,9 @@ const char *ras_block_string[] = {
 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET                2
 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 
+/* inject address is 52 bits */
+#define        RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
+
 static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
                uint64_t offset, uint64_t size,
                struct amdgpu_bo **bo_ptr);
@@ -223,9 +158,14 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
                        return -EINVAL;
 
                data->head.block = block_id;
-               data->head.type = memcmp("ue", err, 2) == 0 ?
-                       AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE :
-                       AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
+               /* only ue and ce errors are supported */
+               if (!memcmp("ue", err, 2))
+                       data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+               else if (!memcmp("ce", err, 2))
+                       data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
+               else
+                       return -EINVAL;
+
                data->op = op;
 
                if (op == 2) {
@@ -310,7 +250,6 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
        struct ras_debug_if data;
-       struct amdgpu_bo *bo;
        int ret = 0;
 
        ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
@@ -328,17 +267,14 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *
                ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
                break;
        case 2:
-               ret = amdgpu_ras_reserve_vram(adev,
-                               data.inject.address, PAGE_SIZE, &bo);
-               if (ret) {
-                       /* address was offset, now it is absolute.*/
-                       data.inject.address += adev->gmc.vram_start;
-                       if (data.inject.address > adev->gmc.vram_end)
-                               break;
-               } else
-                       data.inject.address = amdgpu_bo_gpu_offset(bo);
+               if ((data.inject.address >= adev->gmc.mc_vram_size) ||
+                   (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
+                       ret = -EINVAL;
+                       break;
+               }
+
+               /* data.inject.address is offset instead of absolute gpu address */
                ret = amdgpu_ras_error_inject(adev, &data.inject);
-               amdgpu_ras_release_vram(adev, &bo);
                break;
        default:
                ret = -EINVAL;
@@ -656,14 +592,42 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
                struct ras_query_if *info)
 {
        struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
+       struct ras_err_data err_data = {0, 0, 0, NULL};
 
        if (!obj)
                return -EINVAL;
-       /* TODO might read the register to read the count */
+
+       switch (info->head.block) {
+       case AMDGPU_RAS_BLOCK__UMC:
+               if (adev->umc.funcs->query_ras_error_count)
+                       adev->umc.funcs->query_ras_error_count(adev, &err_data);
+               /* umc query_ras_error_address is also responsible for clearing
+                * error status
+                */
+               if (adev->umc.funcs->query_ras_error_address)
+                       adev->umc.funcs->query_ras_error_address(adev, &err_data);
+               break;
+       case AMDGPU_RAS_BLOCK__GFX:
+               if (adev->gfx.funcs->query_ras_error_count)
+                       adev->gfx.funcs->query_ras_error_count(adev, &err_data);
+               break;
+       default:
+               break;
+       }
+
+       obj->err_data.ue_count += err_data.ue_count;
+       obj->err_data.ce_count += err_data.ce_count;
 
        info->ue_count = obj->err_data.ue_count;
        info->ce_count = obj->err_data.ce_count;
 
+       if (err_data.ce_count)
+               dev_info(adev->dev, "%ld correctable errors detected in %s block\n",
+                        obj->err_data.ce_count, ras_block_str(info->head.block));
+       if (err_data.ue_count)
+               dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n",
+                        obj->err_data.ue_count, ras_block_str(info->head.block));
+
        return 0;
 }
 
@@ -684,13 +648,22 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
        if (!obj)
                return -EINVAL;
 
-       if (block_info.block_id != TA_RAS_BLOCK__UMC) {
+       switch (info->head.block) {
+       case AMDGPU_RAS_BLOCK__GFX:
+               if (adev->gfx.funcs->ras_error_inject)
+                       ret = adev->gfx.funcs->ras_error_inject(adev, info);
+               else
+                       ret = -EINVAL;
+               break;
+       case AMDGPU_RAS_BLOCK__UMC:
+               ret = psp_ras_trigger_error(&adev->psp, &block_info);
+               break;
+       default:
                DRM_INFO("%s error injection is not supported yet\n",
                         ras_block_str(info->head.block));
-               return -EINVAL;
+               ret = -EINVAL;
        }
 
-       ret = psp_ras_trigger_error(&adev->psp, &block_info);
        if (ret)
                DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
                                ras_block_str(info->head.block),
@@ -816,25 +789,18 @@ static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
        struct amdgpu_device *adev = ddev->dev_private;
        struct ras_common_if head;
        int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
-       int i;
+       int i, enabled;
        ssize_t s;
-       struct ras_manager *obj;
 
        s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
 
        for (i = 0; i < ras_block_count; i++) {
                head.block = i;
+               enabled = amdgpu_ras_is_feature_enabled(adev, &head);
 
-               if (amdgpu_ras_is_feature_enabled(adev, &head)) {
-                       obj = amdgpu_ras_find_obj(adev, &head);
-                       s += scnprintf(&buf[s], PAGE_SIZE - s,
-                                       "%s: %s\n",
-                                       ras_block_str(i),
-                                       ras_err_str(obj->head.type));
-               } else
-                       s += scnprintf(&buf[s], PAGE_SIZE - s,
-                                       "%s: disabled\n",
-                                       ras_block_str(i));
+               s += scnprintf(&buf[s], PAGE_SIZE - s,
+                               "%s ras feature mask: %s\n",
+                               ras_block_str(i), enabled?"on":"off");
        }
 
        return s;
@@ -1054,6 +1020,7 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
        struct ras_ih_data *data = &obj->ih_data;
        struct amdgpu_iv_entry entry;
        int ret;
+       struct ras_err_data err_data = {0, 0, 0, NULL};
 
        while (data->rptr != data->wptr) {
                rmb();
@@ -1068,19 +1035,19 @@ static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
                 * from the callback to udpate the error type/count, etc
                 */
                if (data->cb) {
-                       ret = data->cb(obj->adev, &entry);
+                       ret = data->cb(obj->adev, &err_data, &entry);
                        /* ue will trigger an interrupt, and in that case
                         * we need do a reset to recovery the whole system.
                         * But leave IP do that recovery, here we just dispatch
                         * the error.
                         */
-                       if (ret == AMDGPU_RAS_UE) {
-                               obj->err_data.ue_count++;
+                       if (ret == AMDGPU_RAS_SUCCESS) {
+                               /* these counts could be left as 0 if
+                                * some blocks do not count error number
+                                */
+                               obj->err_data.ue_count += err_data.ue_count;
+                               obj->err_data.ce_count += err_data.ce_count;
                        }
-                       /* Might need get ce count by register, but not all IP
-                        * saves ce count, some IP just use one bit or two bits
-                        * to indicate ce happened.
-                        */
                }
        }
 }
@@ -1577,6 +1544,10 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
        if (amdgpu_ras_fs_init(adev))
                goto fs_out;
 
+       /* ras init for each ras block */
+       if (adev->umc.funcs->ras_init)
+               adev->umc.funcs->ras_init(adev);
+
        DRM_INFO("RAS INFO: ras initialized successfully, "
                        "hardware ability[%x] ras_mask[%x]\n",
                        con->hw_supported, con->supported);
index b2841195bd3bbae0d0763d2370cc15c9ddaf9a99..2765f2dbb1e63a5367d93c5363df01655a5174d5 100644 (file)
@@ -52,6 +52,236 @@ enum amdgpu_ras_block {
 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
 #define AMDGPU_RAS_BLOCK_MASK  ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
 
+enum amdgpu_ras_gfx_subblock {
+       /* CPC */
+       AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+       AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
+               AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
+       AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
+       AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
+       AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
+       AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
+       AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
+       AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
+       AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
+               AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
+       /* CPF */
+       AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
+               AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
+       AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
+       AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
+       /* CPG */
+       AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
+               AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
+       AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
+       AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
+       /* GDS */
+       AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
+       AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
+       AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
+       AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
+       AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
+               AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
+       /* SPI */
+       AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
+       /* SQ */
+       AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
+       AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
+       AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
+       AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
+       /* SQC (3 ranges) */
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
+       /* SQC range 0 */
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
+               AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
+               AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
+               AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
+       /* SQC range 1 */
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
+               AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
+               AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
+       /* SQC range 2 */
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
+               AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
+               AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
+       AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
+               AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
+       /* TA */
+       AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
+               AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
+       AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
+       AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
+       AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
+       AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
+       /* TCA */
+       AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
+               AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
+               AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
+       /* TCC (5 sub-ranges) */
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
+       /* TCC range 0 */
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
+               AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
+               AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
+       AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
+       AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
+       AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
+       AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
+       AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
+       AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
+               AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
+       /* TCC range 1 */
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
+               AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
+               AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
+       /* TCC range 2 */
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
+               AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
+       AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
+       AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
+       AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
+       AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
+               AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
+       /* TCC range 3 */
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
+               AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
+               AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
+       /* TCC range 4 */
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
+               AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
+       AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
+               AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
+       AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
+               AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
+       /* TCI */
+       AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
+       /* TCP */
+       AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
+               AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
+       AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
+       AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
+       AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
+       AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
+               AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
+       /* TD */
+       AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
+               AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
+       AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
+       AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
+       /* EA (3 sub-ranges) */
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
+       /* EA range 0 */
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
+               AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
+       AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
+               AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
+       AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
+               AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
+       /* EA range 1 */
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
+       AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
+               AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
+       AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
+               AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
+       /* EA range 2 */
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
+       AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
+               AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
+       AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
+               AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
+       AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
+               AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
+       /* UTC VM L2 bank */
+       AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
+       /* UTC VM walker */
+       AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
+       /* UTC ATC L2 2MB cache */
+       AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
+       /* UTC ATC L2 4KB cache */
+       AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
+       AMDGPU_RAS_BLOCK__GFX_MAX
+};
+
 enum amdgpu_ras_error_type {
        AMDGPU_RAS_ERROR__NONE                                                  = 0,
        AMDGPU_RAS_ERROR__PARITY                                                = 1,
@@ -76,9 +306,6 @@ struct ras_common_if {
        char name[32];
 };
 
-typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
-               struct amdgpu_iv_entry *entry);
-
 struct amdgpu_ras {
        /* ras infrastructure */
        /* for ras itself. */
@@ -108,8 +335,81 @@ struct amdgpu_ras {
        uint32_t flags;
 };
 
-/* interfaces for IP */
+struct ras_fs_data {
+       char sysfs_name[32];
+       char debugfs_name[32];
+};
+
+struct ras_err_data {
+       unsigned long ue_count;
+       unsigned long ce_count;
+       unsigned long err_addr_cnt;
+       uint64_t *err_addr;
+};
+
+struct ras_err_handler_data {
+       /* point to bad pages array */
+       struct {
+               unsigned long bp;
+               struct amdgpu_bo *bo;
+       } *bps;
+       /* the count of entries */
+       int count;
+       /* the space can place new entries */
+       int space_left;
+       /* last reserved entry's index + 1 */
+       int last_reserved;
+};
+
+typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
+               struct ras_err_data *err_data,
+               struct amdgpu_iv_entry *entry);
 
+struct ras_ih_data {
+       /* interrupt bottom half */
+       struct work_struct ih_work;
+       int inuse;
+       /* IP callback */
+       ras_ih_cb cb;
+       /* full of entries */
+       unsigned char *ring;
+       unsigned int ring_size;
+       unsigned int element_size;
+       unsigned int aligned_element_size;
+       unsigned int rptr;
+       unsigned int wptr;
+};
+
+struct ras_manager {
+       struct ras_common_if head;
+       /* reference count */
+       int use;
+       /* ras block link */
+       struct list_head node;
+       /* the device */
+       struct amdgpu_device *adev;
+       /* debugfs */
+       struct dentry *ent;
+       /* sysfs */
+       struct device_attribute sysfs_attr;
+       int attr_inuse;
+
+       /* fs node name */
+       struct ras_fs_data fs_data;
+
+       /* IH data */
+       struct ras_ih_data ih_data;
+
+       struct ras_err_data err_data;
+};
+
+struct ras_badpage {
+       unsigned int bp;
+       unsigned int size;
+       unsigned int flags;
+};
+
+/* interfaces for IP */
 struct ras_fs_if {
        struct ras_common_if head;
        char sysfs_name[32];
index 4410c97ac9b7feff85e9671219c904576d1ff1f6..930316e601554003a42ae3a2fb83473a205379e3 100644 (file)
@@ -29,7 +29,7 @@
 #include <drm/drm_print.h>
 
 /* max number of rings */
-#define AMDGPU_MAX_RINGS               24
+#define AMDGPU_MAX_RINGS               28
 #define AMDGPU_MAX_GFX_RINGS           2
 #define AMDGPU_MAX_COMPUTE_RINGS       8
 #define AMDGPU_MAX_VCE_RINGS           3
index 35dd152f9d5c15c42942874156f98d35cba63f58..a9ae0d8a05894c54327b417728bc446af09937ee 100644 (file)
 #define __AMDGPU_SDMA_H__
 
 /* max number of IP instances */
-#define AMDGPU_MAX_SDMA_INSTANCES              2
+#define AMDGPU_MAX_SDMA_INSTANCES              8
 
 enum amdgpu_sdma_irq {
        AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
        AMDGPU_SDMA_IRQ_INSTANCE1,
+       AMDGPU_SDMA_IRQ_INSTANCE2,
+       AMDGPU_SDMA_IRQ_INSTANCE3,
+       AMDGPU_SDMA_IRQ_INSTANCE4,
+       AMDGPU_SDMA_IRQ_INSTANCE5,
+       AMDGPU_SDMA_IRQ_INSTANCE6,
+       AMDGPU_SDMA_IRQ_INSTANCE7,
        AMDGPU_SDMA_IRQ_LAST
 };
 
index e51b48ac48eb151fcf72d11a4bdf15b9a06dda0e..ab92b24ac4ff43503decdac2e7ab9a9ff028c706 100644 (file)
@@ -444,6 +444,22 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
        if (r)
                goto error;
 
+       /* clear the space being freed */
+       if (old_mem->mem_type == TTM_PL_VRAM &&
+           (ttm_to_amdgpu_bo(bo)->flags &
+            AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
+               struct dma_fence *wipe_fence = NULL;
+
+               r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
+                                      NULL, &wipe_fence);
+               if (r) {
+                       goto error;
+               } else if (wipe_fence) {
+                       dma_fence_put(fence);
+                       fence = wipe_fence;
+               }
+       }
+
        /* Always block for VM page tables before committing the new location */
        if (bo->type == ttm_bo_type_kernel)
                r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
@@ -1599,6 +1615,7 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
        .move = &amdgpu_bo_move,
        .verify_access = &amdgpu_verify_access,
        .move_notify = &amdgpu_bo_move_notify,
+       .release_notify = &amdgpu_bo_release_notify,
        .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
        .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
        .io_mem_free = &amdgpu_ttm_io_mem_free,
index caa76c693700cceaaea1b3a3213fa93c0f03b48f..bccb8c49e5977be785165c131e520e1c904166c0 100644 (file)
@@ -38,6 +38,8 @@
 #define AMDGPU_GTT_MAX_TRANSFER_SIZE   512
 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS        2
 
+#define AMDGPU_POISON  0xd0bed0be
+
 struct amdgpu_mman {
        struct ttm_bo_device            bdev;
        bool                            mem_global_referenced;
index bfaa0eac3213fa93a137d60464c90a32bc6db8d6..dd18ebc2eb0134e363e604a8c95995b93c1979be 100644 (file)
@@ -269,6 +269,16 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
                        DRM_DEBUG("kdb_size_bytes: %u\n",
                                  le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
                }
+               if (version_minor == 2) {
+                       const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
+                               container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
+                       DRM_DEBUG("kdb_header_version: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
+                       DRM_DEBUG("kdb_offset_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
+                       DRM_DEBUG("kdb_size_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
+               }
        } else {
                DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
                          version_major, version_minor);
@@ -351,10 +361,14 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
        case CHIP_VEGA12:
        case CHIP_VEGA20:
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                if (!load_type)
                        return AMDGPU_FW_LOAD_DIRECT;
                else
                        return AMDGPU_FW_LOAD_PSP;
+       case CHIP_ARCTURUS:
+               return AMDGPU_FW_LOAD_DIRECT;
        default:
                DRM_ERROR("Unknown firmware load type\n");
        }
index c1fb6dc86440d880593e9554d301dbacffe5274c..b34f00d420499d447ceb26464b687247edd891d6 100644 (file)
@@ -90,6 +90,15 @@ struct psp_firmware_header_v1_1 {
        uint32_t kdb_size_bytes;
 };
 
+/* version_major=1, version_minor=2 */
+struct psp_firmware_header_v1_2 {
+       struct psp_firmware_header_v1_0 v1_0;
+       uint32_t reserve[3];
+       uint32_t kdb_header_version;
+       uint32_t kdb_offset_bytes;
+       uint32_t kdb_size_bytes;
+};
+
 /* version_major=1, version_minor=0 */
 struct ta_firmware_header_v1_0 {
        struct common_firmware_header header;
@@ -262,6 +271,12 @@ union amdgpu_firmware_header {
 enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_SDMA0 = 0,
        AMDGPU_UCODE_ID_SDMA1,
+       AMDGPU_UCODE_ID_SDMA2,
+       AMDGPU_UCODE_ID_SDMA3,
+       AMDGPU_UCODE_ID_SDMA4,
+       AMDGPU_UCODE_ID_SDMA5,
+       AMDGPU_UCODE_ID_SDMA6,
+       AMDGPU_UCODE_ID_SDMA7,
        AMDGPU_UCODE_ID_CP_CE,
        AMDGPU_UCODE_ID_CP_PFP,
        AMDGPU_UCODE_ID_CP_ME,
@@ -281,6 +296,7 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_UVD1,
        AMDGPU_UCODE_ID_VCE,
        AMDGPU_UCODE_ID_VCN,
+       AMDGPU_UCODE_ID_VCN1,
        AMDGPU_UCODE_ID_DMCU_ERAM,
        AMDGPU_UCODE_ID_DMCU_INTV,
        AMDGPU_UCODE_ID_VCN0_RAM,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
new file mode 100644 (file)
index 0000000..975afa0
--- /dev/null
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __AMDGPU_UMC_H__
+#define __AMDGPU_UMC_H__
+
+/* implement 64 bits REG operations via 32 bits interface */
+#define RREG64_UMC(reg)        (RREG32(reg) | \
+                               ((uint64_t)RREG32((reg) + 1) << 32))
+#define WREG64_UMC(reg, v)     \
+       do {    \
+               WREG32((reg), lower_32_bits(v));        \
+               WREG32((reg) + 1, upper_32_bits(v));    \
+       } while (0)
+
+/*
+ * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
+ *                             uint32_t umc_reg_offset, uint32_t channel_index)
+ */
+#define amdgpu_umc_for_each_channel(func)      \
+       struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;        \
+       uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \
+       for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) {     \
+               /* enable the index mode to query eror count per channel */     \
+               adev->umc.funcs->enable_umc_index_mode(adev, umc_inst); \
+               for (channel_inst = 0;  \
+                       channel_inst < adev->umc.channel_inst_num;      \
+                       channel_inst++) {       \
+                       /* calc the register offset according to channel instance */    \
+                       umc_reg_offset = adev->umc.channel_offs * channel_inst; \
+                       /* get channel index of interleaved memory */   \
+                       channel_index = adev->umc.channel_idx_tbl[      \
+                               umc_inst * adev->umc.channel_inst_num + channel_inst];  \
+                       (func)(adev, err_data, umc_reg_offset, channel_index);  \
+               }       \
+       }       \
+       adev->umc.funcs->disable_umc_index_mode(adev);
+
+struct amdgpu_umc_funcs {
+       void (*ras_init)(struct amdgpu_device *adev);
+       void (*query_ras_error_count)(struct amdgpu_device *adev,
+                                       void *ras_error_status);
+       void (*query_ras_error_address)(struct amdgpu_device *adev,
+                                       void *ras_error_status);
+       void (*enable_umc_index_mode)(struct amdgpu_device *adev,
+                                       uint32_t umc_instance);
+       void (*disable_umc_index_mode)(struct amdgpu_device *adev);
+};
+
+struct amdgpu_umc {
+       /* max error count in one ras query call */
+       uint32_t max_ras_err_cnt_per_query;
+       /* number of umc channel instance with memory map register access */
+       uint32_t channel_inst_num;
+       /* number of umc instance with memory map register access */
+       uint32_t umc_inst_num;
+       /* UMC regiser per channel offset */
+       uint32_t channel_offs;
+       /* channel index table of interleaved memory */
+       const uint32_t *channel_idx_tbl;
+
+       const struct amdgpu_umc_funcs *funcs;
+};
+
+#endif
index 2e12eeb314a755bc00d9e15eb9979187cec1c968..47086cdbb41359d732465f04bf4b76a7cb77442a 100644 (file)
 #define FIRMWARE_RAVEN         "amdgpu/raven_vcn.bin"
 #define FIRMWARE_PICASSO       "amdgpu/picasso_vcn.bin"
 #define FIRMWARE_RAVEN2                "amdgpu/raven2_vcn.bin"
+#define FIRMWARE_ARCTURUS      "amdgpu/arcturus_vcn.bin"
 #define FIRMWARE_NAVI10        "amdgpu/navi10_vcn.bin"
+#define FIRMWARE_NAVI14        "amdgpu/navi14_vcn.bin"
+#define FIRMWARE_NAVI12        "amdgpu/navi12_vcn.bin"
 
 MODULE_FIRMWARE(FIRMWARE_RAVEN);
 MODULE_FIRMWARE(FIRMWARE_PICASSO);
 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
+MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
 MODULE_FIRMWARE(FIRMWARE_NAVI10);
+MODULE_FIRMWARE(FIRMWARE_NAVI14);
+MODULE_FIRMWARE(FIRMWARE_NAVI12);
 
 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
 
@@ -61,7 +67,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
        const char *fw_name;
        const struct common_firmware_header *hdr;
        unsigned char fw_check;
-       int r;
+       int i, r;
 
        INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
 
@@ -74,12 +80,27 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
                else
                        fw_name = FIRMWARE_RAVEN;
                break;
+       case CHIP_ARCTURUS:
+               fw_name = FIRMWARE_ARCTURUS;
+               break;
        case CHIP_NAVI10:
                fw_name = FIRMWARE_NAVI10;
                if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
                    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
                        adev->vcn.indirect_sram = true;
                break;
+       case CHIP_NAVI14:
+               fw_name = FIRMWARE_NAVI14;
+               if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+                   (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+                       adev->vcn.indirect_sram = true;
+               break;
+       case CHIP_NAVI12:
+               fw_name = FIRMWARE_NAVI12;
+               if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+                   (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+                       adev->vcn.indirect_sram = true;
+               break;
        default:
                return -EINVAL;
        }
@@ -133,12 +154,18 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
        bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
                bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
-       r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
-                                   AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
-                                   &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
-       if (r) {
-               dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
-               return r;
+
+       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+               if (adev->vcn.harvest_config & (1 << i))
+                       continue;
+
+               r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+                                               AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
+                                               &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
+               if (r) {
+                       dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
+                       return r;
+               }
        }
 
        if (adev->vcn.indirect_sram) {
@@ -156,26 +183,30 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 
 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 {
-       int i;
-
-       kvfree(adev->vcn.saved_bo);
+       int i, j;
 
        if (adev->vcn.indirect_sram) {
                amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
-                             &adev->vcn.dpg_sram_gpu_addr,
-                             (void **)&adev->vcn.dpg_sram_cpu_addr);
+                                     &adev->vcn.dpg_sram_gpu_addr,
+                                     (void **)&adev->vcn.dpg_sram_cpu_addr);
        }
 
-       amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
-                             &adev->vcn.gpu_addr,
-                             (void **)&adev->vcn.cpu_addr);
+       for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
+               if (adev->vcn.harvest_config & (1 << j))
+                       continue;
+               kvfree(adev->vcn.inst[j].saved_bo);
+
+               amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
+                                         &adev->vcn.inst[j].gpu_addr,
+                                         (void **)&adev->vcn.inst[j].cpu_addr);
 
-       amdgpu_ring_fini(&adev->vcn.ring_dec);
+               amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
 
-       for (i = 0; i < adev->vcn.num_enc_rings; ++i)
-               amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
+               for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+                       amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
 
-       amdgpu_ring_fini(&adev->vcn.ring_jpeg);
+               amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg);
+       }
 
        release_firmware(adev->vcn.fw);
 
@@ -186,21 +217,25 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 {
        unsigned size;
        void *ptr;
+       int i;
 
        cancel_delayed_work_sync(&adev->vcn.idle_work);
 
-       if (adev->vcn.vcpu_bo == NULL)
-               return 0;
-
-       size = amdgpu_bo_size(adev->vcn.vcpu_bo);
-       ptr = adev->vcn.cpu_addr;
+       for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+               if (adev->vcn.harvest_config & (1 << i))
+                       continue;
+               if (adev->vcn.inst[i].vcpu_bo == NULL)
+                       return 0;
 
-       adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL);
-       if (!adev->vcn.saved_bo)
-               return -ENOMEM;
+               size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
+               ptr = adev->vcn.inst[i].cpu_addr;
 
-       memcpy_fromio(adev->vcn.saved_bo, ptr, size);
+               adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
+               if (!adev->vcn.inst[i].saved_bo)
+                       return -ENOMEM;
 
+               memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
+       }
        return 0;
 }
 
@@ -208,32 +243,36 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
 {
        unsigned size;
        void *ptr;
+       int i;
 
-       if (adev->vcn.vcpu_bo == NULL)
-               return -EINVAL;
-
-       size = amdgpu_bo_size(adev->vcn.vcpu_bo);
-       ptr = adev->vcn.cpu_addr;
-
-       if (adev->vcn.saved_bo != NULL) {
-               memcpy_toio(ptr, adev->vcn.saved_bo, size);
-               kvfree(adev->vcn.saved_bo);
-               adev->vcn.saved_bo = NULL;
-       } else {
-               const struct common_firmware_header *hdr;
-               unsigned offset;
-
-               hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-               if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
-                       offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-                       memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
-                                   le32_to_cpu(hdr->ucode_size_bytes));
-                       size -= le32_to_cpu(hdr->ucode_size_bytes);
-                       ptr += le32_to_cpu(hdr->ucode_size_bytes);
+       for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+               if (adev->vcn.harvest_config & (1 << i))
+                       continue;
+               if (adev->vcn.inst[i].vcpu_bo == NULL)
+                       return -EINVAL;
+
+               size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
+               ptr = adev->vcn.inst[i].cpu_addr;
+
+               if (adev->vcn.inst[i].saved_bo != NULL) {
+                       memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
+                       kvfree(adev->vcn.inst[i].saved_bo);
+                       adev->vcn.inst[i].saved_bo = NULL;
+               } else {
+                       const struct common_firmware_header *hdr;
+                       unsigned offset;
+
+                       hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+                       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+                               offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+                               memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
+                                           le32_to_cpu(hdr->ucode_size_bytes));
+                               size -= le32_to_cpu(hdr->ucode_size_bytes);
+                               ptr += le32_to_cpu(hdr->ucode_size_bytes);
+                       }
+                       memset_io(ptr, 0, size);
                }
-               memset_io(ptr, 0, size);
        }
-
        return 0;
 }
 
@@ -241,35 +280,40 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 {
        struct amdgpu_device *adev =
                container_of(work, struct amdgpu_device, vcn.idle_work.work);
-       unsigned int fences = 0;
-       unsigned int i;
+       unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
+       unsigned int i, j;
 
-       for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
-               fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
-       }
+       for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
+               if (adev->vcn.harvest_config & (1 << j))
+                       continue;
+               for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+                       fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
+               }
 
-       if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
-               struct dpg_pause_state new_state;
+               if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
+                       struct dpg_pause_state new_state;
 
-               if (fences)
-                       new_state.fw_based = VCN_DPG_STATE__PAUSE;
-               else
-                       new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+                       if (fence[j])
+                               new_state.fw_based = VCN_DPG_STATE__PAUSE;
+                       else
+                               new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-               if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
-                       new_state.jpeg = VCN_DPG_STATE__PAUSE;
-               else
-                       new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+                       if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg))
+                               new_state.jpeg = VCN_DPG_STATE__PAUSE;
+                       else
+                               new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
 
-               adev->vcn.pause_dpg_mode(adev, &new_state);
-       }
+                       adev->vcn.pause_dpg_mode(adev, &new_state);
+               }
 
-       fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
-       fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
+               fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg);
+               fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
+               fences += fence[j];
+       }
 
        if (fences == 0) {
                amdgpu_gfx_off_ctrl(adev, true);
-               if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
+               if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
                        amdgpu_dpm_enable_uvd(adev, false);
                else
                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
@@ -286,7 +330,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 
        if (set_clocks) {
                amdgpu_gfx_off_ctrl(adev, false);
-               if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
+               if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
                        amdgpu_dpm_enable_uvd(adev, true);
                else
                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
@@ -299,14 +343,14 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
                unsigned int i;
 
                for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
-                       fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
+                       fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
                }
                if (fences)
                        new_state.fw_based = VCN_DPG_STATE__PAUSE;
                else
                        new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-               if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
+               if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg))
                        new_state.jpeg = VCN_DPG_STATE__PAUSE;
                else
                        new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
@@ -332,7 +376,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
        unsigned i;
        int r;
 
-       WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
+       WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r)
                return r;
@@ -340,7 +384,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(adev->vcn.external.scratch9);
+               tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
                if (tmp == 0xDEADBEEF)
                        break;
                udelay(1);
@@ -651,7 +695,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
        unsigned i;
        int r;
 
-       WREG32(adev->vcn.external.jpeg_pitch, 0xCAFEDEAD);
+       WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r)
                return r;
@@ -661,7 +705,7 @@ int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
        amdgpu_ring_commit(ring);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(adev->vcn.external.jpeg_pitch);
+               tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
                if (tmp == 0xDEADBEEF)
                        break;
                udelay(1);
@@ -735,7 +779,7 @@ int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        }
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(adev->vcn.external.jpeg_pitch);
+               tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
                if (tmp == 0xDEADBEEF)
                        break;
                udelay(1);
index 99f14fcc1460550c66e0bf7dfdfedcfc8b297723..dface275c81a39990af847a5294b3b2a498ef754 100644 (file)
 #define AMDGPU_VCN_FIRMWARE_OFFSET     256
 #define AMDGPU_VCN_MAX_ENC_RINGS       3
 
+#define AMDGPU_MAX_VCN_INSTANCES       2
+
+#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
+#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
+
+#define VCN_DEC_KMD_CMD                0x80000000
 #define VCN_DEC_CMD_FENCE              0x00000000
 #define VCN_DEC_CMD_TRAP               0x00000001
 #define VCN_DEC_CMD_WRITE_REG          0x00000004
@@ -145,34 +151,49 @@ struct amdgpu_vcn_reg{
        unsigned        data1;
        unsigned        cmd;
        unsigned        nop;
+       unsigned        context_id;
+       unsigned        ib_vmid;
+       unsigned        ib_bar_low;
+       unsigned        ib_bar_high;
+       unsigned        ib_size;
+       unsigned        gp_scratch8;
        unsigned        scratch9;
        unsigned        jpeg_pitch;
 };
 
-struct amdgpu_vcn {
+struct amdgpu_vcn_inst {
        struct amdgpu_bo        *vcpu_bo;
        void                    *cpu_addr;
        uint64_t                gpu_addr;
-       unsigned                fw_version;
        void                    *saved_bo;
-       struct delayed_work     idle_work;
-       const struct firmware   *fw;    /* VCN firmware */
        struct amdgpu_ring      ring_dec;
        struct amdgpu_ring      ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
        struct amdgpu_ring      ring_jpeg;
        struct amdgpu_irq_src   irq;
+       struct amdgpu_vcn_reg   external;
+};
+
+struct amdgpu_vcn {
+       unsigned                fw_version;
+       struct delayed_work     idle_work;
+       const struct firmware   *fw;    /* VCN firmware */
        unsigned                num_enc_rings;
        enum amd_powergating_state cur_state;
        struct dpg_pause_state pause_state;
-       struct amdgpu_vcn_reg   internal, external;
-       int (*pause_dpg_mode)(struct amdgpu_device *adev,
-               struct dpg_pause_state *new_state);
 
        bool                    indirect_sram;
        struct amdgpu_bo        *dpg_sram_bo;
        void                    *dpg_sram_cpu_addr;
        uint64_t                dpg_sram_gpu_addr;
        uint32_t                *dpg_sram_curr_addr;
+
+       uint8_t num_vcn_inst;
+       struct amdgpu_vcn_inst  inst[AMDGPU_MAX_VCN_INSTANCES];
+       struct amdgpu_vcn_reg   internal;
+
+       unsigned        harvest_config;
+       int (*pause_dpg_mode)(struct amdgpu_device *adev,
+               struct dpg_pause_state *new_state);
 };
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
index 59dd204498c52dff4bc1d1e62ecefa34e419d87f..e32ae906d79732521a1b3a8020d6faa5b5e5639b 100644 (file)
@@ -430,48 +430,3 @@ uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest)
 
        return clk;
 }
-
-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev)
-{
-       struct amdgpu_virt *virt = &adev->virt;
-
-       if (virt->ops && virt->ops->init_reg_access_mode)
-               virt->ops->init_reg_access_mode(adev);
-}
-
-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev)
-{
-       bool ret = false;
-       struct amdgpu_virt *virt = &adev->virt;
-
-       if (amdgpu_sriov_vf(adev)
-               && (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH))
-               ret = true;
-
-       return ret;
-}
-
-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev)
-{
-       bool ret = false;
-       struct amdgpu_virt *virt = &adev->virt;
-
-       if (amdgpu_sriov_vf(adev)
-               && (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_RLC)
-               && !(amdgpu_sriov_runtime(adev)))
-               ret = true;
-
-       return ret;
-}
-
-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev)
-{
-       bool ret = false;
-       struct amdgpu_virt *virt = &adev->virt;
-
-       if (amdgpu_sriov_vf(adev)
-               && (virt->reg_access_mode & AMDGPU_VIRT_REG_SKIP_SEETING))
-               ret = true;
-
-       return ret;
-}
index f5107731e9c4d2dc04ce8c5bebee1e7052f77d6e..b0b2bdc750df924df393dbabd99b0977cdda3749 100644 (file)
@@ -48,12 +48,6 @@ struct amdgpu_vf_error_buffer {
        uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
 };
 
-/* According to the fw feature, some new reg access modes are supported */
-#define AMDGPU_VIRT_REG_ACCESS_LEGACY          (1 << 0) /* directly mmio */
-#define AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH      (1 << 1) /* by PSP */
-#define AMDGPU_VIRT_REG_ACCESS_RLC             (1 << 2) /* by RLC */
-#define AMDGPU_VIRT_REG_SKIP_SEETING           (1 << 3) /* Skip setting reg */
-
 /**
  * struct amdgpu_virt_ops - amdgpu device virt operations
  */
@@ -65,7 +59,6 @@ struct amdgpu_virt_ops {
        void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
        int (*get_pp_clk)(struct amdgpu_device *adev, u32 type, char *buf);
        int (*force_dpm_level)(struct amdgpu_device *adev, u32 level);
-       void (*init_reg_access_mode)(struct amdgpu_device *adev);
 };
 
 /*
@@ -315,10 +308,4 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
 uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest);
 uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest);
-
-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev);
-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev);
-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev);
-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev);
-
 #endif
index 24c3c05e2fb7d70121b03f7ec111de018c67e96a..9ab31ea3cc60e62edb0c7f997688f1643b569b6e 100644 (file)
@@ -1574,7 +1574,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
        flags &= ~AMDGPU_PTE_EXECUTABLE;
        flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 
-       if (adev->asic_type == CHIP_NAVI10) {
+       if (adev->asic_type >= CHIP_NAVI10) {
                flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
                flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
        } else {
@@ -3060,12 +3060,12 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
        switch (args->in.op) {
        case AMDGPU_VM_OP_RESERVE_VMID:
                /* current, we only have requirement to reserve vmid from gfxhub */
-               r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
+               r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
                if (r)
                        return r;
                break;
        case AMDGPU_VM_OP_UNRESERVE_VMID:
-               amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
+               amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
                break;
        default:
                return -EINVAL;
index 489a162ca6207775b7bdcc3408bb0d77911701b9..2eda3a8c330d37472d3957c7a3d750cf060481a7 100644 (file)
@@ -90,7 +90,7 @@ struct amdgpu_bo_list_entry;
                                 | AMDGPU_PTE_WRITEABLE  \
                                 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
 
-/* NAVI10 only */
+/* gfx10 */
 #define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
 #define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)
 
@@ -100,9 +100,10 @@ struct amdgpu_bo_list_entry;
 #define AMDGPU_VM_FAULT_STOP_ALWAYS    2
 
 /* max number of VMHUB */
-#define AMDGPU_MAX_VMHUBS                      2
-#define AMDGPU_GFXHUB                          0
-#define AMDGPU_MMHUB                           1
+#define AMDGPU_MAX_VMHUBS                      3
+#define AMDGPU_GFXHUB_0                                0
+#define AMDGPU_MMHUB_0                         1
+#define AMDGPU_MMHUB_1                         2
 
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE                        (1ULL << 20)
index d11eba09eadd2ef6068f14a4e3ccec6a01d21407..65aae75f80fd5ee4b62b7dc2bdf4cecb24b1b859 100644 (file)
@@ -25,7 +25,7 @@
 #include "amdgpu.h"
 #include "amdgpu_xgmi.h"
 #include "amdgpu_smu.h"
-
+#include "df/df_3_6_offset.h"
 
 static DEFINE_MUTEX(xgmi_mutex);
 
@@ -131,9 +131,37 @@ static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
 
 }
 
+#define AMDGPU_XGMI_SET_FICAA(o)       ((o) | 0x456801)
+static ssize_t amdgpu_xgmi_show_error(struct device *dev,
+                                     struct device_attribute *attr,
+                                     char *buf)
+{
+       struct drm_device *ddev = dev_get_drvdata(dev);
+       struct amdgpu_device *adev = ddev->dev_private;
+       uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
+       uint64_t fica_out;
+       unsigned int error_count = 0;
+
+       ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
+       ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
 
-static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
+       fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in);
+       if (fica_out != 0x1f)
+               pr_err("xGMI error counters not enabled!\n");
+
+       fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in);
+
+       if ((fica_out & 0xffff) == 2)
+               error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
 
+       adev->df_funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
+
+       return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
+}
+
+
+static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
+static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
 
 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
                                         struct amdgpu_hive_info *hive)
@@ -148,6 +176,12 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
                return ret;
        }
 
+       /* Create xgmi error file */
+       ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
+       if (ret)
+               pr_err("failed to create xgmi_error\n");
+
+
        /* Create sysfs link to hive info folder on the first device */
        if (adev != hive->adev) {
                ret = sysfs_create_link(&adev->dev->kobj, hive->kobj,
@@ -248,7 +282,7 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
 
        dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
 
-       if (is_support_sw_smu(adev))
+       if (is_support_sw_smu_xgmi(adev))
                ret = smu_set_xgmi_pstate(&adev->smu, pstate);
        if (ret)
                dev_err(adev->dev,
@@ -296,23 +330,28 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
        struct amdgpu_xgmi      *entry;
        struct amdgpu_device *tmp_adev = NULL;
 
-       int count = 0, ret = -EINVAL;
+       int count = 0, ret = 0;
 
        if (!adev->gmc.xgmi.supported)
                return 0;
 
-       ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
-       if (ret) {
-               dev_err(adev->dev,
-                       "XGMI: Failed to get node id\n");
-               return ret;
-       }
+       if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
+               ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
+               if (ret) {
+                       dev_err(adev->dev,
+                               "XGMI: Failed to get hive id\n");
+                       return ret;
+               }
 
-       ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
-       if (ret) {
-               dev_err(adev->dev,
-                       "XGMI: Failed to get hive id\n");
-               return ret;
+               ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
+               if (ret) {
+                       dev_err(adev->dev,
+                               "XGMI: Failed to get node id\n");
+                       return ret;
+               }
+       } else {
+               adev->gmc.xgmi.hive_id = 16;
+               adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
        }
 
        hive = amdgpu_get_xgmi_hive(adev, 1);
@@ -332,29 +371,32 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
        top_info->num_nodes = count;
        hive->number_devices = count;
 
-       list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
-               /* update node list for other device in the hive */
-               if (tmp_adev != adev) {
-                       top_info = &tmp_adev->psp.xgmi_context.top_info;
-                       top_info->nodes[count - 1].node_id = adev->gmc.xgmi.node_id;
-                       top_info->num_nodes = count;
+       if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
+               list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
+                       /* update node list for other device in the hive */
+                       if (tmp_adev != adev) {
+                               top_info = &tmp_adev->psp.xgmi_context.top_info;
+                               top_info->nodes[count - 1].node_id =
+                                       adev->gmc.xgmi.node_id;
+                               top_info->num_nodes = count;
+                       }
+                       ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
+                       if (ret)
+                               goto exit;
                }
-               ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
-               if (ret)
-                       goto exit;
-       }
 
-       /* get latest topology info for each device from psp */
-       list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
-               ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
-                               &tmp_adev->psp.xgmi_context.top_info);
-               if (ret) {
-                       dev_err(tmp_adev->dev,
-                               "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
-                               tmp_adev->gmc.xgmi.node_id,
-                               tmp_adev->gmc.xgmi.hive_id, ret);
-                       /* To do : continue with some node failed or disable the whole hive */
-                       goto exit;
+               /* get latest topology info for each device from psp */
+               list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
+                       ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
+                                       &tmp_adev->psp.xgmi_context.top_info);
+                       if (ret) {
+                               dev_err(tmp_adev->dev,
+                                       "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
+                                       tmp_adev->gmc.xgmi.node_id,
+                                       tmp_adev->gmc.xgmi.hive_id, ret);
+                               /* To do : continue with some node failed or disable the whole hive */
+                               goto exit;
+                       }
                }
        }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
new file mode 100644 (file)
index 0000000..4853899
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "soc15.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "arct_ip_offset.h"
+
+int arct_reg_base_init(struct amdgpu_device *adev)
+{
+       /* HW has more IP blocks,  only initialized the block needed by our driver  */
+       uint32_t i;
+       for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+               adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+               adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+               adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+               adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+               adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
+               adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+               adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+               adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
+               adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+               adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+               adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
+               adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
+               adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));
+               adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));
+               adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));
+               adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i]));
+               adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i]));
+               adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i]));
+               adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+               adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+       }
+       return 0;
+}
+
+
index 89b32b6b81c88ac4f2ef3e3ebed218f7dc9ab963..7e6c0bc3e8dd74bd039e2bbd20768944f9ec6227 100644 (file)
@@ -74,6 +74,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
 
        switch (adev->asic_type) {
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
                athub_v2_0_update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
                athub_v2_0_update_medium_grain_light_sleep(adev,
index 1ffbc0d3d7a1bbb5adfdcd2c3784d1babb11dfa2..b81bb414fcb300a98312fa7d60c5ced4c72d05f7 100644 (file)
@@ -1291,6 +1291,12 @@ static int cik_asic_reset(struct amdgpu_device *adev)
        return r;
 }
 
+static enum amd_reset_method
+cik_asic_reset_method(struct amdgpu_device *adev)
+{
+       return AMD_RESET_METHOD_LEGACY;
+}
+
 static u32 cik_get_config_memsize(struct amdgpu_device *adev)
 {
        return RREG32(mmCONFIG_MEMSIZE);
@@ -1823,6 +1829,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
        .read_bios_from_rom = &cik_read_bios_from_rom,
        .read_register = &cik_read_register,
        .reset = &cik_asic_reset,
+       .reset_method = &cik_asic_reset_method,
        .set_vga_state = &cik_vga_set_state,
        .get_xclk = &cik_get_xclk,
        .set_uvd_clocks = &cik_set_uvd_clocks,
index 3cc0a16649f96db3534d0b9641114adb11797a6a..4c6d792d51a53570a753321922536c55fc6ab8bb 100644 (file)
@@ -457,7 +457,10 @@ static int dce_virtual_hw_init(void *handle)
        case CHIP_VEGA10:
        case CHIP_VEGA12:
        case CHIP_VEGA20:
+       case CHIP_ARCTURUS:
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                break;
        default:
                DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
index ef6e91f9f51c1c75396f406a9d0fe6636231f2f0..5850c8e34caacc57e2e44581c5e2892022ab7a3d 100644 (file)
@@ -93,6 +93,96 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
                NULL
 };
 
+static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+                                uint32_t ficaa_val)
+{
+       unsigned long flags, address, data;
+       uint32_t ficadl_val, ficadh_val;
+
+       address = adev->nbio_funcs->get_pcie_index_offset(adev);
+       data = adev->nbio_funcs->get_pcie_data_offset(adev);
+
+       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+       WREG32(data, ficaa_val);
+
+       WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
+       ficadl_val = RREG32(data);
+
+       WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+       ficadh_val = RREG32(data);
+
+       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+
+       return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
+}
+
+static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+                            uint32_t ficadl_val, uint32_t ficadh_val)
+{
+       unsigned long flags, address, data;
+
+       address = adev->nbio_funcs->get_pcie_index_offset(adev);
+       data = adev->nbio_funcs->get_pcie_data_offset(adev);
+
+       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+       WREG32(data, ficaa_val);
+
+       WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
+       WREG32(data, ficadl_val);
+
+       WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+       WREG32(data, ficadh_val);
+
+       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
+/*
+ * df_v3_6_perfmon_rreg - read perfmon lo and hi
+ *
+ * required to be atomic.  no mmio method provided so subsequent reads for lo
+ * and hi require to preserve df finite state machine
+ */
+static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+                           uint32_t lo_addr, uint32_t *lo_val,
+                           uint32_t hi_addr, uint32_t *hi_val)
+{
+       unsigned long flags, address, data;
+
+       address = adev->nbio_funcs->get_pcie_index_offset(adev);
+       data = adev->nbio_funcs->get_pcie_data_offset(adev);
+
+       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       WREG32(address, lo_addr);
+       *lo_val = RREG32(data);
+       WREG32(address, hi_addr);
+       *hi_val = RREG32(data);
+       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
+/*
+ * df_v3_6_perfmon_wreg - write to perfmon lo and hi
+ *
+ * required to be atomic.  no mmio method provided so subsequent reads after
+ * data writes cannot occur to preserve data fabrics finite state machine.
+ */
+static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+                           uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val)
+{
+       unsigned long flags, address, data;
+
+       address = adev->nbio_funcs->get_pcie_index_offset(adev);
+       data = adev->nbio_funcs->get_pcie_data_offset(adev);
+
+       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+       WREG32(address, lo_addr);
+       WREG32(data, lo_val);
+       WREG32(address, hi_addr);
+       WREG32(data, hi_val);
+       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
 /* get the number of df counters available */
 static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
                struct device_attribute *attr,
@@ -268,6 +358,10 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
                                          uint32_t *lo_val,
                                          uint32_t *hi_val)
 {
+
+       uint32_t eventsel, instance, unitmask;
+       uint32_t instance_10, instance_5432, instance_76;
+
        df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
 
        if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
@@ -276,40 +370,33 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
                return -ENXIO;
        }
 
-       if (lo_val && hi_val) {
-               uint32_t eventsel, instance, unitmask;
-               uint32_t instance_10, instance_5432, instance_76;
+       eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
+       unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
+       instance = DF_V3_6_GET_INSTANCE(config);
 
-               eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
-               unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
-               instance = DF_V3_6_GET_INSTANCE(config);
+       instance_10 = instance & 0x3;
+       instance_5432 = (instance >> 2) & 0xf;
+       instance_76 = (instance >> 6) & 0x3;
 
-               instance_10 = instance & 0x3;
-               instance_5432 = (instance >> 2) & 0xf;
-               instance_76 = (instance >> 6) & 0x3;
+       *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22);
+       *hi_val = (instance_76 << 29) | instance_5432;
 
-               *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;
-               *hi_val = (instance_76 << 29) | instance_5432;
-       }
+       DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
+               config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);
 
        return 0;
 }
 
-/* assign df performance counters for read */
-static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
-                                  uint64_t config,
-                                  int *is_assigned)
+/* add df performance counters for read */
+static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
+                                  uint64_t config)
 {
        int i, target_cntr;
 
-       *is_assigned = 0;
-
        target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
 
-       if (target_cntr >= 0) {
-               *is_assigned = 1;
+       if (target_cntr >= 0)
                return 0;
-       }
 
        for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
                if (adev->df_perfmon_config_assign_mask[i] == 0U) {
@@ -344,45 +431,13 @@ static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
        if ((lo_base_addr == 0) || (hi_base_addr == 0))
                return;
 
-       WREG32_PCIE(lo_base_addr, 0UL);
-       WREG32_PCIE(hi_base_addr, 0UL);
-}
-
-
-static int df_v3_6_add_perfmon_cntr(struct amdgpu_device *adev,
-                                     uint64_t config)
-{
-       uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
-       int ret, is_assigned;
-
-       ret = df_v3_6_pmc_assign_cntr(adev, config, &is_assigned);
-
-       if (ret || is_assigned)
-               return ret;
-
-       ret = df_v3_6_pmc_get_ctrl_settings(adev,
-                       config,
-                       &lo_base_addr,
-                       &hi_base_addr,
-                       &lo_val,
-                       &hi_val);
-
-       if (ret)
-               return ret;
-
-       DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
-                       config, lo_base_addr, hi_base_addr, lo_val, hi_val);
-
-       WREG32_PCIE(lo_base_addr, lo_val);
-       WREG32_PCIE(hi_base_addr, hi_val);
-
-       return ret;
+       df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
 }
 
 static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
                             int is_enable)
 {
-       uint32_t lo_base_addr, hi_base_addr, lo_val;
+       uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
        int ret = 0;
 
        switch (adev->asic_type) {
@@ -391,24 +446,20 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
                df_v3_6_reset_perfmon_cntr(adev, config);
 
                if (is_enable) {
-                       ret = df_v3_6_add_perfmon_cntr(adev, config);
+                       ret = df_v3_6_pmc_add_cntr(adev, config);
                } else {
                        ret = df_v3_6_pmc_get_ctrl_settings(adev,
                                        config,
                                        &lo_base_addr,
                                        &hi_base_addr,
-                                       NULL,
-                                       NULL);
+                                       &lo_val,
+                                       &hi_val);
 
                        if (ret)
                                return ret;
 
-                       lo_val = RREG32_PCIE(lo_base_addr);
-
-                       DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
-                               config, lo_base_addr, hi_base_addr, lo_val);
-
-                       WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
+                       df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
+                                       hi_base_addr, hi_val);
                }
 
                break;
@@ -422,7 +473,7 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
 static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
                            int is_disable)
 {
-       uint32_t lo_base_addr, hi_base_addr, lo_val;
+       uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
        int ret = 0;
 
        switch (adev->asic_type) {
@@ -431,18 +482,13 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
                        config,
                        &lo_base_addr,
                        &hi_base_addr,
-                       NULL,
-                       NULL);
+                       &lo_val,
+                       &hi_val);
 
                if (ret)
                        return ret;
 
-               lo_val = RREG32_PCIE(lo_base_addr);
-
-               DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
-                               config, lo_base_addr, hi_base_addr, lo_val);
-
-               WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
+               df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
 
                if (is_disable)
                        df_v3_6_pmc_release_cntr(adev, config);
@@ -471,8 +517,8 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
                if ((lo_base_addr == 0) || (hi_base_addr == 0))
                        return;
 
-               lo_val = RREG32_PCIE(lo_base_addr);
-               hi_val = RREG32_PCIE(hi_base_addr);
+               df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
+                               hi_base_addr, &hi_val);
 
                *count  = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
 
@@ -480,7 +526,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
                        *count = 0;
 
                DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
-                       config, lo_base_addr, hi_base_addr, lo_val, hi_val);
+                        config, lo_base_addr, hi_base_addr, lo_val, hi_val);
 
                break;
 
@@ -499,5 +545,7 @@ const struct amdgpu_df_funcs df_v3_6_funcs = {
        .get_clockgating_state = df_v3_6_get_clockgating_state,
        .pmc_start = df_v3_6_pmc_start,
        .pmc_stop = df_v3_6_pmc_stop,
-       .pmc_get_count = df_v3_6_pmc_get_count
+       .pmc_get_count = df_v3_6_pmc_get_count,
+       .get_fica = df_v3_6_get_fica,
+       .set_fica = df_v3_6_set_fica
 };
index 32773b7523d204a8b29266931fb4a9e577c571a4..43427a3148b74094c6b89c7514b6148b97b86801 100644 (file)
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
 #include <linux/firmware.h>
-#include <drm/drmP.h>
+#include <linux/module.h>
+#include <linux/pci.h>
 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
 #include "amdgpu_psp.h"
@@ -56,6 +60,9 @@
 #define F32_CE_PROGRAM_RAM_SIZE                65536
 #define RLCG_UCODE_LOADING_START_ADDRESS       0x00002000L
 
+#define mmCGTT_GS_NGG_CLK_CTRL 0x5087
+#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX        1
+
 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -63,6 +70,20 @@ MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
+MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
+MODULE_FIRMWARE("amdgpu/navi14_me.bin");
+MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
+MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
+MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
+
+MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
+MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
+MODULE_FIRMWARE("amdgpu/navi12_me.bin");
+MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
+MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
+MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -109,6 +130,99 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
        /* Pending on emulation bring up */
 };
 
+static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
+{
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
+};
+
+static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
+{
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
+};
+
+static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
+{
+       /* Pending on emulation bring up */
+};
+
+static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
+{
+       /* Pending on emulation bring up */
+};
+
 #define DEFAULT_SH_MEM_CONFIG \
        ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
         (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -250,6 +364,22 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
                                                golden_settings_gc_10_0_nv10,
                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
                break;
+       case CHIP_NAVI14:
+               soc15_program_register_sequence(adev,
+                                               golden_settings_gc_10_1_1,
+                                               (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
+               soc15_program_register_sequence(adev,
+                                               golden_settings_gc_10_1_nv14,
+                                               (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
+               break;
+       case CHIP_NAVI12:
+               soc15_program_register_sequence(adev,
+                                               golden_settings_gc_10_1_2,
+                                               (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
+               soc15_program_register_sequence(adev,
+                                               golden_settings_gc_10_1_2_nv12,
+                                               (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
+               break;
        default:
                break;
        }
@@ -331,7 +461,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
                if (amdgpu_emu_mode == 1)
                        msleep(1);
                else
-                       DRM_UDELAY(1);
+                       udelay(1);
        }
        if (i < adev->usec_timeout) {
                if (amdgpu_emu_mode == 1)
@@ -481,6 +611,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
        case CHIP_NAVI10:
                chip_name = "navi10";
                break;
+       case CHIP_NAVI14:
+               chip_name = "navi14";
+               break;
+       case CHIP_NAVI12:
+               chip_name = "navi12";
+               break;
        default:
                BUG();
        }
@@ -1026,6 +1162,8 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -1133,6 +1271,8 @@ static int gfx_v10_0_sw_init(void *handle)
 
        switch (adev->asic_type) {
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 2;
                adev->gfx.me.num_queue_per_pipe = 1;
@@ -1452,6 +1592,25 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
        }
 }
 
+static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
+       }
+}
+
+
 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
 {
        int i, j, k;
@@ -1461,7 +1620,8 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
        u32 utcl_invreq_disable = 0;
        /*
         * GCRD_TARGETS_DISABLE field contains
-        * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
+        * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
+        * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
         */
        u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
                2 * max_wgp_per_sh + /* TCP */
@@ -1469,7 +1629,8 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
                4); /* GL1C */
        /*
         * UTCL1_UTCL0_INVREQ_DISABLE field contains
-        * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
+        * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
+        * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
         */
        u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
                2 * max_wgp_per_sh + /* TCP */
@@ -1477,7 +1638,9 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
                4 + /* RMI */
                1); /* SQG */
 
-       if (adev->asic_type == CHIP_NAVI10) {
+       if (adev->asic_type == CHIP_NAVI10 ||
+           adev->asic_type == CHIP_NAVI14 ||
+           adev->asic_type == CHIP_NAVI12) {
                mutex_lock(&adev->grbm_idx_mutex);
                for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
                        for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
@@ -1535,7 +1698,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */
        mutex_lock(&adev->srbm_mutex);
-       for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
+       for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
                nv_grbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
@@ -1552,6 +1715,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v10_0_init_compute_vmid(adev);
+       gfx_v10_0_init_gds_vmid(adev);
 
 }
 
@@ -1624,9 +1788,9 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
                 * hence no handshake between SMU & RLC
                 * GFXOFF will be disabled
                 */
-               rlc_pg_cntl |= 0x80000;
+               rlc_pg_cntl |= 0x800000;
        } else
-               rlc_pg_cntl &= ~0x80000;
+               rlc_pg_cntl &= ~0x800000;
        WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
 }
 
@@ -4037,6 +4201,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
        bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
        switch (adev->asic_type) {
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
                if (!enable) {
                        amdgpu_gfx_off_ctrl(adev, false);
                        cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
@@ -4056,6 +4221,8 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
 
        switch (adev->asic_type) {
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                gfx_v10_0_update_gfx_clock_gating(adev,
                                                 state == AMD_CG_STATE_GATE ? true : false);
                break;
@@ -4462,7 +4629,7 @@ static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
                if (ring->trail_seq ==
                    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 
        if (i >= adev->usec_timeout) {
@@ -4936,7 +5103,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
-       .vmhub = AMDGPU_GFXHUB,
+       .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
        .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
        .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
@@ -4987,7 +5154,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
-       .vmhub = AMDGPU_GFXHUB,
+       .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v10_0_ring_get_rptr_compute,
        .get_wptr = gfx_v10_0_ring_get_wptr_compute,
        .set_wptr = gfx_v10_0_ring_set_wptr_compute,
@@ -5020,7 +5187,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
-       .vmhub = AMDGPU_GFXHUB,
+       .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v10_0_ring_get_rptr_compute,
        .get_wptr = gfx_v10_0_ring_get_wptr_compute,
        .set_wptr = gfx_v10_0_ring_set_wptr_compute,
@@ -5097,6 +5264,8 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
                break;
        default:
index 21187275dfd37e496db7de2de3f21f2518a606f9..791ba398f007ef17e1330fd6160ba69d7f7d0043 100644 (file)
@@ -1890,6 +1890,24 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
        }
 }
 
+static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+       }
+}
+
 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
 {
        adev->gfx.config.double_offchip_lds_buf = 1;
@@ -1968,6 +1986,7 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v7_0_init_compute_vmid(adev);
+       gfx_v7_0_init_gds_vmid(adev);
 
        WREG32(mmSX_DEBUG_1, 0x20);
 
index 751567f78567357c0099cf426c550fe7d9d72b3f..87dd55e9d72b2fe7d8323f8fef33e9024b2fc03d 100644 (file)
@@ -1321,6 +1321,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
        return 0;
 }
 
+static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
+{
+       int r;
+
+       r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+       if (unlikely(r != 0))
+               return r;
+
+       r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+                       AMDGPU_GEM_DOMAIN_VRAM);
+       if (!r)
+               adev->gfx.rlc.clear_state_gpu_addr =
+                       amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
+
+       amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+
+       return r;
+}
+
+static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
+{
+       int r;
+
+       if (!adev->gfx.rlc.clear_state_obj)
+               return;
+
+       r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+       if (likely(r == 0)) {
+               amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+               amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+       }
+}
+
 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 {
        amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -3717,6 +3750,24 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
        }
 }
 
+static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
+       }
+}
+
 static void gfx_v8_0_config_init(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
@@ -3783,6 +3834,7 @@ static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v8_0_init_compute_vmid(adev);
+       gfx_v8_0_init_gds_vmid(adev);
 
        mutex_lock(&adev->grbm_idx_mutex);
        /*
@@ -4785,6 +4837,10 @@ static int gfx_v8_0_hw_init(void *handle)
        gfx_v8_0_init_golden_registers(adev);
        gfx_v8_0_constants_init(adev);
 
+       r = gfx_v8_0_csb_vram_pin(adev);
+       if (r)
+               return r;
+
        r = adev->gfx.rlc.funcs->resume(adev);
        if (r)
                return r;
@@ -4901,6 +4957,9 @@ static int gfx_v8_0_hw_fini(void *handle)
        else
                pr_err("rlc is busy, skip halt rlc\n");
        amdgpu_gfx_rlc_exit_safe_mode(adev);
+
+       gfx_v8_0_csb_vram_unpin(adev);
+
        return 0;
 }
 
index 1cf639a511783c9cb1280f86a6ddbc3a5577c349..52a6fd12e26655fd50731d864c0d8101113ceeff 100644 (file)
@@ -104,6 +104,390 @@ MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
+MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
+MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
+
+#define mmTCP_CHAN_STEER_0_ARCT                                                                0x0b03
+#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX                                                       0
+#define mmTCP_CHAN_STEER_1_ARCT                                                                0x0b04
+#define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX                                                       0
+#define mmTCP_CHAN_STEER_2_ARCT                                                                0x0b09
+#define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX                                                       0
+#define mmTCP_CHAN_STEER_3_ARCT                                                                0x0b0a
+#define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX                                                       0
+#define mmTCP_CHAN_STEER_4_ARCT                                                                0x0b0b
+#define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX                                                       0
+#define mmTCP_CHAN_STEER_5_ARCT                                                                0x0b0c
+#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX                                                       0
+
+enum ta_ras_gfx_subblock {
+       /*CPC*/
+       TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
+       TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
+       TA_RAS_BLOCK__GFX_CPC_UCODE,
+       TA_RAS_BLOCK__GFX_DC_STATE_ME1,
+       TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
+       TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
+       TA_RAS_BLOCK__GFX_DC_STATE_ME2,
+       TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
+       TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
+       TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
+       /* CPF*/
+       TA_RAS_BLOCK__GFX_CPF_INDEX_START,
+       TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
+       TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
+       TA_RAS_BLOCK__GFX_CPF_TAG,
+       TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
+       /* CPG*/
+       TA_RAS_BLOCK__GFX_CPG_INDEX_START,
+       TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
+       TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
+       TA_RAS_BLOCK__GFX_CPG_TAG,
+       TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
+       /* GDS*/
+       TA_RAS_BLOCK__GFX_GDS_INDEX_START,
+       TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
+       TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
+       TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
+       TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
+       TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
+       TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
+       /* SPI*/
+       TA_RAS_BLOCK__GFX_SPI_SR_MEM,
+       /* SQ*/
+       TA_RAS_BLOCK__GFX_SQ_INDEX_START,
+       TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
+       TA_RAS_BLOCK__GFX_SQ_LDS_D,
+       TA_RAS_BLOCK__GFX_SQ_LDS_I,
+       TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
+       TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
+       /* SQC (3 ranges)*/
+       TA_RAS_BLOCK__GFX_SQC_INDEX_START,
+       /* SQC range 0*/
+       TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
+       TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
+               TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
+       TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
+       TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
+       TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
+       TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
+       TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
+       TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
+       TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
+               TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
+       /* SQC range 1*/
+       TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
+               TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
+       TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
+               TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
+       /* SQC range 2*/
+       TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
+               TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
+       TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
+       TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
+               TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
+       TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
+       /* TA*/
+       TA_RAS_BLOCK__GFX_TA_INDEX_START,
+       TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
+       TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
+       TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
+       TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
+       TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
+       TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
+       /* TCA*/
+       TA_RAS_BLOCK__GFX_TCA_INDEX_START,
+       TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
+       TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
+       TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
+       /* TCC (5 sub-ranges)*/
+       TA_RAS_BLOCK__GFX_TCC_INDEX_START,
+       /* TCC range 0*/
+       TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
+       TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
+       TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
+       TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
+       TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
+       TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
+       TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
+       TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
+       TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
+       TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
+       /* TCC range 1*/
+       TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
+       TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
+       TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
+       TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
+               TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
+       /* TCC range 2*/
+       TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
+       TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
+       TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
+       TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
+       TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
+       TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
+       TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
+       TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
+       TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
+       TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
+               TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
+       /* TCC range 3*/
+       TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
+       TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
+       TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
+       TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
+               TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
+       /* TCC range 4*/
+       TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
+       TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
+               TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
+       TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
+       TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
+               TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
+       TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
+       /* TCI*/
+       TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
+       /* TCP*/
+       TA_RAS_BLOCK__GFX_TCP_INDEX_START,
+       TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
+       TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
+       TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
+       TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
+       TA_RAS_BLOCK__GFX_TCP_DB_RAM,
+       TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
+       TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
+       TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
+       /* TD*/
+       TA_RAS_BLOCK__GFX_TD_INDEX_START,
+       TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
+       TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
+       TA_RAS_BLOCK__GFX_TD_CS_FIFO,
+       TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
+       /* EA (3 sub-ranges)*/
+       TA_RAS_BLOCK__GFX_EA_INDEX_START,
+       /* EA range 0*/
+       TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
+       TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
+       TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
+       TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
+       TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
+       TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
+       TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
+       TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
+       TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
+       TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
+       /* EA range 1*/
+       TA_RAS_BLOCK__GFX_EA_INDEX1_START,
+       TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
+       TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
+       TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
+       TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
+       TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
+       TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
+       TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
+       TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
+       /* EA range 2*/
+       TA_RAS_BLOCK__GFX_EA_INDEX2_START,
+       TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
+       TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
+       TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
+       TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
+       TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
+       TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
+       /* UTC VM L2 bank*/
+       TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
+       /* UTC VM walker*/
+       TA_RAS_BLOCK__UTC_VML2_WALKER,
+       /* UTC ATC L2 2MB cache*/
+       TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
+       /* UTC ATC L2 4KB cache*/
+       TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
+       TA_RAS_BLOCK__GFX_MAX
+};
+
+struct ras_gfx_subblock {
+       unsigned char *name;
+       int ta_subblock;
+       int hw_supported_error_type;
+       int sw_supported_error_type;
+};
+
+#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)                             \
+       [AMDGPU_RAS_BLOCK__##subblock] = {                                     \
+               #subblock,                                                     \
+               TA_RAS_BLOCK__##subblock,                                      \
+               ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)),                  \
+               (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)),                  \
+       }
+
+static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
+                            0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
+                            0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
+                            0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
+                            1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
+                            0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
+                            0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
+                            0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
+                            0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
+                            1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
+                            1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
+                            1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
+                            0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
+                            0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
+       AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
+};
+
 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
 {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
@@ -271,6 +655,18 @@ static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 };
 
+static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
+{
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
+};
+
 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 {
        mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
@@