Merge tag 'v5.3-rc3' into drm-next-5.4
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Aug 2019 18:07:28 +0000 (13:07 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Aug 2019 18:07:28 +0000 (13:07 -0500)
Linux 5.3-rc3

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1  2 
MAINTAINERS
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
drivers/gpu/drm/ttm/ttm_bo.c
include/drm/ttm/ttm_bo_driver.h

diff --combined MAINTAINERS
index 1347cc68fc11fe08d448c9c322acba0057e09074,a2c343ee3b2ca13e4cbe7257a9e4a58d69a11285..e0f9d247497362fd338ebec2958f1b646e84123f
@@@ -321,7 -321,7 +321,7 @@@ F: drivers/pnp/pnpacpi
  F:    include/linux/acpi.h
  F:    include/linux/fwnode.h
  F:    include/acpi/
- F:    Documentation/acpi/
+ F:    Documentation/firmware-guide/acpi/
  F:    Documentation/ABI/testing/sysfs-bus-acpi
  F:    Documentation/ABI/testing/configfs-acpi
  F:    drivers/pci/*acpi*
@@@ -364,7 -364,7 +364,7 @@@ F: drivers/acpi/fan.
  
  ACPI FOR ARM64 (ACPI/arm64)
  M:    Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
- M:    Hanjun Guo <hanjun.guo@linaro.org>
+ M:    Hanjun Guo <guohanjun@huawei.com>
  M:    Sudeep Holla <sudeep.holla@arm.com>
  L:    linux-acpi@vger.kernel.org
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -551,6 -551,7 +551,7 @@@ W: http://wiki.analog.com/ADXL34
  W:    http://ez.analog.com/community/linux-device-drivers
  S:    Supported
  F:    drivers/input/misc/adxl34x.c
+ F:    Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
  
  ADXL372 THREE-AXIS DIGITAL ACCELEROMETER DRIVER
  M:    Stefan Popa <stefan.popa@analog.com>
@@@ -559,7 -560,7 +560,7 @@@ S: Supporte
  F:    drivers/iio/accel/adxl372.c
  F:    drivers/iio/accel/adxl372_spi.c
  F:    drivers/iio/accel/adxl372_i2c.c
- F:    Documentation/devicetree/bindings/iio/accel/adxl372.txt
+ F:    Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml
  
  AF9013 MEDIA DRIVER
  M:    Antti Palosaari <crope@iki.fi>
@@@ -668,6 -669,13 +669,13 @@@ S:       Maintaine
  F:    Documentation/i2c/busses/i2c-ali1563
  F:    drivers/i2c/busses/i2c-ali1563.c
  
+ ALLEGRO DVT VIDEO IP CORE DRIVER
+ M:    Michael Tretter <m.tretter@pengutronix.de>
+ R:    Pengutronix Kernel Team <kernel@pengutronix.de>
+ L:    linux-media@vger.kernel.org
+ S:    Maintained
+ F:    drivers/staging/media/allegro-dvt/
  ALLWINNER SECURITY SYSTEM
  M:    Corentin Labbe <clabbe.montjoie@gmail.com>
  L:    linux-crypto@vger.kernel.org
@@@ -821,11 -829,17 +829,11 @@@ F:      drivers/iommu/amd_iommu*.[ch
  F:    include/linux/amd-iommu.h
  
  AMD KFD
 -M:    Oded Gabbay <oded.gabbay@gmail.com>
 -L:    dri-devel@lists.freedesktop.org
 -T:    git git://people.freedesktop.org/~gabbayo/linux.git
 +M:    Felix Kuehling <Felix.Kuehling@amd.com>
 +L:    amd-gfx@lists.freedesktop.org
 +T:    git git://people.freedesktop.org/~agd5f/linux
  S:    Supported
 -F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
 -F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
 -F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
 -F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
 -F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
 -F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
 -F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
 +F:    drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
  F:    drivers/gpu/drm/amd/amdkfd/
  F:    drivers/gpu/drm/amd/include/cik_structs.h
  F:    drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@@ -885,7 -899,7 +893,7 @@@ L: linux-iio@vger.kernel.or
  W:    http://ez.analog.com/community/linux-device-drivers
  S:    Supported
  F:    drivers/iio/adc/ad7124.c
- F:    Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt
+ F:    Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml
  
  ANALOG DEVICES INC AD7606 DRIVER
  M:    Stefan Popa <stefan.popa@analog.com>
@@@ -903,8 -917,17 +911,17 @@@ S:       Supporte
  F:    drivers/iio/adc/ad7768-1.c
  F:    Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.txt
  
+ ANALOG DEVICES INC AD7780 DRIVER
+ M:    Michael Hennerich <Michael.Hennerich@analog.com>
+ M:    Renato Lui Geh <renatogeh@gmail.com>
+ L:    linux-iio@vger.kernel.org
+ W:    http://ez.analog.com/community/linux-device-drivers
+ S:    Supported
+ F:    drivers/iio/adc/ad7780.c
+ F:    Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
  ANALOG DEVICES INC AD9389B DRIVER
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  S:    Maintained
  F:    drivers/media/i2c/ad9389b*
@@@ -915,6 -938,13 +932,13 @@@ S:       Supporte
  F:    drivers/mux/adgs1408.c
  F:    Documentation/devicetree/bindings/mux/adi,adgs1408.txt
  
+ ANALOG DEVICES INC ADIS DRIVER LIBRARY
+ M:    Alexandru Ardelean <alexandru.ardelean@analog.com>
+ S:    Supported
+ L:    linux-iio@vger.kernel.org
+ F:    include/linux/iio/imu/adis.h
+ F:    drivers/iio/imu/adis.c
  ANALOG DEVICES INC ADP5061 DRIVER
  M:    Stefan Popa <stefan.popa@analog.com>
  L:    linux-pm@vger.kernel.org
@@@ -936,19 -966,19 +960,19 @@@ S:      Maintaine
  F:    drivers/media/i2c/adv748x/*
  
  ANALOG DEVICES INC ADV7511 DRIVER
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  S:    Maintained
  F:    drivers/media/i2c/adv7511*
  
  ANALOG DEVICES INC ADV7604 DRIVER
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  S:    Maintained
  F:    drivers/media/i2c/adv7604*
  
  ANALOG DEVICES INC ADV7842 DRIVER
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  S:    Maintained
  F:    drivers/media/i2c/adv7842*
@@@ -1125,7 -1155,7 +1149,7 @@@ APPLIED MICRO (APM) X-GENE SOC PM
  M:    Khuong Dinh <khuong@os.amperecomputing.com>
  S:    Supported
  F:    drivers/perf/xgene_pmu.c
- F:    Documentation/perf/xgene-pmu.txt
+ F:    Documentation/admin-guide/perf/xgene-pmu.rst
  F:    Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
  
  APTINA CAMERA SENSOR PLL
@@@ -1134,6 -1164,15 +1158,15 @@@ L:    linux-media@vger.kernel.or
  S:    Maintained
  F:    drivers/media/i2c/aptina-pll.*
  
+ AQUANTIA ETHERNET DRIVER (atlantic)
+ M:    Igor Russkikh <igor.russkikh@aquantia.com>
+ L:    netdev@vger.kernel.org
+ S:    Supported
+ W:    http://www.aquantia.com
+ Q:    http://patchwork.ozlabs.org/project/netdev/list/
+ F:    drivers/net/ethernet/aquantia/atlantic/
+ F:    Documentation/networking/device_drivers/aquantia/atlantic.txt
  ARC FRAMEBUFFER DRIVER
  M:    Jaya Kumar <jayalk@intworks.biz>
  S:    Maintained
@@@ -1155,7 -1194,7 +1188,7 @@@ F:      include/uapi/linux/if_arcnet.
  
  ARM ARCHITECTED TIMER DRIVER
  M:    Mark Rutland <mark.rutland@arm.com>
- M:    Marc Zyngier <marc.zyngier@arm.com>
+ M:    Marc Zyngier <maz@kernel.org>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
  F:    arch/arm/include/asm/arch_timer.h
@@@ -1197,7 -1236,7 +1230,7 @@@ M:      James (Qian) Wang <james.qian.wang@a
  M:    Liviu Dudau <liviu.dudau@arm.com>
  L:    Mali DP Maintainers <malidp@foss.arm.com>
  S:    Supported
- T:    git git://linux-arm.org/linux-ld.git for-upstream/mali-dp
+ T:    git git://anongit.freedesktop.org/drm/drm-misc
  F:    drivers/gpu/drm/arm/display/include/
  F:    drivers/gpu/drm/arm/display/komeda/
  F:    Documentation/devicetree/bindings/display/arm,komeda.txt
@@@ -1208,7 -1247,7 +1241,7 @@@ M:      Liviu Dudau <liviu.dudau@arm.com
  M:    Brian Starkey <brian.starkey@arm.com>
  L:    Mali DP Maintainers <malidp@foss.arm.com>
  S:    Supported
- T:    git git://linux-arm.org/linux-ld.git for-upstream/mali-dp
+ T:    git git://anongit.freedesktop.org/drm/drm-misc
  F:    drivers/gpu/drm/arm/
  F:    Documentation/devicetree/bindings/display/arm,malidp.txt
  F:    Documentation/gpu/afbc.rst
@@@ -1225,11 -1264,11 +1258,11 @@@ F:   include/uapi/drm/panfrost_drm.
  ARM MFM AND FLOPPY DRIVERS
  M:    Ian Molton <spyro@f2s.com>
  S:    Maintained
- F:    arch/arm/lib/floppydma.S
+ F:    arch/arm/mach-rpc/floppydma.S
  F:    arch/arm/include/asm/floppy.h
  
  ARM PMU PROFILING AND DEBUGGING
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  M:    Mark Rutland <mark.rutland@arm.com>
  S:    Maintained
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -1284,7 -1323,7 +1317,7 @@@ ARM PRIMECELL SSP PL022 SPI DRIVE
  M:    Linus Walleij <linus.walleij@linaro.org>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
- F:    Documentation/devicetree/bindings/spi/spi_pl022.txt
+ F:    Documentation/devicetree/bindings/spi/spi-pl022.yaml
  F:    drivers/spi/spi-pl022.c
  
  ARM PRIMECELL UART PL010 AND PL011 DRIVERS
@@@ -1300,8 -1339,14 +1333,14 @@@ S:    Maintaine
  F:    Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt
  F:    drivers/irqchip/irq-vic.c
  
+ AMAZON ANNAPURNA LABS FIC DRIVER
+ M:    Talel Shenhar <talel@amazon.com>
+ S:    Maintained
+ F:    Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt
+ F:    drivers/irqchip/irq-al-fic.c
  ARM SMMU DRIVERS
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  R:    Robin Murphy <robin.murphy@arm.com>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
@@@ -1818,6 -1863,7 +1857,7 @@@ F:      arch/arm/mach-orion5x
  F:    arch/arm/plat-orion/
  F:    arch/arm/boot/dts/dove*
  F:    arch/arm/boot/dts/orion5x*
+ T:    git git://git.infradead.org/linux-mvebu.git
  
  ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K SOC support
  M:    Jason Cooper <jason@lakedaemon.net>
@@@ -1838,6 -1884,7 +1878,7 @@@ F:      drivers/irqchip/irq-armada-370-xp.
  F:    drivers/irqchip/irq-mvebu-*
  F:    drivers/pinctrl/mvebu/
  F:    drivers/rtc/rtc-armada38x.c
+ T:    git git://git.infradead.org/linux-mvebu.git
  
  ARM/Mediatek RTC DRIVER
  M:    Eddie Huang <eddie.huang@mediatek.com>
@@@ -2044,7 -2091,6 +2085,6 @@@ S:      Maintaine
  
  ARM/QUALCOMM SUPPORT
  M:    Andy Gross <agross@kernel.org>
- M:    David Brown <david.brown@linaro.org>
  L:    linux-arm-msm@vger.kernel.org
  S:    Maintained
  F:    Documentation/devicetree/bindings/soc/qcom/
@@@ -2066,7 -2112,7 +2106,7 @@@ F:      drivers/i2c/busses/i2c-qup.
  F:    drivers/i2c/busses/i2c-qcom-geni.c
  F:    drivers/mfd/ssbi.c
  F:    drivers/mmc/host/mmci_qcom*
- F:    drivers/mmc/host/sdhci_msm.c
+ F:    drivers/mmc/host/sdhci-msm.c
  F:    drivers/pci/controller/dwc/pcie-qcom.c
  F:    drivers/phy/qualcomm/
  F:    drivers/power/*/msm*
@@@ -2079,7 -2125,7 +2119,7 @@@ F:      drivers/tty/serial/msm_serial.
  F:    drivers/usb/dwc3/dwc3-qcom.c
  F:    include/dt-bindings/*/qcom*
  F:    include/linux/*/qcom*
- T:    git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
  
  ARM/RADISYS ENP2611 MACHINE SUPPORT
  M:    Lennert Buytenhek <kernel@wantstofly.org>
@@@ -2095,7 -2141,7 +2135,7 @@@ F:      arch/arm/boot/dts/rda8810pl-
  F:    drivers/clocksource/timer-rda.c
  F:    drivers/irqchip/irq-rda-intc.c
  F:    drivers/tty/serial/rda-uart.c
- F:    Documentation/devicetree/bindings/arm/rda.txt
+ F:    Documentation/devicetree/bindings/arm/rda.yaml
  F:    Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
  F:    Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt
  F:    Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt
@@@ -2109,10 -2155,12 +2149,12 @@@ F:   Documentation/devicetree/bindings/ar
  
  ARM/RENESAS ARM64 ARCHITECTURE
  M:    Simon Horman <horms@verge.net.au>
+ M:    Geert Uytterhoeven <geert+renesas@glider.be>
  M:    Magnus Damm <magnus.damm@gmail.com>
  L:    linux-renesas-soc@vger.kernel.org
  Q:    http://patchwork.kernel.org/project/linux-renesas-soc/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
  S:    Supported
  F:    arch/arm64/boot/dts/renesas/
  F:    Documentation/devicetree/bindings/arm/renesas.yaml
@@@ -2173,7 -2221,7 +2215,7 @@@ F:      drivers/*/*s3c64xx
  F:    drivers/*/*s5pv210*
  F:    drivers/memory/samsung/*
  F:    drivers/soc/samsung/*
- F:    Documentation/arm/Samsung/
+ F:    Documentation/arm/samsung/
  F:    Documentation/devicetree/bindings/arm/samsung/
  F:    Documentation/devicetree/bindings/sram/samsung-sram.txt
  F:    Documentation/devicetree/bindings/power/pd-samsung.txt
@@@ -2223,10 -2271,12 +2265,12 @@@ F:   drivers/media/platform/s5p-mfc
  
  ARM/SHMOBILE ARM ARCHITECTURE
  M:    Simon Horman <horms@verge.net.au>
+ M:    Geert Uytterhoeven <geert+renesas@glider.be>
  M:    Magnus Damm <magnus.damm@gmail.com>
  L:    linux-renesas-soc@vger.kernel.org
  Q:    http://patchwork.kernel.org/project/linux-renesas-soc/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
  S:    Supported
  F:    arch/arm/boot/dts/emev2*
  F:    arch/arm/boot/dts/gr-peach*
@@@ -2338,7 -2388,7 +2382,7 @@@ L:      linux-arm-kernel@lists.infradead.or
  S:    Maintained
  
  ARM/TEGRA HDMI CEC SUBSYSTEM SUPPORT
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-tegra@vger.kernel.org
  L:    linux-media@vger.kernel.org
  S:    Maintained
@@@ -2544,7 -2594,7 +2588,7 @@@ F:      drivers/i2c/busses/i2c-xiic.
  
  ARM64 PORT (AARCH64 ARCHITECTURE)
  M:    Catalin Marinas <catalin.marinas@arm.com>
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
  S:    Maintained
@@@ -2580,6 -2630,15 +2624,15 @@@ S:    Maintaine
  F:    Documentation/hwmon/asc7621.rst
  F:    drivers/hwmon/asc7621.c
  
+ ASPEED PINCTRL DRIVERS
+ M:    Andrew Jeffery <andrew@aj.id.au>
+ L:    linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
+ L:    openbmc@lists.ozlabs.org (moderated for non-subscribers)
+ L:    linux-gpio@vger.kernel.org
+ S:    Maintained
+ F:    drivers/pinctrl/aspeed/
+ F:    Documentation/devicetree/bindings/pinctrl/aspeed,*
  ASPEED VIDEO ENGINE DRIVER
  M:    Eddie James <eajames@linux.ibm.com>
  L:    linux-media@vger.kernel.org
@@@ -2635,7 -2694,7 +2688,7 @@@ ATA OVER ETHERNET (AOE) DRIVE
  M:    "Justin Sanders" <justin@coraid.com>
  W:    http://www.openaoe.org/
  S:    Supported
- F:    Documentation/aoe/
+ F:    Documentation/admin-guide/aoe/
  F:    drivers/block/aoe/
  
  ATHEROS 71XX/9XXX GPIO DRIVER
@@@ -2728,7 -2787,7 +2781,7 @@@ S:      Maintaine
  F:    drivers/net/wireless/atmel/atmel*
  
  ATOMIC INFRASTRUCTURE
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  M:    Peter Zijlstra <peterz@infradead.org>
  R:    Boqun Feng <boqun.feng@gmail.com>
  L:    linux-kernel@vger.kernel.org
@@@ -2914,7 -2973,7 +2967,7 @@@ M:      Jens Axboe <axboe@kernel.dk
  L:    linux-block@vger.kernel.org
  S:    Maintained
  F:    block/bfq-*
- F:    Documentation/block/bfq-iosched.txt
+ F:    Documentation/block/bfq-iosched.rst
  
  BFS FILE SYSTEM
  M:    "Tigran A. Aivazian" <aivazian.tigran@gmail.com>
@@@ -3054,9 -3113,9 +3107,9 @@@ S:      Maintaine
  F:    arch/riscv/net/
  
  BPF JIT for S390
+ M:    Ilya Leoshkevich <iii@linux.ibm.com>
  M:    Heiko Carstens <heiko.carstens@de.ibm.com>
  M:    Vasily Gorbik <gor@linux.ibm.com>
- M:    Christian Borntraeger <borntraeger@de.ibm.com>
  L:    netdev@vger.kernel.org
  L:    bpf@vger.kernel.org
  S:    Maintained
@@@ -3115,7 -3174,8 +3168,8 @@@ F:      arch/arm/mach-bcm
  
  BROADCOM BCM2835 ARM ARCHITECTURE
  M:    Eric Anholt <eric@anholt.net>
- M:    Stefan Wahren <stefan.wahren@i2se.com>
+ M:    Stefan Wahren <wahrenst@gmx.net>
+ L:    bcm-kernel-feedback-list@broadcom.com
  L:    linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  T:    git git://github.com/anholt/linux
@@@ -3145,6 -3205,7 +3199,7 @@@ F:      arch/arm/boot/dts/bcm953012
  
  BROADCOM BCM53573 ARM ARCHITECTURE
  M:    Rafał Miłecki <rafal@milecki.pl>
+ L:    bcm-kernel-feedback-list@broadcom.com
  L:    linux-arm-kernel@lists.infradead.org
  S:    Maintained
  F:    arch/arm/boot/dts/bcm53573*
@@@ -3671,7 -3732,7 +3726,7 @@@ F:      drivers/crypto/ccree
  W:    https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family
  
  CEC FRAMEWORK
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  W:    http://linuxtv.org
@@@ -3688,7 -3749,7 +3743,7 @@@ F:      Documentation/devicetree/bindings/me
  F:    Documentation/ABI/testing/debugfs-cec-error-inj
  
  CEC GPIO DRIVER
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  W:    http://linuxtv.org
@@@ -3709,7 -3770,7 +3764,7 @@@ F:      arch/powerpc/platforms/cell
  
  CEPH COMMON CODE (LIBCEPH)
  M:    Ilya Dryomov <idryomov@gmail.com>
- M:    "Yan, Zheng" <zyan@redhat.com>
+ M:    Jeff Layton <jlayton@kernel.org>
  M:    Sage Weil <sage@redhat.com>
  L:    ceph-devel@vger.kernel.org
  W:    http://ceph.com/
@@@ -3721,7 -3782,7 +3776,7 @@@ F:      include/linux/ceph
  F:    include/linux/crush/
  
  CEPH DISTRIBUTED FILE SYSTEM CLIENT (CEPH)
- M:    "Yan, Zheng" <zyan@redhat.com>
+ M:    Jeff Layton <jlayton@kernel.org>
  M:    Sage Weil <sage@redhat.com>
  M:    Ilya Dryomov <idryomov@gmail.com>
  L:    ceph-devel@vger.kernel.org
@@@ -3745,7 -3806,7 +3800,7 @@@ F:      scripts/extract-cert.
  CERTIFIED WIRELESS USB (WUSB) SUBSYSTEM:
  L:    linux-usb@vger.kernel.org
  S:    Orphan
- F:    Documentation/usb/WUSB-Design-overview.txt
+ F:    Documentation/usb/wusb-design-overview.rst
  F:    Documentation/usb/wusb-cbaf
  F:    drivers/usb/host/hwa-hc.c
  F:    drivers/usb/host/whci/
@@@ -3880,7 -3941,7 +3935,7 @@@ F:      Documentation/devicetree/bindings/hw
  F:    Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt
  F:    Documentation/devicetree/bindings/regulator/cirrus,lochnagar.txt
  F:    Documentation/devicetree/bindings/sound/cirrus,lochnagar.txt
- F:    Documentation/hwmon/lochnagar
+ F:    Documentation/hwmon/lochnagar.rst
  
  CISCO FCOE HBA DRIVER
  M:    Satish Kharat <satishkh@cisco.com>
@@@ -3921,19 -3982,32 +3976,32 @@@ W:   https://github.com/CirrusLogic/linux
  S:    Supported
  F:    Documentation/devicetree/bindings/mfd/madera.txt
  F:    Documentation/devicetree/bindings/pinctrl/cirrus,madera-pinctrl.txt
+ F:    Documentation/devicetree/bindings/sound/madera.txt
+ F:    include/dt-bindings/sound/madera*
  F:    include/linux/irqchip/irq-madera*
  F:    include/linux/mfd/madera/*
+ F:    include/sound/madera*
  F:    drivers/gpio/gpio-madera*
  F:    drivers/irqchip/irq-madera*
  F:    drivers/mfd/madera*
  F:    drivers/mfd/cs47l*
  F:    drivers/pinctrl/cirrus/*
+ F:    sound/soc/codecs/cs47l*
+ F:    sound/soc/codecs/madera*
  
  CLANG-FORMAT FILE
  M:    Miguel Ojeda <miguel.ojeda.sandonis@gmail.com>
  S:    Maintained
  F:    .clang-format
  
+ CLANG/LLVM BUILD SUPPORT
+ L:    clang-built-linux@googlegroups.com
+ W:    https://clangbuiltlinux.github.io/
+ B:    https://github.com/ClangBuiltLinux/linux/issues
+ C:    irc://chat.freenode.net/clangbuiltlinux
+ S:    Supported
+ K:    \b(?i:clang|llvm)\b
  CLEANCACHE API
  M:    Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
  L:    linux-kernel@vger.kernel.org
@@@ -3964,7 -4038,7 +4032,7 @@@ S:      Supporte
  F:    drivers/platform/x86/classmate-laptop.c
  
  COBALT MEDIA DRIVER
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  W:    https://linuxtv.org
@@@ -4089,7 -4163,7 +4157,7 @@@ L:      cgroups@vger.kernel.or
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup.git
  S:    Maintained
  F:    Documentation/admin-guide/cgroup-v2.rst
- F:    Documentation/cgroup-v1/
+ F:    Documentation/admin-guide/cgroup-v1/
  F:    include/linux/cgroup*
  F:    kernel/cgroup/
  
@@@ -4100,7 -4174,7 +4168,7 @@@ W:      http://www.bullopensource.org/cpuset
  W:    http://oss.sgi.com/projects/cpusets/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup.git
  S:    Maintained
- F:    Documentation/cgroup-v1/cpusets.txt
+ F:    Documentation/admin-guide/cgroup-v1/cpusets.rst
  F:    include/linux/cpuset.h
  F:    kernel/cgroup/cpuset.c
  
@@@ -4114,6 -4188,19 +4182,19 @@@ S:    Maintaine
  F:    mm/memcontrol.c
  F:    mm/swap_cgroup.c
  
+ CONTROL GROUP - BLOCK IO CONTROLLER (BLKIO)
+ M:    Tejun Heo <tj@kernel.org>
+ M:    Jens Axboe <axboe@kernel.dk>
+ L:    cgroups@vger.kernel.org
+ L:    linux-block@vger.kernel.org
+ T:    git git://git.kernel.dk/linux-block
+ F:    Documentation/admin-guide/cgroup-v1/blkio-controller.rst
+ F:    block/blk-cgroup.c
+ F:    include/linux/blk-cgroup.h
+ F:    block/blk-throttle.c
+ F:    block/blk-iolatency.c
+ F:    block/bfq-cgroup.c
  CORETEMP HARDWARE MONITORING DRIVER
  M:    Fenghua Yu <fenghua.yu@intel.com>
  L:    linux-hwmon@vger.kernel.org
@@@ -4235,6 -4322,7 +4316,7 @@@ F:      crypto
  F:    drivers/crypto/
  F:    include/crypto/
  F:    include/linux/crypto*
+ F:    lib/crypto/
  
  CRYPTOGRAPHIC RANDOM NUMBER GENERATOR
  M:    Neil Horman <nhorman@tuxdriver.com>
@@@ -4385,7 -4473,7 +4467,7 @@@ F:      arch/powerpc/platforms/powernv/pci-c
  F:    drivers/misc/cxl/
  F:    include/misc/cxl*
  F:    include/uapi/misc/cxl.h
- F:    Documentation/powerpc/cxl.txt
+ F:    Documentation/powerpc/cxl.rst
  F:    Documentation/ABI/testing/sysfs-class-cxl
  
  CXLFLASH (IBM Coherent Accelerator Processor Interface CAPI Flash) SCSI DRIVER
@@@ -4396,7 -4484,7 +4478,7 @@@ L:      linux-scsi@vger.kernel.or
  S:    Supported
  F:    drivers/scsi/cxlflash/
  F:    include/uapi/scsi/cxlflash_ioctl.h
- F:    Documentation/powerpc/cxlflash.txt
+ F:    Documentation/powerpc/cxlflash.rst
  
  CYBERPRO FB DRIVER
  M:    Russell King <linux@armlinux.org.uk>
@@@ -4572,7 -4660,7 +4654,7 @@@ DELL SYSTEMS MANAGEMENT BASE DRIVER (dc
  M:    Stuart Hayes <stuart.w.hayes@gmail.com>
  L:    platform-driver-x86@vger.kernel.org
  S:    Maintained
- F:    Documentation/dcdbas.txt
+ F:    Documentation/driver-api/dcdbas.rst
  F:    drivers/platform/x86/dcdbas.*
  
  DELL WMI NOTIFICATIONS DRIVER
@@@ -4600,6 -4688,13 +4682,13 @@@ L:    linux-mtd@lists.infradead.or
  S:    Supported
  F:    drivers/mtd/nand/raw/denali*
  
+ DESIGNWARE EDMA CORE IP DRIVER
+ M:    Gustavo Pimentel <gustavo.pimentel@synopsys.com>
+ L:    dmaengine@vger.kernel.org
+ S:    Maintained
+ F:    drivers/dma/dw-edma/
+ F:    include/linux/dma/edma.h
  DESIGNWARE USB2 DRD IP DRIVER
  M:    Minas Harutyunyan <hminas@synopsys.com>
  L:    linux-usb@vger.kernel.org
@@@ -4665,7 -4760,7 +4754,7 @@@ Q:      http://patchwork.kernel.org/project/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm.git
  T:    quilt http://people.redhat.com/agk/patches/linux/editing/
  S:    Maintained
- F:    Documentation/device-mapper/
+ F:    Documentation/admin-guide/device-mapper/
  F:    drivers/md/Makefile
  F:    drivers/md/Kconfig
  F:    drivers/md/dm*
@@@ -4691,6 -4786,7 +4780,7 @@@ F:      Documentation/devicetree/bindings/mf
  F:    Documentation/devicetree/bindings/input/da90??-onkey.txt
  F:    Documentation/devicetree/bindings/thermal/da90??-thermal.txt
  F:    Documentation/devicetree/bindings/regulator/da92*.txt
+ F:    Documentation/devicetree/bindings/regulator/slg51000.txt
  F:    Documentation/devicetree/bindings/watchdog/da90??-wdt.txt
  F:    Documentation/devicetree/bindings/sound/da[79]*.txt
  F:    drivers/gpio/gpio-da90??.c
@@@ -4706,6 -4802,7 +4796,7 @@@ F:      drivers/power/supply/da9052-battery.
  F:    drivers/power/supply/da91??-*.c
  F:    drivers/regulator/da903x.c
  F:    drivers/regulator/da9???-regulator.[ch]
+ F:    drivers/regulator/slg51000-regulator.[ch]
  F:    drivers/thermal/da90??-thermal.c
  F:    drivers/rtc/rtc-da90??.c
  F:    drivers/video/backlight/da90??_bl.c
@@@ -4783,7 -4880,7 +4874,7 @@@ S:      Maintaine
  W:    http://plugable.com/category/projects/udlfb/
  F:    drivers/video/fbdev/udlfb.c
  F:    include/video/udlfb.h
- F:    Documentation/fb/udlfb.txt
+ F:    Documentation/fb/udlfb.rst
  
  DISTRIBUTED LOCK MANAGER (DLM)
  M:    Christine Caulfield <ccaulfie@redhat.com>
@@@ -4856,7 -4953,7 +4947,7 @@@ S:      Maintaine
  F:    Documentation/
  F:    scripts/kernel-doc
  X:    Documentation/ABI/
- X:    Documentation/acpi/
+ X:    Documentation/firmware-guide/acpi/
  X:    Documentation/devicetree/
  X:    Documentation/i2c/
  X:    Documentation/media/
@@@ -4916,13 -5013,6 +5007,6 @@@ L:     linux-kernel@vger.kernel.or
  S:    Maintained
  F:    drivers/staging/fsl-dpaa2/ethsw
  
- DPAA2 PTP CLOCK DRIVER
- M:    Yangbo Lu <yangbo.lu@nxp.com>
- L:    netdev@vger.kernel.org
- S:    Maintained
- F:    drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp*
- F:    drivers/net/ethernet/freescale/dpaa2/dprtc*
  DPT_I2O SCSI RAID DRIVER
  M:    Adaptec OEM Raid Solutions <aacraid@microsemi.com>
  L:    linux-scsi@vger.kernel.org
@@@ -4941,7 -5031,7 +5025,7 @@@ T:      git git://git.linbit.com/drbd-8.4.gi
  S:    Supported
  F:    drivers/block/drbd/
  F:    lib/lru_cache.c
- F:    Documentation/blockdev/drbd/
+ F:    Documentation/admin-guide/blockdev/
  
  DRIVER CORE, KOBJECTS, DEBUGFS AND SYSFS
  M:    Greg Kroah-Hartman <gregkh@linuxfoundation.org>
@@@ -5185,7 -5275,6 +5269,6 @@@ T:      git git://people.freedesktop.org/~th
  S:    Supported
  F:    drivers/gpu/drm/vmwgfx/
  F:    include/uapi/drm/vmwgfx_drm.h
- F:    mm/as_dirty_helpers.c
  
  DRM DRIVERS
  M:    David Airlie <airlied@linux.ie>
@@@ -5602,7 -5691,8 +5685,8 @@@ F:      include/linux/dynamic_debug.
  DYNAMIC INTERRUPT MODERATION
  M:    Tal Gilboa <talgi@mellanox.com>
  S:    Maintained
- F:    include/linux/net_dim.h
+ F:    include/linux/dim.h
+ F:    lib/dim/
  
  DZ DECSTATION DZ11 SERIAL DRIVER
  M:    "Maciej W. Rozycki" <macro@linux-mips.org>
@@@ -5811,6 -5901,12 +5895,12 @@@ L:    linux-edac@vger.kernel.or
  S:    Maintained
  F:    drivers/edac/sb_edac.c
  
+ EDAC-SIFIVE
+ M:    Yash Shah <yash.shah@sifive.com>
+ L:    linux-edac@vger.kernel.org
+ S:    Supported
+ F:    drivers/edac/sifive_edac.c
  EDAC-SKYLAKE
  M:    Tony Luck <tony.luck@intel.com>
  L:    linux-edac@vger.kernel.org
@@@ -5970,6 -6066,7 +6060,7 @@@ M:      Heiner Kallweit <hkallweit1@gmail.co
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    Documentation/ABI/testing/sysfs-bus-mdio
+ F:    Documentation/devicetree/bindings/net/ethernet-phy.yaml
  F:    Documentation/devicetree/bindings/net/mdio*
  F:    Documentation/networking/phy.rst
  F:    drivers/net/phy/
@@@ -6015,7 -6112,7 +6106,7 @@@ M:      Ard Biesheuvel <ard.biesheuvel@linar
  L:    linux-efi@vger.kernel.org
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git
  S:    Maintained
- F:    Documentation/efi-stub.txt
+ F:    Documentation/admin-guide/efi-stub.rst
  F:    arch/*/kernel/efi.c
  F:    arch/x86/boot/compressed/eboot.[ch]
  F:    arch/*/include/asm/efi.h
@@@ -6034,7 -6131,7 +6125,7 @@@ S:      Maintaine
  F:    drivers/extcon/
  F:    include/linux/extcon/
  F:    include/linux/extcon.h
- F:    Documentation/extcon/
+ F:    Documentation/firmware-guide/acpi/extcon-intel-int3496.rst
  F:    Documentation/devicetree/bindings/extcon/
  
  EXYNOS DP DRIVER
@@@ -6220,10 -6317,18 +6311,18 @@@ M:   Philip Kelleher <pjk1939@linux.ibm.c
  S:    Maintained
  F:    drivers/block/rsxx/
  
+ FLEXTIMER FTM-QUADDEC DRIVER
+ M:    Patrick Havelange <patrick.havelange@essensium.com>
+ L:    linux-iio@vger.kernel.org
+ S:    Maintained
+ F:    Documentation/ABI/testing/sysfs-bus-counter-ftm-quadddec
+ F:    Documentation/devicetree/bindings/counter/ftm-quaddec.txt
+ F:    drivers/counter/ftm-quaddec.c
  FLOPPY DRIVER
- M:    Jiri Kosina <jikos@kernel.org>
- T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/floppy.git
- S:    Odd fixes
+ M:    Denis Efremov <efremov@linux.com>
+ S:    Odd Fixes
+ L:    linux-block@vger.kernel.org
  F:    drivers/block/floppy.c
  
  FMC SUBSYSTEM
@@@ -6236,7 -6341,6 +6335,6 @@@ F:      include/linux/ipmi-fru.
  K:    fmc_d.*register
  
  FPGA MANAGER FRAMEWORK
- M:    Alan Tull <atull@kernel.org>
  M:    Moritz Fischer <mdf@kernel.org>
  L:    linux-fpga@vger.kernel.org
  S:    Maintained
@@@ -6253,7 -6357,7 +6351,7 @@@ FPGA DFL DRIVER
  M:    Wu Hao <hao.wu@intel.com>
  L:    linux-fpga@vger.kernel.org
  S:    Maintained
- F:    Documentation/fpga/dfl.txt
+ F:    Documentation/fpga/dfl.rst
  F:    include/uapi/linux/fpga-dfl.h
  F:    drivers/fpga/dfl*
  
@@@ -6330,6 -6434,13 +6428,13 @@@ L:    linux-i2c@vger.kernel.or
  S:    Maintained
  F:    drivers/i2c/busses/i2c-cpm.c
  
+ FREESCALE IMX DDR PMU DRIVER
+ M:    Frank Li <Frank.li@nxp.com>
+ L:    linux-arm-kernel@lists.infradead.org
+ S:    Maintained
+ F:    drivers/perf/fsl_imx8_ddr_perf.c
+ F:    Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
  FREESCALE IMX LPI2C DRIVER
  M:    Dong Aisheng <aisheng.dong@nxp.com>
  L:    linux-i2c@vger.kernel.org
@@@ -6373,6 -6484,8 +6478,8 @@@ FREESCALE QORIQ PTP CLOCK DRIVE
  M:    Yangbo Lu <yangbo.lu@nxp.com>
  L:    netdev@vger.kernel.org
  S:    Maintained
+ F:    drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp*
+ F:    drivers/net/ethernet/freescale/dpaa2/dprtc*
  F:    drivers/net/ethernet/freescale/enetc/enetc_ptp.c
  F:    drivers/ptp/ptp_qoriq.c
  F:    drivers/ptp/ptp_qoriq_debugfs.c
@@@ -6418,6 -6531,7 +6525,7 @@@ M:      Li Yang <leoyang.li@nxp.com
  L:    linuxppc-dev@lists.ozlabs.org
  L:    linux-arm-kernel@lists.infradead.org
  S:    Maintained
+ F:    Documentation/devicetree/bindings/misc/fsl,dpaa2-console.txt
  F:    Documentation/devicetree/bindings/soc/fsl/
  F:    drivers/soc/fsl/
  F:    include/linux/fsl/
@@@ -6460,7 -6574,7 +6568,7 @@@ M:      "Rafael J. Wysocki" <rjw@rjwysocki.n
  M:    Pavel Machek <pavel@ucw.cz>
  L:    linux-pm@vger.kernel.org
  S:    Supported
- F:    Documentation/power/freezing-of-tasks.txt
+ F:    Documentation/power/freezing-of-tasks.rst
  F:    include/linux/freezer.h
  F:    kernel/freezer.c
  
@@@ -6491,6 -6605,19 +6599,19 @@@ F:    fs/crypto
  F:    include/linux/fscrypt*.h
  F:    Documentation/filesystems/fscrypt.rst
  
+ FSI SUBSYSTEM
+ M:    Jeremy Kerr <jk@ozlabs.org>
+ M:    Joel Stanley <joel@jms.id.au>
+ R:    Alistar Popple <alistair@popple.id.au>
+ R:    Eddie James <eajames@linux.ibm.com>
+ L:    linux-fsi@lists.ozlabs.org
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/joel/fsi.git
+ Q:    http://patchwork.ozlabs.org/project/linux-fsi/list/
+ S:    Supported
+ F:    drivers/fsi/
+ F:    include/linux/fsi*.h
+ F:    include/trace/events/fsi*.h
  FSI-ATTACHED I2C DRIVER
  M:    Eddie James <eajames@linux.ibm.com>
  L:    linux-i2c@vger.kernel.org
@@@ -6561,7 -6688,7 +6682,7 @@@ S:      Maintaine
  F:    scripts/gcc-plugins/
  F:    scripts/gcc-plugin.sh
  F:    scripts/Makefile.gcc-plugins
- F:    Documentation/gcc-plugins.txt
+ F:    Documentation/core-api/gcc-plugins.rst
  
  GASKET DRIVER FRAMEWORK
  M:    Rob Springer <rspringer@google.com>
@@@ -6667,6 -6794,18 +6788,18 @@@ L:    kvm@vger.kernel.or
  S:    Supported
  F:    drivers/uio/uio_pci_generic.c
  
+ GENERIC VDSO LIBRARY:
+ M:    Andy Lutomirski <luto@kernel.org>
+ M:    Thomas Gleixner <tglx@linutronix.de>
+ M:    Vincenzo Frascino <vincenzo.frascino@arm.com>
+ L:    linux-kernel@vger.kernel.org
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git timers/vdso
+ S:    Maintained
+ F:    lib/vdso/
+ F:    kernel/time/vsyscall.c
+ F:    include/vdso/
+ F:    include/asm-generic/vdso/vsyscall.h
  GENWQE (IBM Generic Workqueue Card)
  M:    Frank Haverkamp <haver@linux.ibm.com>
  S:    Supported
@@@ -6693,9 -6832,7 +6826,7 @@@ M:      Paul Bolle <pebolle@tiscali.nl
  L:    gigaset307x-common@lists.sourceforge.net
  W:    http://gigaset307x.sourceforge.net/
  S:    Odd Fixes
- F:    Documentation/isdn/README.gigaset
- F:    drivers/isdn/gigaset/
- F:    include/uapi/linux/gigaset_dev.h
+ F:    drivers/staging/isdn/gigaset/
  
  GNSS SUBSYSTEM
  M:    Johan Hovold <johan@kernel.org>
@@@ -6707,7 -6844,7 +6838,7 @@@ F:      drivers/gnss
  F:    include/linux/gnss.h
  
  GO7007 MPEG CODEC
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  S:    Maintained
  F:    drivers/media/usb/go7007/
@@@ -6718,6 -6855,15 +6849,15 @@@ L:    linux-input@vger.kernel.or
  S:    Maintained
  F:    drivers/input/touchscreen/goodix.c
  
+ GOOGLE ETHERNET DRIVERS
+ M:    Catherine Sullivan <csully@google.com>
+ R:    Sagi Shahar <sagis@google.com>
+ R:    Jon Olson <jonolson@google.com>
+ L:    netdev@vger.kernel.org
+ S:    Supported
+ F:    Documentation/networking/device_drivers/google/gve.rst
+ F:    drivers/net/ethernet/google
  GPD POCKET FAN DRIVER
  M:    Hans de Goede <hdegoede@redhat.com>
  L:    platform-driver-x86@vger.kernel.org
@@@ -6754,7 -6900,7 +6894,7 @@@ T:      git git://git.kernel.org/pub/scm/lin
  S:    Maintained
  F:    Documentation/devicetree/bindings/gpio/
  F:    Documentation/driver-api/gpio/
- F:    Documentation/gpio/
+ F:    Documentation/admin-guide/gpio/
  F:    Documentation/ABI/testing/gpio-cdev
  F:    Documentation/ABI/obsolete/sysfs-gpio
  F:    drivers/gpio/
@@@ -6975,7 -7121,7 +7115,7 @@@ M:      Herbert Xu <herbert@gondor.apana.org
  L:    linux-crypto@vger.kernel.org
  S:    Odd fixes
  F:    Documentation/devicetree/bindings/rng/
- F:    Documentation/hw_random.txt
+ F:    Documentation/admin-guide/hw_random.rst
  F:    drivers/char/hw_random/
  F:    include/linux/hw_random.h
  
@@@ -7011,7 -7157,7 +7151,7 @@@ F:      drivers/media/usb/hdpvr
  HEWLETT PACKARD ENTERPRISE ILO NMI WATCHDOG DRIVER
  M:    Jerry Hoemann <jerry.hoemann@hpe.com>
  S:    Supported
- F:    Documentation/watchdog/hpwdt.txt
+ F:    Documentation/watchdog/hpwdt.rst
  F:    drivers/watchdog/hpwdt.c
  
  HEWLETT-PACKARD SMART ARRAY RAID DRIVER (hpsa)
@@@ -7149,7 -7295,7 +7289,7 @@@ M:      Shaokun Zhang <zhangshaokun@hisilico
  W:    http://www.hisilicon.com
  S:    Supported
  F:    drivers/perf/hisilicon
- F:    Documentation/perf/hisi-pmu.txt
+ F:    Documentation/admin-guide/perf/hisi-pmu.rst
  
  HISILICON ROCE DRIVER
  M:    Lijun Ou <oulijun@huawei.com>
@@@ -7194,7 -7340,7 +7334,7 @@@ F:      drivers/net/ethernet/hp/hp100.
  HPET: High Precision Event Timers driver
  M:    Clemens Ladisch <clemens@ladisch.de>
  S:    Maintained
- F:    Documentation/timers/hpet.txt
+ F:    Documentation/timers/hpet.rst
  F:    drivers/char/hpet.c
  F:    include/linux/hpet.h
  F:    include/uapi/linux/hpet.h
@@@ -7304,6 -7450,7 +7444,7 @@@ F:      arch/x86/include/asm/trace/hyperv.
  F:    arch/x86/include/asm/hyperv-tlfs.h
  F:    arch/x86/kernel/cpu/mshyperv.c
  F:    arch/x86/hyperv
+ F:    drivers/clocksource/hyperv_timer.c
  F:    drivers/hid/hid-hyperv.c
  F:    drivers/hv/
  F:    drivers/input/serio/hyperv-keyboard.c
@@@ -7314,11 -7461,21 +7455,21 @@@ F:   drivers/uio/uio_hv_generic.
  F:    drivers/video/fbdev/hyperv_fb.c
  F:    drivers/iommu/hyperv_iommu.c
  F:    net/vmw_vsock/hyperv_transport.c
+ F:    include/clocksource/hyperv_timer.h
  F:    include/linux/hyperv.h
  F:    include/uapi/linux/hyperv.h
+ F:    include/asm-generic/mshyperv.h
  F:    tools/hv/
  F:    Documentation/ABI/stable/sysfs-bus-vmbus
  
+ HYPERBUS SUPPORT
+ M:    Vignesh Raghavendra <vigneshr@ti.com>
+ S:    Supported
+ F:    drivers/mtd/hyperbus/
+ F:    include/linux/mtd/hyperbus.h
+ F:    Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt
+ F:    Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt
  HYPERVISOR VIRTUAL CONSOLE DRIVER
  L:    linuxppc-dev@lists.ozlabs.org
  S:    Odd Fixes
@@@ -7612,7 -7769,7 +7763,7 @@@ IDE/ATAPI DRIVER
  M:    Borislav Petkov <bp@alien8.de>
  L:    linux-ide@vger.kernel.org
  S:    Maintained
- F:    Documentation/cdrom/ide-cd
+ F:    Documentation/cdrom/ide-cd.rst
  F:    drivers/ide/ide-cd*
  
  IDEAPAD LAPTOP EXTRAS DRIVER
@@@ -7775,6 -7932,12 +7926,12 @@@ W:    http://industrypack.sourceforge.ne
  S:    Maintained
  F:    drivers/ipack/
  
+ INFINEON DPS310 Driver
+ M:    Eddie James <eajames@linux.ibm.com>
+ L:    linux-iio@vger.kernel.org
+ F:    drivers/iio/pressure/dps310.c
+ S:    Maintained
  INFINIBAND SUBSYSTEM
  M:    Doug Ledford <dledford@redhat.com>
  M:    Jason Gunthorpe <jgg@mellanox.com>
@@@ -7803,7 -7966,34 +7960,34 @@@ INGENIC JZ4780 NAND DRIVE
  M:    Harvey Hunt <harveyhuntnexus@gmail.com>
  L:    linux-mtd@lists.infradead.org
  S:    Maintained
- F:    drivers/mtd/nand/raw/jz4780_*
+ F:    drivers/mtd/nand/raw/ingenic/
+ INGENIC JZ47xx SoCs
+ M:    Paul Cercueil <paul@crapouillou.net>
+ S:    Maintained
+ F:    arch/mips/boot/dts/ingenic/
+ F:    arch/mips/include/asm/mach-jz4740/
+ F:    arch/mips/jz4740/
+ F:    drivers/clk/ingenic/
+ F:    drivers/dma/dma-jz4780.c
+ F:    drivers/gpu/drm/ingenic/
+ F:    drivers/i2c/busses/i2c-jz4780.c
+ F:    drivers/iio/adc/ingenic-adc.c
+ F:    drivers/irqchip/irq-ingenic.c
+ F:    drivers/memory/jz4780-nemc.c
+ F:    drivers/mmc/host/jz4740_mmc.c
+ F:    drivers/mtd/nand/raw/ingenic/
+ F:    drivers/pinctrl/pinctrl-ingenic.c
+ F:    drivers/power/supply/ingenic-battery.c
+ F:    drivers/pwm/pwm-jz4740.c
+ F:    drivers/rtc/rtc-jz4740.c
+ F:    drivers/tty/serial/8250/8250_ingenic.c
+ F:    drivers/usb/musb/jz4740.c
+ F:    drivers/watchdog/jz4740_wdt.c
+ F:    include/dt-bindings/iio/adc/ingenic,adc.h
+ F:    include/linux/mfd/ingenic-tcu.h
+ F:    sound/soc/jz4740/
+ F:    sound/soc/codecs/jz47*
  
  INOTIFY
  M:    Jan Kara <jack@suse.cz>
@@@ -7925,7 -8115,7 +8109,7 @@@ INTEL FRAMEBUFFER DRIVER (excluding 81
  M:    Maik Broemme <mbroemme@libmpq.org>
  L:    linux-fbdev@vger.kernel.org
  S:    Maintained
- F:    Documentation/fb/intelfb.txt
+ F:    Documentation/fb/intelfb.rst
  F:    drivers/video/fbdev/intelfb/
  
  INTEL GPIO DRIVERS
@@@ -8036,7 -8226,7 +8220,7 @@@ F:      include/uapi/linux/mei.
  F:    include/linux/mei_cl_bus.h
  F:    drivers/misc/mei/*
  F:    drivers/watchdog/mei_wdt.c
- F:    Documentation/misc-devices/mei/*
+ F:    Documentation/driver-api/mei/*
  F:    samples/mei/*
  
  INTEL MENLOW THERMAL DRIVER
@@@ -8085,7 -8275,7 +8269,7 @@@ T:      git git://git.kernel.org/pub/scm/lin
  F:    drivers/gpio/gpio-*cove.c
  F:    drivers/gpio/gpio-msic.c
  
- INTEL MULTIFUNCTION PMIC DEVICE DRIVERS
+ INTEL PMIC MULTIFUNCTION DEVICE DRIVERS
  R:    Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  S:    Maintained
  F:    drivers/mfd/intel_msic.c
@@@ -8116,6 -8306,14 +8300,14 @@@ S:    Supporte
  F:    drivers/infiniband/hw/i40iw/
  F:    include/uapi/rdma/i40iw-abi.h
  
+ INTEL SPEED SELECT TECHNOLOGY
+ M:    Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+ L:    platform-driver-x86@vger.kernel.org
+ S:    Maintained
+ F:    drivers/platform/x86/intel_speed_select_if/
+ F:    tools/power/x86/intel-speed-select/
+ F:    include/uapi/linux/isst_if.h
  INTEL TELEMETRY DRIVER
  M:    Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
  M:    "David E. Box" <david.e.box@linux.intel.com>
@@@ -8174,7 -8372,7 +8366,7 @@@ L:      tboot-devel@lists.sourceforge.ne
  W:    http://tboot.sourceforge.net
  T:    hg http://tboot.hg.sourceforge.net:8000/hgroot/tboot/tboot
  S:    Supported
- F:    Documentation/intel_txt.txt
+ F:    Documentation/x86/intel_txt.rst
  F:    include/linux/tboot.h
  F:    arch/x86/kernel/tboot.c
  
@@@ -8188,7 -8386,7 +8380,7 @@@ INTERCONNECT AP
  M:    Georgi Djakov <georgi.djakov@linaro.org>
  L:    linux-pm@vger.kernel.org
  S:    Maintained
- F:    Documentation/interconnect/
+ F:    Documentation/driver-api/interconnect.rst
  F:    Documentation/devicetree/bindings/interconnect/
  F:    drivers/interconnect/
  F:    include/dt-bindings/interconnect/
@@@ -8224,6 -8422,7 +8416,7 @@@ L:      linux-fsdevel@vger.kernel.or
  T:    git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git
  S:    Supported
  F:    fs/iomap.c
+ F:    fs/iomap/
  F:    include/linux/iomap.h
  
  IOMMU DRIVERS
@@@ -8296,7 -8495,7 +8489,7 @@@ S:      Obsolet
  F:    include/uapi/linux/ipx.h
  
  IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
- M:    Marc Zyngier <marc.zyngier@arm.com>
+ M:    Marc Zyngier <maz@kernel.org>
  S:    Maintained
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
  F:    Documentation/IRQ-domain.txt
@@@ -8314,7 -8513,7 +8507,7 @@@ F:      kernel/irq
  IRQCHIP DRIVERS
  M:    Thomas Gleixner <tglx@linutronix.de>
  M:    Jason Cooper <jason@lakedaemon.net>
- M:    Marc Zyngier <marc.zyngier@arm.com>
+ M:    Marc Zyngier <maz@kernel.org>
  L:    linux-kernel@vger.kernel.org
  S:    Maintained
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
@@@ -8324,7 -8523,7 +8517,7 @@@ F:      drivers/irqchip
  ISA
  M:    William Breathitt Gray <vilhelm.gray@gmail.com>
  S:    Maintained
- F:    Documentation/isa.txt
+ F:    Documentation/driver-api/isa.rst
  F:    drivers/base/isa.c
  F:    include/linux/isa.h
  
@@@ -8339,7 -8538,7 +8532,7 @@@ F:      drivers/media/radio/radio-isa
  ISAPNP
  M:    Jaroslav Kysela <perex@perex.cz>
  S:    Maintained
- F:    Documentation/isapnp.txt
+ F:    Documentation/driver-api/isapnp.rst
  F:    drivers/pnp/isapnp/
  F:    include/linux/isapnp.h
  
@@@ -8377,18 -8576,26 +8570,26 @@@ S:   Supporte
  W:    http://www.linux-iscsi.org
  F:    drivers/infiniband/ulp/isert
  
- ISDN SUBSYSTEM
+ ISDN/mISDN SUBSYSTEM
  M:    Karsten Keil <isdn@linux-pingi.de>
  L:    isdn4linux@listserv.isdn4linux.de (subscribers-only)
  L:    netdev@vger.kernel.org
  W:    http://www.isdn4linux.de
- T:    git git://git.kernel.org/pub/scm/linux/kernel/git/kkeil/isdn-2.6.git
  S:    Maintained
+ F:    drivers/isdn/mISDN
+ F:    drivers/isdn/hardware
+ ISDN/CAPI SUBSYSTEM
+ M:    Karsten Keil <isdn@linux-pingi.de>
+ L:    isdn4linux@listserv.isdn4linux.de (subscribers-only)
+ L:    netdev@vger.kernel.org
+ W:    http://www.isdn4linux.de
+ S:    Odd Fixes
  F:    Documentation/isdn/
- F:    drivers/isdn/
- F:    include/linux/isdn.h
+ F:    drivers/isdn/capi/
+ F:    drivers/staging/isdn/
+ F:    net/bluetooth/cmtp/
  F:    include/linux/isdn/
- F:    include/uapi/linux/isdn.h
  F:    include/uapi/linux/isdn/
  
  IT87 HARDWARE MONITORING DRIVER
@@@ -8529,7 -8736,7 +8730,7 @@@ R:      Vivek Goyal <vgoyal@redhat.com
  L:    kexec@lists.infradead.org
  W:    http://lse.sourceforge.net/kdump/
  S:    Maintained
- F:    Documentation/kdump/
+ F:    Documentation/admin-guide/kdump/
  
  KEENE FM RADIO TRANSMITTER DRIVER
  M:    Hans Verkuil <hverkuil@xs4all.nl>
@@@ -8568,7 -8775,7 +8769,7 @@@ S:      Odd Fixe
  
  KERNEL NFSD, SUNRPC, AND LOCKD SERVERS
  M:    "J. Bruce Fields" <bfields@fieldses.org>
- M:    Jeff Layton <jlayton@kernel.org>
+ M:    Chuck Lever <chuck.lever@oracle.com>
  L:    linux-nfs@vger.kernel.org
  W:    http://nfs.sourceforge.net/
  T:    git git://linux-nfs.org/~bfields/linux.git
@@@ -8606,7 -8813,7 +8807,7 @@@ L:      kvm@vger.kernel.or
  W:    http://www.linux-kvm.org
  T:    git git://git.kernel.org/pub/scm/virt/kvm/kvm.git
  S:    Supported
- F:    Documentation/virtual/kvm/
+ F:    Documentation/virt/kvm/
  F:    include/trace/events/kvm.h
  F:    include/uapi/asm-generic/kvm*
  F:    include/uapi/linux/kvm*
@@@ -8626,10 -8833,10 +8827,10 @@@ F:   arch/x86/include/asm/svm.
  F:    arch/x86/kvm/svm.c
  
  KERNEL VIRTUAL MACHINE FOR ARM/ARM64 (KVM/arm, KVM/arm64)
- M:    Marc Zyngier <marc.zyngier@arm.com>
+ M:    Marc Zyngier <maz@kernel.org>
  R:    James Morse <james.morse@arm.com>
- R:    Julien Thierry <julien.thierry@arm.com>
- R:    Suzuki K Pouloze <suzuki.poulose@arm.com>
+ R:    Julien Thierry <julien.thierry.kdev@gmail.com>
+ R:    Suzuki K Poulose <suzuki.poulose@arm.com>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  L:    kvmarm@lists.cs.columbia.edu
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git
@@@ -8676,6 -8883,8 +8877,8 @@@ F:      arch/s390/include/asm/gmap.
  F:    arch/s390/include/asm/kvm*
  F:    arch/s390/kvm/
  F:    arch/s390/mm/gmap.c
+ F:    tools/testing/selftests/kvm/s390x/
+ F:    tools/testing/selftests/kvm/*/s390x/
  
  KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
  M:    Paolo Bonzini <pbonzini@redhat.com>
@@@ -8861,7 -9070,7 +9064,7 @@@ F:      include/linux/leds.
  LEGACY EEPROM DRIVER
  M:    Jean Delvare <jdelvare@suse.com>
  S:    Maintained
- F:    Documentation/misc-devices/eeprom
+ F:    Documentation/misc-devices/eeprom.rst
  F:    drivers/misc/eeprom/eeprom.c
  
  LEGO MINDSTORMS EV3
@@@ -8883,7 -9092,7 +9086,7 @@@ M:      Matan Ziv-Av <matan@svgalib.org
  L:    platform-driver-x86@vger.kernel.org
  S:    Maintained
  F:    Documentation/ABI/testing/sysfs-platform-lg-laptop
- F:    Documentation/laptops/lg-laptop.rst
+ F:    Documentation/admin-guide/laptops/lg-laptop.rst
  F:    drivers/platform/x86/lg-laptop.c
  
  LG2160 MEDIA DRIVER
@@@ -9123,7 -9332,7 +9326,7 @@@ F:      drivers/misc/lkdtm/
  LINUX KERNEL MEMORY CONSISTENCY MODEL (LKMM)
  M:    Alan Stern <stern@rowland.harvard.edu>
  M:    Andrea Parri <andrea.parri@amarulasolutions.com>
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  M:    Peter Zijlstra <peterz@infradead.org>
  M:    Boqun Feng <boqun.feng@gmail.com>
  M:    Nicholas Piggin <npiggin@gmail.com>
@@@ -9147,7 -9356,7 +9350,7 @@@ F:      Documentation/memory-barriers.tx
  LIS3LV02D ACCELEROMETER DRIVER
  M:    Eric Piel <eric.piel@tremplin-utc.net>
  S:    Maintained
- F:    Documentation/misc-devices/lis3lv02d
+ F:    Documentation/misc-devices/lis3lv02d.rst
  F:    drivers/misc/lis3lv02d/
  F:    drivers/platform/x86/hp_accel.c
  
@@@ -9231,7 -9440,7 +9434,7 @@@ F:      Documentation/admin-guide/LSM/LoadPi
  LOCKING PRIMITIVES
  M:    Peter Zijlstra <peterz@infradead.org>
  M:    Ingo Molnar <mingo@redhat.com>
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  L:    linux-kernel@vger.kernel.org
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git locking/core
  S:    Maintained
@@@ -9252,7 -9461,7 +9455,7 @@@ M:      "Richard Russon (FlatCap)" <ldm@flat
  L:    linux-ntfs-dev@lists.sourceforge.net
  W:    http://www.linux-ntfs.org/content/view/19/37/
  S:    Maintained
- F:    Documentation/ldm.txt
+ F:    Documentation/admin-guide/ldm.rst
  F:    block/partitions/ldm.*
  
  LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
@@@ -9638,6 -9847,17 +9841,17 @@@ L:    linux-iio@vger.kernel.or
  S:    Maintained
  F:    drivers/iio/dac/cio-dac.c
  
+ MEDIA CONTROLLER FRAMEWORK
+ M:    Sakari Ailus <sakari.ailus@linux.intel.com>
+ M:    Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ L:    linux-media@vger.kernel.org
+ W:    https://www.linuxtv.org
+ T:    git git://linuxtv.org/media_tree.git
+ S:    Supported
+ F:    drivers/media/mc/
+ F:    include/media/media-*.h
+ F:    include/uapi/linux/media.h
  MEDIA DRIVERS FOR ASCOT2E
  M:    Sergey Kozlov <serjk@netup.ru>
  M:    Abylay Ospan <aospan@netup.ru>
@@@ -9959,6 -10179,13 +10173,13 @@@ L:  linux-wireless@vger.kernel.or
  S:    Maintained
  F:    drivers/net/wireless/mediatek/mt7601u/
  
+ MEDIATEK MT7621/28/88 I2C DRIVER
+ M:    Stefan Roese <sr@denx.de>
+ L:    linux-i2c@vger.kernel.org
+ S:    Maintained
+ F:    drivers/i2c/busses/i2c-mt7621.c
+ F:    Documentation/devicetree/bindings/i2c/i2c-mt7621.txt
  MEDIATEK NAND CONTROLLER DRIVER
  M:    Xiaolei Li <xiaolei.li@mediatek.com>
  L:    linux-mtd@lists.infradead.org
@@@ -10104,6 -10331,7 +10325,7 @@@ Q:   http://patchwork.ozlabs.org/project/
  S:    Supported
  F:    drivers/net/ethernet/mellanox/mlx5/core/
  F:    include/linux/mlx5/
+ F:    Documentation/networking/device_drivers/mellanox/
  
  MELLANOX MLX5 IB driver
  M:    Leon Romanovsky <leonro@mellanox.com>
@@@ -10130,7 -10358,7 +10352,7 @@@ L:   linux-leds@vger.kernel.or
  S:    Supported
  F:    drivers/leds/leds-mlxcpld.c
  F:    drivers/leds/leds-mlxreg.c
- F:    Documentation/leds/leds-mlxcpld.txt
+ F:    Documentation/leds/leds-mlxcpld.rst
  
  MELLANOX PLATFORM DRIVER
  M:    Vadim Pasternak <vadimp@mellanox.com>
@@@ -10195,7 -10423,7 +10417,7 @@@ M:   Johannes Thumshirn <morbidrsa@gmail.
  S:    Maintained
  F:    drivers/mcb/
  F:    include/linux/mcb.h
- F:    Documentation/men-chameleon-bus.txt
+ F:    Documentation/driver-api/men-chameleon-bus.rst
  
  MEN F21BMC (Board Management Controller)
  M:    Andreas Werner <andreas.werner@men.de>
@@@ -10214,7 -10442,7 +10436,7 @@@ F:   drivers/watchdog/menz69_wdt.
  
  MESON AO CEC DRIVER FOR AMLOGIC SOCS
  M:    Neil Armstrong <narmstrong@baylibre.com>
- L:    linux-media@lists.freedesktop.org
+ L:    linux-media@vger.kernel.org
  L:    linux-amlogic@lists.infradead.org
  W:    http://linux-meson.com/
  S:    Supported
@@@ -10230,6 -10458,14 +10452,14 @@@ S: Maintaine
  F:    drivers/mtd/nand/raw/meson_*
  F:    Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
  
+ MESON VIDEO DECODER DRIVER FOR AMLOGIC SOCS
+ M:    Maxime Jourdan <mjourdan@baylibre.com>
+ L:    linux-media@vger.kernel.org
+ L:    linux-amlogic@lists.infradead.org
+ S:    Supported
+ F:    drivers/staging/media/meson/vdec/
+ T:    git git://linuxtv.org/media_tree.git
  METHODE UDPU SUPPORT
  M:    Vladimir Vid <vladimir.vid@sartura.hr>
  S:    Maintained
@@@ -10283,7 -10519,9 +10513,9 @@@ MICROCHIP ISC DRIVE
  M:    Eugen Hristev <eugen.hristev@microchip.com>
  L:    linux-media@vger.kernel.org
  S:    Supported
- F:    drivers/media/platform/atmel/atmel-isc.c
+ F:    drivers/media/platform/atmel/atmel-sama5d2-isc.c
+ F:    drivers/media/platform/atmel/atmel-isc.h
+ F:    drivers/media/platform/atmel/atmel-isc-base.c
  F:    drivers/media/platform/atmel/atmel-isc-regs.h
  F:    Documentation/devicetree/bindings/media/atmel-isc.txt
  
@@@ -10552,7 -10790,7 +10784,7 @@@ F:   arch/arm/boot/dts/mmp
  F:    arch/arm/mach-mmp/
  
  MMU GATHER AND TLB INVALIDATION
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  M:    "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
  M:    Andrew Morton <akpm@linux-foundation.org>
  M:    Nick Piggin <npiggin@gmail.com>
@@@ -10599,7 -10837,7 +10831,7 @@@ F:   include/uapi/linux/meye.
  MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD
  M:    Jiri Slaby <jirislaby@gmail.com>
  S:    Maintained
- F:    Documentation/serial/moxa-smartio.rst
+ F:    Documentation/driver-api/serial/moxa-smartio.rst
  F:    drivers/tty/mxser.*
  
  MR800 AVERMEDIA USB FM RADIO DRIVER
@@@ -10843,14 -11081,6 +11075,6 @@@ F:  driver/net/net_failover.
  F:    include/net/net_failover.h
  F:    Documentation/networking/net_failover.rst
  
- NETEFFECT IWARP RNIC DRIVER (IW_NES)
- M:    Faisal Latif <faisal.latif@intel.com>
- L:    linux-rdma@vger.kernel.org
- W:    http://www.intel.com/Products/Server/Adapters/Server-Cluster/Server-Cluster-overview.htm
- S:    Supported
- F:    drivers/infiniband/hw/nes/
- F:    include/uapi/rdma/nes-abi.h
  NETEM NETWORK EMULATOR
  M:    Stephen Hemminger <stephen@networkplumber.org>
  L:    netem@lists.linux-foundation.org (moderated for non-subscribers)
@@@ -10867,7 -11097,7 +11091,7 @@@ F:   drivers/net/ethernet/neterion
  
  NETFILTER
  M:    Pablo Neira Ayuso <pablo@netfilter.org>
- M:    Jozsef Kadlecsik <kadlec@blackhole.kfki.hu>
+ M:    Jozsef Kadlecsik <kadlec@netfilter.org>
  M:    Florian Westphal <fw@strlen.de>
  L:    netfilter-devel@vger.kernel.org
  L:    coreteam@netfilter.org
@@@ -10908,7 -11138,7 +11132,7 @@@ M:   Josef Bacik <josef@toxicpanda.com
  S:    Maintained
  L:    linux-block@vger.kernel.org
  L:    nbd@other.debian.org
- F:    Documentation/blockdev/nbd.txt
+ F:    Documentation/admin-guide/blockdev/nbd.rst
  F:    drivers/block/nbd.c
  F:    include/trace/events/nbd.h
  F:    include/uapi/linux/nbd.h
@@@ -11080,6 -11310,15 +11304,15 @@@ L: netdev@vger.kernel.or
  S:    Supported
  F:    drivers/net/ethernet/qlogic/netxen/
  
+ NEXTHOP
+ M:    David Ahern <dsahern@kernel.org>
+ L:    netdev@vger.kernel.org
+ S:    Maintained
+ F:    include/net/nexthop.h
+ F:    include/uapi/linux/nexthop.h
+ F:    include/net/netns/nexthop.h
+ F:    net/ipv4/nexthop.c
  NFC SUBSYSTEM
  L:    netdev@vger.kernel.org
  S:    Orphan
@@@ -11109,7 -11348,7 +11342,7 @@@ F:   include/uapi/linux/nfs
  F:    include/uapi/linux/sunrpc/
  
  NILFS2 FILESYSTEM
- M:    Ryusuke Konishi <konishi.ryusuke@lab.ntt.co.jp>
+ M:    Ryusuke Konishi <konishi.ryusuke@gmail.com>
  L:    linux-nilfs@vger.kernel.org
  W:    https://nilfs.sourceforge.io/
  W:    https://nilfs.osdn.jp/
@@@ -11283,7 -11522,7 +11516,7 @@@ NXP FXAS21002C DRIVE
  M:    Rui Miguel Silva <rmfrfs@gmail.com>
  L:    linux-iio@vger.kernel.org
  S:    Maintained
- F:    Documentation/devicetree/bindings/iio/gyroscope/fxas21002c.txt
+ F:    Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.txt
  F:    drivers/iio/gyro/fxas21002c_core.c
  F:    drivers/iio/gyro/fxas21002c.h
  F:    drivers/iio/gyro/fxas21002c_i2c.c
@@@ -11358,7 -11597,7 +11591,7 @@@ F:   arch/powerpc/include/asm/pnv-ocxl.
  F:    drivers/misc/ocxl/
  F:    include/misc/ocxl*
  F:    include/uapi/misc/ocxl.h
- F:    Documentation/accelerators/ocxl.rst
+ F:    Documentation/userspace-api/accelerators/ocxl.rst
  
  OMAP AUDIO SUPPORT
  M:    Peter Ujfalusi <peter.ujfalusi@ti.com>
@@@ -11394,7 -11633,7 +11627,7 @@@ L:   linux-omap@vger.kernel.or
  L:    linux-fbdev@vger.kernel.org
  S:    Orphan
  F:    drivers/video/fbdev/omap2/
- F:    Documentation/arm/OMAP/DSS
+ F:    Documentation/arm/omap/dss.rst
  
  OMAP FRAMEBUFFER SUPPORT
  L:    linux-fbdev@vger.kernel.org
@@@ -11673,23 -11912,15 +11906,15 @@@ S:        Maintaine
  F:    drivers/mtd/nand/onenand/
  F:    include/linux/mtd/onenand*.h
  
- ONSTREAM SCSI TAPE DRIVER
- M:    Willem Riede <osst@riede.org>
- L:    osst-users@lists.sourceforge.net
- L:    linux-scsi@vger.kernel.org
- S:    Maintained
- F:    Documentation/scsi/osst.txt
- F:    drivers/scsi/osst.*
- F:    drivers/scsi/osst_*.h
- F:    drivers/scsi/st.h
  OP-TEE DRIVER
  M:    Jens Wiklander <jens.wiklander@linaro.org>
+ L:    tee-dev@lists.linaro.org
  S:    Maintained
  F:    drivers/tee/optee/
  
  OP-TEE RANDOM NUMBER GENERATOR (RNG) DRIVER
  M:    Sumit Garg <sumit.garg@linaro.org>
+ L:    tee-dev@lists.linaro.org
  S:    Maintained
  F:    drivers/char/hw_random/optee-rng.c
  
@@@ -11776,7 -12007,7 +12001,7 @@@ S:   Maintaine
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git
  F:    drivers/opp/
  F:    include/linux/pm_opp.h
- F:    Documentation/power/opp.txt
+ F:    Documentation/power/opp.rst
  F:    Documentation/devicetree/bindings/opp/
  
  OPL4 DRIVER
@@@ -11873,6 -12104,14 +12098,14 @@@ F: kernel/padata.
  F:    include/linux/padata.h
  F:    Documentation/padata.txt
  
+ PAGE POOL
+ M:    Jesper Dangaard Brouer <hawk@kernel.org>
+ M:    Ilias Apalodimas <ilias.apalodimas@linaro.org>
+ L:    netdev@vger.kernel.org
+ S:    Supported
+ F:    net/core/page_pool.c
+ F:    include/net/page_pool.h
  PANASONIC LAPTOP ACPI EXTRAS DRIVER
  M:    Harald Welte <laforge@gnumonks.org>
  L:    platform-driver-x86@vger.kernel.org
@@@ -11883,7 -12122,7 +12116,7 @@@ PARALLEL LCD/KEYPAD PANEL DRIVE
  M:    Willy Tarreau <willy@haproxy.com>
  M:    Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
  S:    Odd Fixes
- F:    Documentation/auxdisplay/lcd-panel-cgram.txt
+ F:    Documentation/admin-guide/lcd-panel-cgram.rst
  F:    drivers/auxdisplay/panel.c
  
  PARALLEL PORT SUBSYSTEM
@@@ -11895,14 -12134,15 +12128,15 @@@ F:        drivers/parport
  F:    include/linux/parport*.h
  F:    drivers/char/ppdev.c
  F:    include/uapi/linux/ppdev.h
- F:    Documentation/parport*.txt
+ F:    Documentation/driver-api/parport*.rst
  
  PARAVIRT_OPS INTERFACE
  M:    Juergen Gross <jgross@suse.com>
- M:    Alok Kataria <akataria@vmware.com>
+ M:    Thomas Hellstrom <thellstrom@vmware.com>
+ M:    "VMware, Inc." <pv-drivers@vmware.com>
  L:    virtualization@lists.linux-foundation.org
  S:    Supported
- F:    Documentation/virtual/paravirt_ops.txt
+ F:    Documentation/virt/paravirt_ops.rst
  F:    arch/*/kernel/paravirt*
  F:    arch/*/include/asm/paravirt*.h
  F:    include/linux/hypervisor.h
@@@ -11911,7 -12151,7 +12145,7 @@@ PARIDE DRIVERS FOR PARALLEL PORT IDE DE
  M:    Tim Waugh <tim@cyberelk.net>
  L:    linux-parport@lists.infradead.org (subscribers-only)
  S:    Maintained
- F:    Documentation/blockdev/paride.txt
+ F:    Documentation/admin-guide/blockdev/paride.rst
  F:    drivers/block/paride/
  
  PARISC ARCHITECTURE
@@@ -12041,7 -12281,7 +12275,7 @@@ S:   Maintaine
  F:    drivers/pci/controller/dwc/*layerscape*
  
  PCI DRIVER FOR GENERIC OF HOSTS
- M:    Will Deacon <will.deacon@arm.com>
+ M:    Will Deacon <will@kernel.org>
  L:    linux-pci@vger.kernel.org
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  S:    Maintained
@@@ -12070,7 -12310,7 +12304,7 @@@ M:   Kurt Schwemmer <kurt.schwemmer@micro
  M:    Logan Gunthorpe <logang@deltatee.com>
  L:    linux-pci@vger.kernel.org
  S:    Maintained
- F:    Documentation/switchtec.txt
+ F:    Documentation/driver-api/switchtec.rst
  F:    Documentation/ABI/testing/sysfs-class-switchtec
  F:    drivers/pci/switch/switchtec*
  F:    include/uapi/linux/switchtec_ioctl.h
@@@ -12155,11 -12395,11 +12389,11 @@@ M:        Sam Bobroff <sbobroff@linux.ibm.com
  M:    Oliver O'Halloran <oohall@gmail.com>
  L:    linuxppc-dev@lists.ozlabs.org
  S:    Supported
- F:    Documentation/PCI/pci-error-recovery.txt
+ F:    Documentation/PCI/pci-error-recovery.rst
  F:    drivers/pci/pcie/aer.c
  F:    drivers/pci/pcie/dpc.c
  F:    drivers/pci/pcie/err.c
- F:    Documentation/powerpc/eeh-pci-error-recovery.txt
+ F:    Documentation/powerpc/eeh-pci-error-recovery.rst
  F:    arch/powerpc/kernel/eeh*.c
  F:    arch/powerpc/platforms/*/eeh*.c
  F:    arch/powerpc/include/*/eeh*.h
@@@ -12168,7 -12408,7 +12402,7 @@@ PCI ERROR RECOVER
  M:    Linas Vepstas <linasvepstas@gmail.com>
  L:    linux-pci@vger.kernel.org
  S:    Supported
- F:    Documentation/PCI/pci-error-recovery.txt
+ F:    Documentation/PCI/pci-error-recovery.rst
  
  PCI MSI DRIVER FOR ALTERA MSI IP
  M:    Ley Foon Tan <lftan@altera.com>
@@@ -12417,6 -12657,17 +12651,17 @@@ F: arch/arm/boot/dts/picoxcell
  F:    arch/arm/mach-picoxcell/
  F:    drivers/crypto/picoxcell*
  
+ PIDFD API
+ M:    Christian Brauner <christian@brauner.io>
+ L:    linux-kernel@vger.kernel.org
+ S:    Maintained
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git
+ F:    samples/pidfd/
+ F:    tools/testing/selftests/pidfd/
+ K:    (?i)pidfd
+ K:    (?i)clone3
+ K:    \b(clone_args|kernel_clone_args)\b
  PIN CONTROL SUBSYSTEM
  M:    Linus Walleij <linus.walleij@linaro.org>
  L:    linux-gpio@vger.kernel.org
@@@ -12566,8 -12817,7 +12811,7 @@@ S:   Orpha
  F:    drivers/scsi/pmcraid.*
  
  PMC SIERRA PM8001 DRIVER
- M:    Jack Wang <jinpu.wang@profitbricks.com>
- M:    lindar_liu@usish.com
+ M:    Jack Wang <jinpu.wang@cloud.ionos.com>
  L:    linux-scsi@vger.kernel.org
  S:    Supported
  F:    drivers/scsi/pm8001/
@@@ -12603,6 -12853,7 +12847,7 @@@ F:   drivers/base/power
  F:    include/linux/pm.h
  F:    include/linux/pm_*
  F:    include/linux/powercap.h
+ F:    include/linux/intel_rapl.h
  F:    drivers/powercap/
  F:    kernel/configs/nopm.config
  
@@@ -12661,7 -12912,7 +12906,7 @@@ M:   Rodolfo Giometti <giometti@enneenne.
  W:    http://wiki.enneenne.com/index.php/LinuxPPS_support
  L:    linuxpps@ml.enneenne.com (subscribers-only)
  S:    Maintained
- F:    Documentation/pps/
+ F:    Documentation/driver-api/pps.rst
  F:    Documentation/devicetree/bindings/pps/pps-gpio.txt
  F:    Documentation/ABI/testing/sysfs-pps
  F:    drivers/pps/
@@@ -12767,7 -13018,7 +13012,7 @@@ L:   netdev@vger.kernel.or
  S:    Maintained
  W:    http://linuxptp.sourceforge.net/
  F:    Documentation/ABI/testing/sysfs-ptp
- F:    Documentation/ptp/*
+ F:    Documentation/driver-api/ptp.rst
  F:    drivers/net/phy/dp83640*
  F:    drivers/ptp/*
  F:    include/linux/ptp_cl*
@@@ -12781,7 -13032,6 +13026,6 @@@ F:   include/linux/regset.
  F:    include/linux/tracehook.h
  F:    include/uapi/linux/ptrace.h
  F:    include/uapi/linux/ptrace.h
- F:    include/asm-generic/ptrace.h
  F:    kernel/ptrace.c
  F:    arch/*/ptrace*.c
  F:    arch/*/*/ptrace*.c
@@@ -12833,7 -13083,7 +13077,7 @@@ M:   Thierry Reding <thierry.reding@gmail
  L:    linux-pwm@vger.kernel.org
  S:    Maintained
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git
- F:    Documentation/pwm.txt
+ F:    Documentation/driver-api/pwm.rst
  F:    Documentation/devicetree/bindings/pwm/
  F:    include/linux/pwm.h
  F:    drivers/pwm/
@@@ -13055,7 -13305,7 +13299,7 @@@ M:   Niklas Cassel <niklas.cassel@linaro.
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
- F:    Documentation/devicetree/bindings/net/qcom,dwmac.txt
+ F:    Documentation/devicetree/bindings/net/qcom,ethqos.txt
  
  QUALCOMM GENERIC INTERFACE I2C DRIVER
  M:    Alok Chauhan <alokc@codeaurora.org>
@@@ -13194,7 -13444,7 +13438,7 @@@ F:   drivers/net/wireless/ralink/rt2x00
  RAMDISK RAM BLOCK DEVICE DRIVER
  M:    Jens Axboe <axboe@kernel.dk>
  S:    Maintained
- F:    Documentation/blockdev/ramdisk.txt
+ F:    Documentation/admin-guide/blockdev/ramdisk.rst
  F:    drivers/block/brd.c
  
  RANCHU VIRTUAL BOARD FOR MIPS
@@@ -13303,7 -13553,7 +13547,7 @@@ Q:   http://patchwork.ozlabs.org/project/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git
  S:    Maintained
  F:    Documentation/devicetree/bindings/rtc/
- F:    Documentation/rtc.txt
+ F:    Documentation/admin-guide/rtc.rst
  F:    drivers/rtc/
  F:    include/linux/rtc.h
  F:    include/uapi/linux/rtc.h
@@@ -13353,9 -13603,11 +13597,11 @@@ L: linux-remoteproc@vger.kernel.or
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/ohad/remoteproc.git
  S:    Maintained
  F:    Documentation/devicetree/bindings/remoteproc/
+ F:    Documentation/ABI/testing/sysfs-class-remoteproc
  F:    Documentation/remoteproc.txt
  F:    drivers/remoteproc/
  F:    include/linux/remoteproc.h
+ F:    include/linux/remoteproc/
  
  REMOTE PROCESSOR MESSAGING (RPMSG) SUBSYSTEM
  M:    Ohad Ben-Cohen <ohad@wizery.com>
@@@ -13365,8 -13617,11 +13611,11 @@@ T: git git://git.kernel.org/pub/scm/lin
  S:    Maintained
  F:    drivers/rpmsg/
  F:    Documentation/rpmsg.txt
+ F:    Documentation/ABI/testing/sysfs-bus-rpmsg
  F:    include/linux/rpmsg.h
  F:    include/linux/rpmsg/
+ F:    include/uapi/linux/rpmsg.h
+ F:    samples/rpmsg/
  
  RENESAS CLOCK DRIVERS
  M:    Geert Uytterhoeven <geert+renesas@glider.be>
@@@ -13447,7 -13702,7 +13696,7 @@@ W:   http://wireless.kernel.org
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
  S:    Maintained
- F:    Documentation/rfkill.txt
+ F:    Documentation/driver-api/rfkill.rst
  F:    Documentation/ABI/stable/sysfs-class-rfkill
  F:    net/rfkill/
  F:    include/linux/rfkill.h
@@@ -13475,10 -13730,11 +13724,11 @@@ F:        drivers/mtd/nand/raw/r852.
  F:    drivers/mtd/nand/raw/r852.h
  
  RISC-V ARCHITECTURE
+ M:    Paul Walmsley <paul.walmsley@sifive.com>
  M:    Palmer Dabbelt <palmer@sifive.com>
  M:    Albert Ou <aou@eecs.berkeley.edu>
  L:    linux-riscv@lists.infradead.org
- T:    git git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
  S:    Supported
  F:    arch/riscv/
  K:    riscv
@@@ -13499,11 -13755,11 +13749,11 @@@ S:        Maintaine
  F:    drivers/media/platform/rockchip/rga/
  F:    Documentation/devicetree/bindings/media/rockchip-rga.txt
  
ROCKCHIP VPU CODEC DRIVER
HANTRO VPU CODEC DRIVER
  M:    Ezequiel Garcia <ezequiel@collabora.com>
  L:    linux-media@vger.kernel.org
  S:    Maintained
- F:    drivers/staging/media/platform/rockchip/vpu/
+ F:    drivers/staging/media/platform/hantro/
  F:    Documentation/devicetree/bindings/media/rockchip-vpu.txt
  
  ROCKER DRIVER
@@@ -13516,7 -13772,7 +13766,7 @@@ ROCKETPORT DRIVE
  P:    Comtrol Corp.
  W:    http://www.comtrol.com
  S:    Maintained
- F:    Documentation/serial/rocket.rst
+ F:    Documentation/driver-api/serial/rocket.rst
  F:    drivers/tty/rocket*
  
  ROCKETPORT EXPRESS/INFINITY DRIVER
@@@ -13697,14 -13953,13 +13947,13 @@@ F:        drivers/pci/hotplug/s390_pci_hpc.
  
  S390 VFIO-CCW DRIVER
  M:    Cornelia Huck <cohuck@redhat.com>
- M:    Farhan Ali <alifm@linux.ibm.com>
  M:    Eric Farman <farman@linux.ibm.com>
  R:    Halil Pasic <pasic@linux.ibm.com>
  L:    linux-s390@vger.kernel.org
  L:    kvm@vger.kernel.org
  S:    Supported
  F:    drivers/s390/cio/vfio_ccw*
- F:    Documentation/s390/vfio-ccw.txt
+ F:    Documentation/s390/vfio-ccw.rst
  F:    include/uapi/linux/vfio_ccw.h
  
  S390 ZCRYPT DRIVER
@@@ -13724,7 -13979,7 +13973,7 @@@ S:   Supporte
  F:    drivers/s390/crypto/vfio_ap_drv.c
  F:    drivers/s390/crypto/vfio_ap_private.h
  F:    drivers/s390/crypto/vfio_ap_ops.c
- F:    Documentation/s390/vfio-ap.txt
+ F:    Documentation/s390/vfio-ap.rst
  
  S390 ZFCP DRIVER
  M:    Steffen Maier <maier@linux.ibm.com>
@@@ -13766,6 -14021,12 +14015,12 @@@ F: drivers/media/common/saa7146
  F:    drivers/media/pci/saa7146/
  F:    include/media/drv-intf/saa7146*
  
+ SAFESETID SECURITY MODULE
+ M:     Micah Morton <mortonm@chromium.org>
+ S:     Supported
+ F:     security/safesetid/
+ F:     Documentation/admin-guide/LSM/SafeSetID.rst
  SAMSUNG AUDIO (ASoC) DRIVERS
  M:    Krzysztof Kozlowski <krzk@kernel.org>
  M:    Sangbeom Kim <sbkim73@samsung.com>
@@@ -13910,7 -14171,7 +14165,7 @@@ M:   Sylwester Nawrocki <s.nawrocki@samsu
  L:    linux-kernel@vger.kernel.org
  S:    Supported
  F:    Documentation/devicetree/bindings/phy/samsung-phy.txt
- F:    Documentation/phy/samsung-usb2.txt
+ F:    Documentation/driver-api/phy/samsung-usb2.rst
  F:    drivers/phy/samsung/phy-exynos4210-usb2.c
  F:    drivers/phy/samsung/phy-exynos4x12-usb2.c
  F:    drivers/phy/samsung/phy-exynos5250-usb2.c
@@@ -14163,6 -14424,12 +14418,12 @@@ S: Maintaine
  F:    drivers/misc/phantom.c
  F:    include/uapi/linux/phantom.h
  
+ SENSIRION SPS30 AIR POLLUTION SENSOR DRIVER
+ M:    Tomasz Duszynski <tduszyns@gmail.com>
+ S:    Maintained
+ F:    drivers/iio/chemical/sps30.c
+ F:    Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml
  SERIAL DEVICE BUS
  M:    Rob Herring <robh@kernel.org>
  L:    linux-serial@vger.kernel.org
@@@ -14210,7 -14477,7 +14471,7 @@@ SGI SN-IA64 (Altix) SERIAL CONSOLE DRIV
  M:    Pat Gefre <pfg@sgi.com>
  L:    linux-ia64@vger.kernel.org
  S:    Supported
- F:    Documentation/ia64/serial.txt
+ F:    Documentation/ia64/serial.rst
  F:    drivers/tty/serial/ioc?_serial.c
  F:    include/linux/ioc?.h
  
@@@ -14334,9 -14601,18 +14595,18 @@@ M: Paul Walmsley <paul.walmsley@sifive.
  L:    linux-riscv@lists.infradead.org
  T:    git git://github.com/sifive/riscv-linux.git
  S:    Supported
- K:    sifive
+ K:    [^@]sifive
  N:    sifive
  
+ SIFIVE FU540 SYSTEM-ON-CHIP
+ M:    Paul Walmsley <paul.walmsley@sifive.com>
+ M:    Palmer Dabbelt <palmer@sifive.com>
+ L:    linux-riscv@lists.infradead.org
+ T:    git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git
+ S:    Supported
+ K:    fu540
+ N:    fu540
  SILEAD TOUCHSCREEN DRIVER
  M:    Hans de Goede <hdegoede@redhat.com>
  L:    linux-input@vger.kernel.org
@@@ -14352,7 -14628,7 +14622,7 @@@ M:   Sudip Mukherjee <sudip.mukherjee@cod
  L:    linux-fbdev@vger.kernel.org
  S:    Maintained
  F:    drivers/video/fbdev/sm712*
- F:    Documentation/fb/sm712fb.txt
+ F:    Documentation/fb/sm712fb.rst
  
  SIMPLE FIRMWARE INTERFACE (SFI)
  M:    Len Brown <lenb@kernel.org>
@@@ -14397,7 -14673,7 +14667,7 @@@ F:   lib/test_siphash.
  F:    include/linux/siphash.h
  
  SIOX
- M:    Gavin Schenk <g.schenk@eckelmann.de>
+ M:    Thorsten Scherer <t.scherer@eckelmann.de>
  M:    Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
  R:    Pengutronix Kernel Team <kernel@pengutronix.de>
  S:    Supported
@@@ -14422,7 -14698,7 +14692,7 @@@ SIS FRAMEBUFFER DRIVE
  M:    Thomas Winischhofer <thomas@winischhofer.net>
  W:    http://www.winischhofer.net/linuxsisvga.shtml
  S:    Maintained
- F:    Documentation/fb/sisfb.txt
+ F:    Documentation/fb/sisfb.rst
  F:    drivers/video/fbdev/sis/
  F:    include/video/sisfb.h
  
@@@ -14560,6 -14836,13 +14830,13 @@@ M: Chris Boot <bootc@bootc.net
  S:    Maintained
  F:    drivers/leds/leds-net48xx.c
  
+ SOFT-IWARP DRIVER (siw)
+ M:    Bernard Metzler <bmt@zurich.ibm.com>
+ L:    linux-rdma@vger.kernel.org
+ S:    Supported
+ F:    drivers/infiniband/sw/siw/
+ F:    include/uapi/rdma/siw-abi.h
  SOFT-ROCE DRIVER (rxe)
  M:    Moni Shoua <monis@mellanox.com>
  L:    linux-rdma@vger.kernel.org
@@@ -14609,11 -14892,20 +14886,20 @@@ F:        Documentation/devicetree/bindings/ne
  
  SOCIONEXT (SNI) NETSEC NETWORK DRIVER
  M:    Jassi Brar <jaswinder.singh@linaro.org>
+ M:    Ilias Apalodimas <ilias.apalodimas@linaro.org>
  L:    netdev@vger.kernel.org
  S:    Maintained
  F:    drivers/net/ethernet/socionext/netsec.c
  F:    Documentation/devicetree/bindings/net/socionext-netsec.txt
  
+ SOCIONEXT (SNI) Synquacer SPI DRIVER
+ M:    Masahisa Kojima <masahisa.kojima@linaro.org>
+ M:    Jassi Brar <jaswinder.singh@linaro.org>
+ L:    linux-spi@vger.kernel.org
+ S:    Maintained
+ F:    drivers/spi/spi-synquacer.c
+ F:    Documentation/devicetree/bindings/spi/spi-synquacer.txt
  SOLIDRUN CLEARFOG SUPPORT
  M:    Russell King <linux@armlinux.org.uk>
  S:    Maintained
@@@ -14692,7 -14984,7 +14978,7 @@@ M:   Mattia Dongili <malattia@linux.it
  L:    platform-driver-x86@vger.kernel.org
  W:    http://www.linux.it/~malattia/wiki/index.php/Sony_drivers
  S:    Maintained
- F:    Documentation/laptops/sony-laptop.txt
+ F:    Documentation/admin-guide/laptops/sony-laptop.rst
  F:    drivers/char/sonypi.c
  F:    drivers/platform/x86/sony-laptop.c
  F:    include/linux/sony-laptop.h
@@@ -14920,6 -15212,17 +15206,17 @@@ L: linux-erofs@lists.ozlabs.or
  S:    Maintained
  F:    drivers/staging/erofs/
  
+ STAGING - FIELDBUS SUBSYSTEM
+ M:    Sven Van Asbroeck <TheSven73@gmail.com>
+ S:    Maintained
+ F:    drivers/staging/fieldbus/*
+ F:    drivers/staging/fieldbus/Documentation/
+ STAGING - HMS ANYBUS-S BUS
+ M:    Sven Van Asbroeck <TheSven73@gmail.com>
+ S:    Maintained
+ F:    drivers/staging/fieldbus/anybuss/
  STAGING - INDUSTRIAL IO
  M:    Jonathan Cameron <jic23@kernel.org>
  L:    linux-iio@vger.kernel.org
@@@ -15099,7 -15402,7 +15396,7 @@@ SVGA HANDLIN
  M:    Martin Mares <mj@ucw.cz>
  L:    linux-video@atrey.karlin.mff.cuni.cz
  S:    Maintained
- F:    Documentation/svga.txt
+ F:    Documentation/admin-guide/svga.rst
  F:    arch/x86/boot/video*
  
  SWIOTLB SUBSYSTEM
@@@ -15136,7 -15439,7 +15433,7 @@@ F:   drivers/dma-buf/dma-fence
  F:    drivers/dma-buf/sw_sync.c
  F:    include/linux/sync_file.h
  F:    include/uapi/linux/sync_file.h
- F:    Documentation/sync_file.txt
+ F:    Documentation/driver-api/sync_file.rst
  T:    git git://anongit.freedesktop.org/drm/drm-misc
  
  SYNOPSYS ARC ARCHITECTURE
@@@ -15458,6 -15761,7 +15755,7 @@@ F:   include/media/i2c/tw9910.
  
  TEE SUBSYSTEM
  M:    Jens Wiklander <jens.wiklander@linaro.org>
+ L:    tee-dev@lists.linaro.org
  S:    Maintained
  F:    include/linux/tee_drv.h
  F:    include/uapi/linux/tee.h
@@@ -15487,6 -15791,7 +15785,7 @@@ F:   drivers/dma/tegra
  
  TEGRA I2C DRIVER
  M:    Laxman Dewangan <ldewangan@nvidia.com>
+ R:    Dmitry Osipenko <digetx@gmail.com>
  S:    Supported
  F:    drivers/i2c/busses/i2c-tegra.c
  
@@@ -15612,7 -15917,7 +15911,7 @@@ M:   Viresh Kumar <viresh.kumar@linaro.or
  M:    Javi Merino <javi.merino@kernel.org>
  L:    linux-pm@vger.kernel.org
  S:    Supported
- F:    Documentation/thermal/cpu-cooling-api.txt
+ F:    Documentation/thermal/cpu-cooling-api.rst
  F:    drivers/thermal/cpu_cooling.c
  F:    include/linux/cpu_cooling.h
  
@@@ -15756,7 -16061,7 +16055,7 @@@ F:   sound/soc/codecs/isabelle
  TI LP855x BACKLIGHT DRIVER
  M:    Milo Kim <milo.kim@ti.com>
  S:    Maintained
- F:    Documentation/backlight/lp855x-driver.txt
+ F:    Documentation/driver-api/backlight/lp855x-driver.rst
  F:    drivers/video/backlight/lp855x_bl.c
  F:    include/linux/platform_data/lp855x.h
  
@@@ -16020,7 -16325,7 +16319,7 @@@ M:   Greg Kroah-Hartman <gregkh@linuxfoun
  M:    Jiri Slaby <jslaby@suse.com>
  S:    Supported
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git
- F:    Documentation/serial/
+ F:    Documentation/driver-api/serial/
  F:    drivers/tty/
  F:    drivers/tty/serial/serial_core.c
  F:    include/linux/serial_core.h
@@@ -16240,7 -16545,7 +16539,7 @@@ USB ACM DRIVE
  M:    Oliver Neukum <oneukum@suse.com>
  L:    linux-usb@vger.kernel.org
  S:    Maintained
- F:    Documentation/usb/acm.txt
+ F:    Documentation/usb/acm.rst
  F:    drivers/usb/class/cdc-acm.*
  
  USB AR5523 WIRELESS DRIVER
@@@ -16293,7 -16598,7 +16592,7 @@@ USB EHCI DRIVE
  M:    Alan Stern <stern@rowland.harvard.edu>
  L:    linux-usb@vger.kernel.org
  S:    Maintained
- F:    Documentation/usb/ehci.txt
+ F:    Documentation/usb/ehci.rst
  F:    drivers/usb/host/ehci*
  
  USB GADGET/PERIPHERAL SUBSYSTEM
@@@ -16311,7 -16616,7 +16610,7 @@@ M:   Benjamin Tissoires <benjamin.tissoir
  L:    linux-usb@vger.kernel.org
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git
  S:    Maintained
- F:    Documentation/hid/hiddev.txt
+ F:    Documentation/hid/hiddev.rst
  F:    drivers/hid/usbhid/
  
  USB INTEL XHCI ROLE MUX DRIVER
@@@ -16367,7 -16672,7 +16666,7 @@@ USB OHCI DRIVE
  M:    Alan Stern <stern@rowland.harvard.edu>
  L:    linux-usb@vger.kernel.org
  S:    Maintained
- F:    Documentation/usb/ohci.txt
+ F:    Documentation/usb/ohci.rst
  F:    drivers/usb/host/ohci*
  
  USB OTG FSM (Finite State Machine)
@@@ -16383,7 -16688,7 +16682,7 @@@ M:   Shuah Khan <shuah@kernel.org
  M:    Shuah Khan <skhan@linuxfoundation.org>
  L:    linux-usb@vger.kernel.org
  S:    Maintained
- F:    Documentation/usb/usbip_protocol.txt
+ F:    Documentation/usb/usbip_protocol.rst
  F:    drivers/usb/usbip/
  F:    tools/usb/usbip/
  F:    tools/testing/selftests/drivers/usb/usbip/
@@@ -16431,7 -16736,7 +16730,7 @@@ M:   Johan Hovold <johan@kernel.org
  L:    linux-usb@vger.kernel.org
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git
  S:    Maintained
- F:    Documentation/usb/usb-serial.txt
+ F:    Documentation/usb/usb-serial.rst
  F:    drivers/usb/serial/
  F:    include/linux/usb/serial.h
  
@@@ -16560,7 -16865,7 +16859,7 @@@ W:   http://user-mode-linux.sourceforge.n
  Q:    https://patchwork.ozlabs.org/project/linux-um/list/
  T:    git git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml.git
  S:    Maintained
- F:    Documentation/virtual/uml/
+ F:    Documentation/virt/uml/
  F:    arch/um/
  F:    arch/x86/um/
  F:    fs/hostfs/
@@@ -16610,7 -16915,7 +16909,7 @@@ M:   Michal Januszewski <spock@gentoo.org
  L:    linux-fbdev@vger.kernel.org
  W:    https://github.com/mjanusz/v86d
  S:    Maintained
- F:    Documentation/fb/uvesafb.txt
+ F:    Documentation/fb/uvesafb.rst
  F:    drivers/video/fbdev/uvesafb.*
  
  VF610 NAND DRIVER
@@@ -16631,7 -16936,7 +16930,7 @@@ R:   Cornelia Huck <cohuck@redhat.com
  L:    kvm@vger.kernel.org
  T:    git git://github.com/awilliam/linux-vfio.git
  S:    Maintained
- F:    Documentation/vfio.txt
+ F:    Documentation/driver-api/vfio.rst
  F:    drivers/vfio/
  F:    include/linux/vfio.h
  F:    include/uapi/linux/vfio.h
@@@ -16640,7 -16945,7 +16939,7 @@@ VFIO MEDIATED DEVICE DRIVER
  M:    Kirti Wankhede <kwankhede@nvidia.com>
  L:    kvm@vger.kernel.org
  S:    Maintained
- F:    Documentation/vfio-mediated-device.txt
+ F:    Documentation/driver-api/vfio-mediated-device.rst
  F:    drivers/vfio/mdev/
  F:    include/linux/mdev.h
  F:    samples/vfio-mdev/
@@@ -16685,7 -16990,7 +16984,7 @@@ S:   Maintaine
  F:    drivers/net/ethernet/via/via-velocity.*
  
  VICODEC VIRTUAL CODEC DRIVER
- M:    Hans Verkuil <hans.verkuil@cisco.com>
+ M:    Hans Verkuil <hverkuil-cisco@xs4all.nl>
  L:    linux-media@vger.kernel.org
  T:    git git://linuxtv.org/media_tree.git
  W:    https://linuxtv.org
@@@ -16708,6 -17013,7 +17007,7 @@@ VIDEOBUF2 FRAMEWOR
  M:    Pawel Osciak <pawel@osciak.com>
  M:    Marek Szyprowski <m.szyprowski@samsung.com>
  M:    Kyungmin Park <kyungmin.park@samsung.com>
+ R:    Tomasz Figa <tfiga@chromium.org>
  L:    linux-media@vger.kernel.org
  S:    Maintained
  F:    drivers/media/common/videobuf2/*
@@@ -16827,6 -17133,13 +17127,13 @@@ S: Maintaine
  F:    drivers/virtio/virtio_input.c
  F:    include/uapi/linux/virtio_input.h
  
+ VIRTIO IOMMU DRIVER
+ M:    Jean-Philippe Brucker <jean-philippe@linaro.org>
+ L:    virtualization@lists.linux-foundation.org
+ S:    Maintained
+ F:    drivers/iommu/virtio-iommu.c
+ F:    include/uapi/linux/virtio_iommu.h
  VIRTUAL BOX GUEST DEVICE DRIVER
  M:    Hans de Goede <hdegoede@redhat.com>
  M:    Arnd Bergmann <arnd@arndb.de>
@@@ -16870,7 -17183,6 +17177,6 @@@ F:   drivers/vme
  F:    include/linux/vme*
  
  VMWARE BALLOON DRIVER
- M:    Julien Freche <jfreche@vmware.com>
  M:    Nadav Amit <namit@vmware.com>
  M:    "VMware, Inc." <pv-drivers@vmware.com>
  L:    linux-kernel@vger.kernel.org
@@@ -16878,7 -17190,8 +17184,8 @@@ S:   Maintaine
  F:    drivers/misc/vmw_balloon.c
  
  VMWARE HYPERVISOR INTERFACE
- M:    Alok Kataria <akataria@vmware.com>
+ M:    Thomas Hellstrom <thellstrom@vmware.com>
+ M:    "VMware, Inc." <pv-drivers@vmware.com>
  L:    virtualization@lists.linux-foundation.org
  S:    Supported
  F:    arch/x86/kernel/cpu/vmware.c
@@@ -17266,6 -17579,7 +17573,7 @@@ N:   xd
  XDP SOCKETS (AF_XDP)
  M:    Björn Töpel <bjorn.topel@intel.com>
  M:    Magnus Karlsson <magnus.karlsson@intel.com>
+ R:    Jonathan Lemon <jonathan.lemon@gmail.com>
  L:    netdev@vger.kernel.org
  L:    bpf@vger.kernel.org
  S:    Maintained
@@@ -17358,8 -17672,13 +17666,13 @@@ L: linux-xfs@vger.kernel.or
  W:    http://xfs.org/
  T:    git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git
  S:    Supported
- F:    Documentation/filesystems/xfs.txt
+ F:    Documentation/admin-guide/xfs.rst
+ F:    Documentation/ABI/testing/sysfs-fs-xfs
+ F:    Documentation/filesystems/xfs-delayed-logging-design.txt
+ F:    Documentation/filesystems/xfs-self-describing-metadata.txt
  F:    fs/xfs/
+ F:    include/uapi/linux/dqblk_xfs.h
+ F:    include/uapi/linux/fsmap.h
  
  XILINX AXI ETHERNET DRIVER
  M:    Anirudha Sarangi <anirudh@xilinx.com>
@@@ -17479,6 -17798,12 +17792,12 @@@ Q: https://patchwork.linuxtv.org/projec
  S:    Maintained
  F:    drivers/media/dvb-frontends/zd1301_demod*
  
+ ZHAOXIN PROCESSOR SUPPORT
+ M:    Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
+ L:    linux-kernel@vger.kernel.org
+ S:    Maintained
+ F:    arch/x86/kernel/cpu/zhaoxin.c
  ZPOOL COMPRESSED PAGE STORAGE API
  M:    Dan Streetman <ddstreet@ieee.org>
  L:    linux-mm@kvack.org
@@@ -17501,7 -17826,7 +17820,7 @@@ R:   Sergey Senozhatsky <sergey.senozhats
  L:    linux-kernel@vger.kernel.org
  S:    Maintained
  F:    drivers/block/zram/
- F:    Documentation/blockdev/zram.txt
+ F:    Documentation/admin-guide/blockdev/zram.rst
  
  ZS DECSTATION Z85C30 SERIAL DRIVER
  M:    "Maciej W. Rozycki" <macro@linux-mips.org>
index 018d1d3478962d0b2126e99525eb02110ee5d93d,e51b48ac48eb151fcf72d11a4bdf15b9a06dda0e..ab92b24ac4ff43503decdac2e7ab9a9ff028c706
@@@ -444,22 -444,6 +444,22 @@@ static int amdgpu_move_blit(struct ttm_
        if (r)
                goto error;
  
 +      /* clear the space being freed */
 +      if (old_mem->mem_type == TTM_PL_VRAM &&
 +          (ttm_to_amdgpu_bo(bo)->flags &
 +           AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 +              struct dma_fence *wipe_fence = NULL;
 +
 +              r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 +                                     NULL, &wipe_fence);
 +              if (r) {
 +                      goto error;
 +              } else if (wipe_fence) {
 +                      dma_fence_put(fence);
 +                      fence = wipe_fence;
 +              }
 +      }
 +
        /* Always block for VM page tables before committing the new location */
        if (bo->type == ttm_bo_type_kernel)
                r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
@@@ -835,7 -819,7 +835,7 @@@ int amdgpu_ttm_tt_get_user_pages(struc
                                0 : range->flags[HMM_PFN_WRITE];
        range->pfn_flags_mask = 0;
        range->pfns = pfns;
-       hmm_range_register(range, mm, start,
+       hmm_range_register(range, mirror, start,
                           start + ttm->num_pages * PAGE_SIZE, PAGE_SHIFT);
  
  retry:
@@@ -1615,7 -1599,6 +1615,7 @@@ static struct ttm_bo_driver amdgpu_bo_d
        .move = &amdgpu_bo_move,
        .verify_access = &amdgpu_verify_access,
        .move_notify = &amdgpu_bo_move_notify,
 +      .release_notify = &amdgpu_bo_release_notify,
        .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
        .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
        .io_mem_free = &amdgpu_ttm_io_mem_free,
index ec71e2a7d7b71c0af24f9e0a6f2818b3c5b06029,32773b7523d204a8b29266931fb4a9e577c571a4..43427a3148b74094c6b89c7514b6148b97b86801
   * OTHER DEALINGS IN THE SOFTWARE.
   *
   */
 +
 +#include <linux/delay.h>
 +#include <linux/kernel.h>
  #include <linux/firmware.h>
 -#include <drm/drmP.h>
 +#include <linux/module.h>
 +#include <linux/pci.h>
  #include "amdgpu.h"
  #include "amdgpu_gfx.h"
  #include "amdgpu_psp.h"
@@@ -60,9 -56,6 +60,9 @@@
  #define F32_CE_PROGRAM_RAM_SIZE               65536
  #define RLCG_UCODE_LOADING_START_ADDRESS      0x00002000L
  
 +#define mmCGTT_GS_NGG_CLK_CTRL        0x5087
 +#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX       1
 +
  MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
  MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
  MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@@ -70,20 -63,6 +70,20 @@@ MODULE_FIRMWARE("amdgpu/navi10_mec.bin"
  MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
  MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
  
 +MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 +MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 +MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 +MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 +MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 +MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 +
 +MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 +MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 +MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 +MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 +MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 +MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 +
  static const struct soc15_reg_golden golden_settings_gc_10_1[] =
  {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@@ -130,99 -109,6 +130,99 @@@ static const struct soc15_reg_golden go
        /* Pending on emulation bring up */
  };
  
 +static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
 +{
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
 +};
 +
 +static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
 +{
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
 +};
 +
 +static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
 +{
 +      /* Pending on emulation bring up */
 +};
 +
 +static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
 +{
 +      /* Pending on emulation bring up */
 +};
 +
  #define DEFAULT_SH_MEM_CONFIG \
        ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
         (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@@ -364,22 -250,6 +364,22 @@@ static void gfx_v10_0_init_golden_regis
                                                golden_settings_gc_10_0_nv10,
                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
                break;
 +      case CHIP_NAVI14:
 +              soc15_program_register_sequence(adev,
 +                                              golden_settings_gc_10_1_1,
 +                                              (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
 +              soc15_program_register_sequence(adev,
 +                                              golden_settings_gc_10_1_nv14,
 +                                              (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
 +              break;
 +      case CHIP_NAVI12:
 +              soc15_program_register_sequence(adev,
 +                                              golden_settings_gc_10_1_2,
 +                                              (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
 +              soc15_program_register_sequence(adev,
 +                                              golden_settings_gc_10_1_2_nv12,
 +                                              (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
 +              break;
        default:
                break;
        }
@@@ -461,7 -331,7 +461,7 @@@ static int gfx_v10_0_ring_test_ring(str
                if (amdgpu_emu_mode == 1)
                        msleep(1);
                else
 -                      DRM_UDELAY(1);
 +                      udelay(1);
        }
        if (i < adev->usec_timeout) {
                if (amdgpu_emu_mode == 1)
@@@ -611,12 -481,6 +611,12 @@@ static int gfx_v10_0_init_microcode(str
        case CHIP_NAVI10:
                chip_name = "navi10";
                break;
 +      case CHIP_NAVI14:
 +              chip_name = "navi14";
 +              break;
 +      case CHIP_NAVI12:
 +              chip_name = "navi12";
 +              break;
        default:
                BUG();
        }
@@@ -1162,8 -1026,6 +1162,8 @@@ static void gfx_v10_0_gpu_early_init(st
  
        switch (adev->asic_type) {
        case CHIP_NAVI10:
 +      case CHIP_NAVI14:
 +      case CHIP_NAVI12:
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@@ -1271,8 -1133,6 +1271,8 @@@ static int gfx_v10_0_sw_init(void *hand
  
        switch (adev->asic_type) {
        case CHIP_NAVI10:
 +      case CHIP_NAVI14:
 +      case CHIP_NAVI12:
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 2;
                adev->gfx.me.num_queue_per_pipe = 1;
@@@ -1581,27 -1441,17 +1581,36 @@@ static void gfx_v10_0_init_compute_vmid
        }
        nv_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+       }
  }
  
 +static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
 +      }
 +}
 +
 +
  static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
  {
        int i, j, k;
        u32 utcl_invreq_disable = 0;
        /*
         * GCRD_TARGETS_DISABLE field contains
 -       * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
 +       * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
 +       * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
         */
        u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
                2 * max_wgp_per_sh + /* TCP */
                4); /* GL1C */
        /*
         * UTCL1_UTCL0_INVREQ_DISABLE field contains
 -       * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
 +       * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
 +       * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
         */
        u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
                2 * max_wgp_per_sh + /* TCP */
                4 + /* RMI */
                1); /* SQG */
  
 -      if (adev->asic_type == CHIP_NAVI10) {
 +      if (adev->asic_type == CHIP_NAVI10 ||
 +          adev->asic_type == CHIP_NAVI14 ||
 +          adev->asic_type == CHIP_NAVI12) {
                mutex_lock(&adev->grbm_idx_mutex);
                for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
                        for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
@@@ -1689,7 -1535,7 +1698,7 @@@ static void gfx_v10_0_constants_init(st
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */
        mutex_lock(&adev->srbm_mutex);
 -      for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
 +      for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
                nv_grbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
        mutex_unlock(&adev->srbm_mutex);
  
        gfx_v10_0_init_compute_vmid(adev);
 +      gfx_v10_0_init_gds_vmid(adev);
  
  }
  
@@@ -1779,9 -1624,9 +1788,9 @@@ static void gfx_v10_0_rlc_smu_handshake
                 * hence no handshake between SMU & RLC
                 * GFXOFF will be disabled
                 */
 -              rlc_pg_cntl |= 0x80000;
 +              rlc_pg_cntl |= 0x800000;
        } else
 -              rlc_pg_cntl &= ~0x80000;
 +              rlc_pg_cntl &= ~0x800000;
        WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
  }
  
@@@ -4192,7 -4037,6 +4201,7 @@@ static int gfx_v10_0_set_powergating_st
        bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
        switch (adev->asic_type) {
        case CHIP_NAVI10:
 +      case CHIP_NAVI14:
                if (!enable) {
                        amdgpu_gfx_off_ctrl(adev, false);
                        cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
@@@ -4212,8 -4056,6 +4221,8 @@@ static int gfx_v10_0_set_clockgating_st
  
        switch (adev->asic_type) {
        case CHIP_NAVI10:
 +      case CHIP_NAVI14:
 +      case CHIP_NAVI12:
                gfx_v10_0_update_gfx_clock_gating(adev,
                                                 state == AMD_CG_STATE_GATE ? true : false);
                break;
@@@ -4620,7 -4462,7 +4629,7 @@@ static int gfx_v10_0_ring_preempt_ib(st
                if (ring->trail_seq ==
                    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
                        break;
 -              DRM_UDELAY(1);
 +              udelay(1);
        }
  
        if (i >= adev->usec_timeout) {
@@@ -4778,6 -4620,7 +4787,7 @@@ gfx_v10_0_set_gfx_eop_interrupt_state(s
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
                                            TIME_STAMP_INT_ENABLE, 0);
                WREG32(cp_int_cntl_reg, cp_int_cntl);
+               break;
        case AMDGPU_IRQ_STATE_ENABLE:
                cp_int_cntl = RREG32(cp_int_cntl_reg);
                cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
@@@ -5093,7 -4936,7 +5103,7 @@@ static const struct amdgpu_ring_funcs g
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
 -      .vmhub = AMDGPU_GFXHUB,
 +      .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
        .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
        .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
@@@ -5144,7 -4987,7 +5154,7 @@@ static const struct amdgpu_ring_funcs g
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
 -      .vmhub = AMDGPU_GFXHUB,
 +      .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v10_0_ring_get_rptr_compute,
        .get_wptr = gfx_v10_0_ring_get_wptr_compute,
        .set_wptr = gfx_v10_0_ring_set_wptr_compute,
@@@ -5177,7 -5020,7 +5187,7 @@@ static const struct amdgpu_ring_funcs g
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
 -      .vmhub = AMDGPU_GFXHUB,
 +      .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v10_0_ring_get_rptr_compute,
        .get_wptr = gfx_v10_0_ring_get_wptr_compute,
        .set_wptr = gfx_v10_0_ring_set_wptr_compute,
@@@ -5254,8 -5097,6 +5264,8 @@@ static void gfx_v10_0_set_rlc_funcs(str
  {
        switch (adev->asic_type) {
        case CHIP_NAVI10:
 +      case CHIP_NAVI14:
 +      case CHIP_NAVI12:
                adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
                break;
        default:
index 53eee129b168132ed5914144e17ee3f71a9ec6cf,21187275dfd37e496db7de2de3f21f2518a606f9..791ba398f007ef17e1330fd6160ba69d7f7d0043
@@@ -1879,26 -1879,17 +1879,35 @@@ static void gfx_v7_0_init_compute_vmid(
        }
        cik_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+       }
  }
  
 +static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
 +      }
 +}
 +
  static void gfx_v7_0_config_init(struct amdgpu_device *adev)
  {
        adev->gfx.config.double_offchip_lds_buf = 1;
@@@ -1977,7 -1968,6 +1986,7 @@@ static void gfx_v7_0_constants_init(str
        mutex_unlock(&adev->srbm_mutex);
  
        gfx_v7_0_init_compute_vmid(adev);
 +      gfx_v7_0_init_gds_vmid(adev);
  
        WREG32(mmSX_DEBUG_1, 0x20);
  
index 3f866107d38335754814b999c6c38b548e1bab23,751567f78567357c0099cf426c550fe7d9d72b3f..87dd55e9d72b2fe7d8323f8fef33e9024b2fc03d
@@@ -1321,39 -1321,6 +1321,39 @@@ static int gfx_v8_0_rlc_init(struct amd
        return 0;
  }
  
 +static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
 +{
 +      int r;
 +
 +      r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
 +      if (unlikely(r != 0))
 +              return r;
 +
 +      r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
 +                      AMDGPU_GEM_DOMAIN_VRAM);
 +      if (!r)
 +              adev->gfx.rlc.clear_state_gpu_addr =
 +                      amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
 +
 +      amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 +
 +      return r;
 +}
 +
 +static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
 +{
 +      int r;
 +
 +      if (!adev->gfx.rlc.clear_state_obj)
 +              return;
 +
 +      r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
 +      if (likely(r == 0)) {
 +              amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
 +              amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 +      }
 +}
 +
  static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
  {
        amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@@ -3739,26 -3706,17 +3739,35 @@@ static void gfx_v8_0_init_compute_vmid(
        }
        vi_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[i].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+       }
  }
  
 +static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
 +              WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
 +      }
 +}
 +
  static void gfx_v8_0_config_init(struct amdgpu_device *adev)
  {
        switch (adev->asic_type) {
@@@ -3825,7 -3783,6 +3834,7 @@@ static void gfx_v8_0_constants_init(str
        mutex_unlock(&adev->srbm_mutex);
  
        gfx_v8_0_init_compute_vmid(adev);
 +      gfx_v8_0_init_gds_vmid(adev);
  
        mutex_lock(&adev->grbm_idx_mutex);
        /*
@@@ -4828,10 -4785,6 +4837,10 @@@ static int gfx_v8_0_hw_init(void *handl
        gfx_v8_0_init_golden_registers(adev);
        gfx_v8_0_constants_init(adev);
  
 +      r = gfx_v8_0_csb_vram_pin(adev);
 +      if (r)
 +              return r;
 +
        r = adev->gfx.rlc.funcs->resume(adev);
        if (r)
                return r;
@@@ -4948,9 -4901,6 +4957,9 @@@ static int gfx_v8_0_hw_fini(void *handl
        else
                pr_err("rlc is busy, skip halt rlc\n");
        amdgpu_gfx_rlc_exit_safe_mode(adev);
 +
 +      gfx_v8_0_csb_vram_unpin(adev);
 +
        return 0;
  }
  
index 0951b91180c424b56aa0bb5edbcb83530ee775e3,1cf639a511783c9cb1280f86a6ddbc3a5577c349..52a6fd12e26655fd50731d864c0d8101113ceeff
@@@ -104,390 -104,6 +104,390 @@@ MODULE_FIRMWARE("amdgpu/raven2_mec2.bin
  MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
  MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
  
 +MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
 +MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
 +MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
 +
 +#define mmTCP_CHAN_STEER_0_ARCT                                                               0x0b03
 +#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX                                                      0
 +#define mmTCP_CHAN_STEER_1_ARCT                                                               0x0b04
 +#define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX                                                      0
 +#define mmTCP_CHAN_STEER_2_ARCT                                                               0x0b09
 +#define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX                                                      0
 +#define mmTCP_CHAN_STEER_3_ARCT                                                               0x0b0a
 +#define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX                                                      0
 +#define mmTCP_CHAN_STEER_4_ARCT                                                               0x0b0b
 +#define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX                                                      0
 +#define mmTCP_CHAN_STEER_5_ARCT                                                               0x0b0c
 +#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX                                                      0
 +
 +enum ta_ras_gfx_subblock {
 +      /*CPC*/
 +      TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
 +      TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
 +      TA_RAS_BLOCK__GFX_CPC_UCODE,
 +      TA_RAS_BLOCK__GFX_DC_STATE_ME1,
 +      TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
 +      TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
 +      TA_RAS_BLOCK__GFX_DC_STATE_ME2,
 +      TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
 +      TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 +      TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
 +      /* CPF*/
 +      TA_RAS_BLOCK__GFX_CPF_INDEX_START,
 +      TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
 +      TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
 +      TA_RAS_BLOCK__GFX_CPF_TAG,
 +      TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
 +      /* CPG*/
 +      TA_RAS_BLOCK__GFX_CPG_INDEX_START,
 +      TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
 +      TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
 +      TA_RAS_BLOCK__GFX_CPG_TAG,
 +      TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
 +      /* GDS*/
 +      TA_RAS_BLOCK__GFX_GDS_INDEX_START,
 +      TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
 +      TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
 +      TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
 +      TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
 +      TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 +      TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 +      /* SPI*/
 +      TA_RAS_BLOCK__GFX_SPI_SR_MEM,
 +      /* SQ*/
 +      TA_RAS_BLOCK__GFX_SQ_INDEX_START,
 +      TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
 +      TA_RAS_BLOCK__GFX_SQ_LDS_D,
 +      TA_RAS_BLOCK__GFX_SQ_LDS_I,
 +      TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
 +      TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
 +      /* SQC (3 ranges)*/
 +      TA_RAS_BLOCK__GFX_SQC_INDEX_START,
 +      /* SQC range 0*/
 +      TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
 +      TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 +              TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 +      TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
 +              TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 +      /* SQC range 1*/
 +      TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 +              TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
 +              TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 +      /* SQC range 2*/
 +      TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 +              TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
 +              TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 +      TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
 +      /* TA*/
 +      TA_RAS_BLOCK__GFX_TA_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
 +      TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
 +      TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
 +      TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
 +      TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
 +      /* TCA*/
 +      TA_RAS_BLOCK__GFX_TCA_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 +      TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 +      /* TCC (5 sub-ranges)*/
 +      TA_RAS_BLOCK__GFX_TCC_INDEX_START,
 +      /* TCC range 0*/
 +      TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
 +      TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 +      TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 +      TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 +      TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 +      TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 +      TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 +      TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 +      TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 +      /* TCC range 1*/
 +      TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
 +      TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
 +      TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 +      TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
 +              TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 +      /* TCC range 2*/
 +      TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
 +      TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
 +      TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 +      TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 +      TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 +      TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 +      TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 +      TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 +      TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 +      TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
 +              TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 +      /* TCC range 3*/
 +      TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
 +      TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
 +      TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 +      TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
 +              TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 +      /* TCC range 4*/
 +      TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
 +      TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 +              TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
 +      TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 +      TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
 +              TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 +      TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
 +      /* TCI*/
 +      TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 +      /* TCP*/
 +      TA_RAS_BLOCK__GFX_TCP_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 +      TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 +      TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
 +      TA_RAS_BLOCK__GFX_TCP_DB_RAM,
 +      TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 +      TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 +      TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 +      /* TD*/
 +      TA_RAS_BLOCK__GFX_TD_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
 +      TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 +      TA_RAS_BLOCK__GFX_TD_CS_FIFO,
 +      TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
 +      /* EA (3 sub-ranges)*/
 +      TA_RAS_BLOCK__GFX_EA_INDEX_START,
 +      /* EA range 0*/
 +      TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
 +      TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
 +      TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 +      TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 +      TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 +      TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 +      TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 +      TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 +      TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 +      TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 +      /* EA range 1*/
 +      TA_RAS_BLOCK__GFX_EA_INDEX1_START,
 +      TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
 +      TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 +      TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 +      TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 +      TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 +      TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 +      TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 +      TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 +      /* EA range 2*/
 +      TA_RAS_BLOCK__GFX_EA_INDEX2_START,
 +      TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
 +      TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 +      TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 +      TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 +      TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 +      TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
 +      /* UTC VM L2 bank*/
 +      TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 +      /* UTC VM walker*/
 +      TA_RAS_BLOCK__UTC_VML2_WALKER,
 +      /* UTC ATC L2 2MB cache*/
 +      TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 +      /* UTC ATC L2 4KB cache*/
 +      TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 +      TA_RAS_BLOCK__GFX_MAX
 +};
 +
 +struct ras_gfx_subblock {
 +      unsigned char *name;
 +      int ta_subblock;
 +      int hw_supported_error_type;
 +      int sw_supported_error_type;
 +};
 +
 +#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)                             \
 +      [AMDGPU_RAS_BLOCK__##subblock] = {                                     \
 +              #subblock,                                                     \
 +              TA_RAS_BLOCK__##subblock,                                      \
 +              ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)),                  \
 +              (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)),                  \
 +      }
 +
 +static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
 +                           0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
 +                           0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
 +                           0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
 +                           1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
 +                           0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
 +                           0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
 +                           0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
 +                           0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
 +                           1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
 +                           1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
 +                           1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
 +                           0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
 +                           0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
 +      AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
 +};
 +
  static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  {
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
@@@ -655,18 -271,6 +655,18 @@@ static const struct soc15_reg_golden go
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
  };
  
 +static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
 +{
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
 +      SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
 +};
 +
  static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
  {
        mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
@@@ -706,21 -310,19 +706,21 @@@ static uint64_t gfx_v9_0_get_gpu_clock_
  static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
  static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
  static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
 +static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
 +                                        void *ras_error_status);
 +static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
 +                                   void *inject_if);
  
  static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
  {
        switch (adev->asic_type) {
        case CHIP_VEGA10:
 -              if (!amdgpu_virt_support_skip_setting(adev)) {
 -                      soc15_program_register_sequence(adev,
 -                                                       golden_settings_gc_9_0,
 -                                                       ARRAY_SIZE(golden_settings_gc_9_0));
 -                      soc15_program_register_sequence(adev,
 -                                                       golden_settings_gc_9_0_vg10,
 -                                                       ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 -              }
 +              soc15_program_register_sequence(adev,
 +                                              golden_settings_gc_9_0,
 +                                              ARRAY_SIZE(golden_settings_gc_9_0));
 +              soc15_program_register_sequence(adev,
 +                                              golden_settings_gc_9_0_vg10,
 +                                              ARRAY_SIZE(golden_settings_gc_9_0_vg10));
                break;
        case CHIP_VEGA12:
                soc15_program_register_sequence(adev,
                                                golden_settings_gc_9_0_vg20,
                                                ARRAY_SIZE(golden_settings_gc_9_0_vg20));
                break;
 +      case CHIP_ARCTURUS:
 +              soc15_program_register_sequence(adev,
 +                                              golden_settings_gc_9_4_1_arct,
 +                                              ARRAY_SIZE(golden_settings_gc_9_4_1_arct));
 +              break;
        case CHIP_RAVEN:
                soc15_program_register_sequence(adev, golden_settings_gc_9_1,
                                                ARRAY_SIZE(golden_settings_gc_9_1));
                break;
        }
  
 -      soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 -                                      (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 +      if (adev->asic_type != CHIP_ARCTURUS)
 +              soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 +                                              (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
  }
  
  static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
@@@ -1014,14 -610,44 +1014,14 @@@ static void gfx_v9_0_check_if_need_gfxo
        }
  }
  
 -static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 +static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
 +                                        const char *chip_name)
  {
 -      const char *chip_name;
        char fw_name[30];
        int err;
        struct amdgpu_firmware_info *info = NULL;
        const struct common_firmware_header *header = NULL;
        const struct gfx_firmware_header_v1_0 *cp_hdr;
 -      const struct rlc_firmware_header_v2_0 *rlc_hdr;
 -      unsigned int *tmp = NULL;
 -      unsigned int i = 0;
 -      uint16_t version_major;
 -      uint16_t version_minor;
 -      uint32_t smu_version;
 -
 -      DRM_DEBUG("\n");
 -
 -      switch (adev->asic_type) {
 -      case CHIP_VEGA10:
 -              chip_name = "vega10";
 -              break;
 -      case CHIP_VEGA12:
 -              chip_name = "vega12";
 -              break;
 -      case CHIP_VEGA20:
 -              chip_name = "vega20";
 -              break;
 -      case CHIP_RAVEN:
 -              if (adev->rev_id >= 8)
 -                      chip_name = "raven2";
 -              else if (adev->pdev->device == 0x15d8)
 -                      chip_name = "picasso";
 -              else
 -                      chip_name = "raven";
 -              break;
 -      default:
 -              BUG();
 -      }
  
        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
        err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
        adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
        adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  
 +      if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 +              info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 +              info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 +              info->fw = adev->gfx.pfp_fw;
 +              header = (const struct common_firmware_header *)info->fw->data;
 +              adev->firmware.fw_size +=
 +                      ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 +
 +              info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 +              info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 +              info->fw = adev->gfx.me_fw;
 +              header = (const struct common_firmware_header *)info->fw->data;
 +              adev->firmware.fw_size +=
 +                      ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 +
 +              info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 +              info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 +              info->fw = adev->gfx.ce_fw;
 +              header = (const struct common_firmware_header *)info->fw->data;
 +              adev->firmware.fw_size +=
 +                      ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 +      }
 +
 +out:
 +      if (err) {
 +              dev_err(adev->dev,
 +                      "gfx9: Failed to load firmware \"%s\"\n",
 +                      fw_name);
 +              release_firmware(adev->gfx.pfp_fw);
 +              adev->gfx.pfp_fw = NULL;
 +              release_firmware(adev->gfx.me_fw);
 +              adev->gfx.me_fw = NULL;
 +              release_firmware(adev->gfx.ce_fw);
 +              adev->gfx.ce_fw = NULL;
 +      }
 +      return err;
 +}
 +
 +static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
 +                                        const char *chip_name)
 +{
 +      char fw_name[30];
 +      int err;
 +      struct amdgpu_firmware_info *info = NULL;
 +      const struct common_firmware_header *header = NULL;
 +      const struct rlc_firmware_header_v2_0 *rlc_hdr;
 +      unsigned int *tmp = NULL;
 +      unsigned int i = 0;
 +      uint16_t version_major;
 +      uint16_t version_minor;
 +      uint32_t smu_version;
 +
        /*
         * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
         * instead of picasso_rlc.bin.
        if (adev->gfx.rlc.is_rlc_v2_1)
                gfx_v9_0_init_rlc_ext_microcode(adev);
  
 -      snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 -      err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 -      if (err)
 -              goto out;
 -      err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 -      if (err)
 -              goto out;
 -      cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 -      adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 -      adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 -
 -
 -      snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 -      err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 -      if (!err) {
 -              err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 -              if (err)
 -                      goto out;
 -              cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 -              adev->gfx.mec2_fw->data;
 -              adev->gfx.mec2_fw_version =
 -              le32_to_cpu(cp_hdr->header.ucode_version);
 -              adev->gfx.mec2_feature_version =
 -              le32_to_cpu(cp_hdr->ucode_feature_version);
 -      } else {
 -              err = 0;
 -              adev->gfx.mec2_fw = NULL;
 -      }
 -
        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 -              info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 -              info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 -              info->fw = adev->gfx.pfp_fw;
 -              header = (const struct common_firmware_header *)info->fw->data;
 -              adev->firmware.fw_size +=
 -                      ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 -
 -              info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 -              info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 -              info->fw = adev->gfx.me_fw;
 -              header = (const struct common_firmware_header *)info->fw->data;
 -              adev->firmware.fw_size +=
 -                      ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 -
 -              info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 -              info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 -              info->fw = adev->gfx.ce_fw;
 -              header = (const struct common_firmware_header *)info->fw->data;
 -              adev->firmware.fw_size +=
 -                      ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 -
                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
                info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
                info->fw = adev->gfx.rlc_fw;
                        adev->firmware.fw_size +=
                                ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
                }
 +      }
  
 +out:
 +      if (err) {
 +              dev_err(adev->dev,
 +                      "gfx9: Failed to load firmware \"%s\"\n",
 +                      fw_name);
 +              release_firmware(adev->gfx.rlc_fw);
 +              adev->gfx.rlc_fw = NULL;
 +      }
 +      return err;
 +}
 +
 +static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
 +                                        const char *chip_name)
 +{
 +      char fw_name[30];
 +      int err;
 +      struct amdgpu_firmware_info *info = NULL;
 +      const struct common_firmware_header *header = NULL;
 +      const struct gfx_firmware_header_v1_0 *cp_hdr;
 +
 +      snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 +      err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 +      if (err)
 +              goto out;
 +      err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 +      if (err)
 +              goto out;
 +      cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 +      adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 +      adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 +
 +
 +      snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 +      err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 +      if (!err) {
 +              err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 +              if (err)
 +                      goto out;
 +              cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 +              adev->gfx.mec2_fw->data;
 +              adev->gfx.mec2_fw_version =
 +              le32_to_cpu(cp_hdr->header.ucode_version);
 +              adev->gfx.mec2_feature_version =
 +              le32_to_cpu(cp_hdr->ucode_feature_version);
 +      } else {
 +              err = 0;
 +              adev->gfx.mec2_fw = NULL;
 +      }
 +
 +      if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
                info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
                info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
                info->fw = adev->gfx.mec_fw;
                        cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
                        adev->firmware.fw_size +=
                                ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 -                      info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 -                      info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 -                      info->fw = adev->gfx.mec2_fw;
 -                      adev->firmware.fw_size +=
 -                              ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 -              }
  
 +                      /* TODO: Determine if MEC2 JT FW loading can be removed
 +                               for all GFX V9 asic and above */
 +                      if (adev->asic_type != CHIP_ARCTURUS) {
 +                              info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 +                              info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 +                              info->fw = adev->gfx.mec2_fw;
 +                              adev->firmware.fw_size +=
 +                                      ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
 +                                      PAGE_SIZE);
 +                      }
 +              }
        }
  
  out:
                dev_err(adev->dev,
                        "gfx9: Failed to load firmware \"%s\"\n",
                        fw_name);
 -              release_firmware(adev->gfx.pfp_fw);
 -              adev->gfx.pfp_fw = NULL;
 -              release_firmware(adev->gfx.me_fw);
 -              adev->gfx.me_fw = NULL;
 -              release_firmware(adev->gfx.ce_fw);
 -              adev->gfx.ce_fw = NULL;
 -              release_firmware(adev->gfx.rlc_fw);
 -              adev->gfx.rlc_fw = NULL;
                release_firmware(adev->gfx.mec_fw);
                adev->gfx.mec_fw = NULL;
                release_firmware(adev->gfx.mec2_fw);
        return err;
  }
  
 +static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 +{
 +      const char *chip_name;
 +      int r;
 +
 +      DRM_DEBUG("\n");
 +
 +      switch (adev->asic_type) {
 +      case CHIP_VEGA10:
 +              chip_name = "vega10";
 +              break;
 +      case CHIP_VEGA12:
 +              chip_name = "vega12";
 +              break;
 +      case CHIP_VEGA20:
 +              chip_name = "vega20";
 +              break;
 +      case CHIP_RAVEN:
 +              if (adev->rev_id >= 8)
 +                      chip_name = "raven2";
 +              else if (adev->pdev->device == 0x15d8)
 +                      chip_name = "picasso";
 +              else
 +                      chip_name = "raven";
 +              break;
 +      case CHIP_ARCTURUS:
 +              chip_name = "arcturus";
 +              break;
 +      default:
 +              BUG();
 +      }
 +
 +      /* No CPG in Arcturus */
 +      if (adev->asic_type != CHIP_ARCTURUS) {
 +              r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
 +              if (r)
 +                      return r;
 +      }
 +
 +      r = gfx_v9_0_init_rlc_microcode(adev, chip_name);
 +      if (r)
 +              return r;
 +
 +      r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name);
 +      if (r)
 +              return r;
 +
 +      return r;
 +}
 +
  static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
  {
        u32 count = 0;
@@@ -1798,9 -1324,7 +1798,9 @@@ static const struct amdgpu_gfx_funcs gf
        .read_wave_data = &gfx_v9_0_read_wave_data,
        .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
        .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
 -      .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
 +      .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
 +      .ras_error_inject = &gfx_v9_0_ras_error_inject,
 +      .query_ras_error_count = &gfx_v9_0_query_ras_error_count
  };
  
  static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
                else
                        gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
                break;
 +      case CHIP_ARCTURUS:
 +              adev->gfx.config.max_hw_contexts = 8;
 +              adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 +              adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 +              adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 +              adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 +              gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
 +              gb_addr_config &= ~0xf3e777ff;
 +              gb_addr_config |= 0x22014042;
 +              break;
        default:
                BUG();
                break;
@@@ -2139,7 -1653,6 +2139,7 @@@ static int gfx_v9_0_sw_init(void *handl
        case CHIP_VEGA12:
        case CHIP_VEGA20:
        case CHIP_RAVEN:
 +      case CHIP_ARCTURUS:
                adev->gfx.mec.num_mec = 2;
                break;
        default:
@@@ -2405,26 -1918,17 +2405,35 @@@ static void gfx_v9_0_init_compute_vmid(
        }
        soc15_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
+          acccess. These should be enabled by FW for target VMIDs. */
+       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+       }
  }
  
 +static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
 +{
 +      int vmid;
 +
 +      /*
 +       * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 +       * access. Compute VMIDs should be enabled by FW for target VMIDs,
 +       * the driver can enable them for graphics. VMID0 should maintain
 +       * access so that HWS firmware can save/restore entries.
 +       */
 +      for (vmid = 1; vmid < 16; vmid++) {
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
 +              WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
 +      }
 +}
 +
  static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
  {
        u32 tmp;
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */
        mutex_lock(&adev->srbm_mutex);
 -      for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
 +      for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
                soc15_grbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                if (i == 0) {
        mutex_unlock(&adev->srbm_mutex);
  
        gfx_v9_0_init_compute_vmid(adev);
 +      gfx_v9_0_init_gds_vmid(adev);
  }
  
  static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
@@@ -3346,10 -2849,6 +3355,10 @@@ static int gfx_v9_0_mqd_init(struct amd
        mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
        mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
        mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 +      mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
 +      mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
 +      mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
 +      mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
        mqd->compute_misc_reserved = 0x00000003;
  
        mqd->dynamic_cu_mask_addr_lo =
@@@ -3753,12 -3252,10 +3762,12 @@@ static int gfx_v9_0_cp_resume(struct am
                gfx_v9_0_enable_gui_idle_interrupt(adev, false);
  
        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 -              /* legacy firmware loading */
 -              r = gfx_v9_0_cp_gfx_load_microcode(adev);
 -              if (r)
 -                      return r;
 +              if (adev->asic_type != CHIP_ARCTURUS) {
 +                      /* legacy firmware loading */
 +                      r = gfx_v9_0_cp_gfx_load_microcode(adev);
 +                      if (r)
 +                              return r;
 +              }
  
                r = gfx_v9_0_cp_compute_load_microcode(adev);
                if (r)
        if (r)
                return r;
  
 -      r = gfx_v9_0_cp_gfx_resume(adev);
 -      if (r)
 -              return r;
 +      if (adev->asic_type != CHIP_ARCTURUS) {
 +              r = gfx_v9_0_cp_gfx_resume(adev);
 +              if (r)
 +                      return r;
 +      }
  
        r = gfx_v9_0_kcq_resume(adev);
        if (r)
                return r;
  
 -      ring = &adev->gfx.gfx_ring[0];
 -      r = amdgpu_ring_test_helper(ring);
 -      if (r)
 -              return r;
 +      if (adev->asic_type != CHIP_ARCTURUS) {
 +              ring = &adev->gfx.gfx_ring[0];
 +              r = amdgpu_ring_test_helper(ring);
 +              if (r)
 +                      return r;
 +      }
  
        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                ring = &adev->gfx.compute_ring[i];
  
  static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
  {
 -      gfx_v9_0_cp_gfx_enable(adev, enable);
 +      if (adev->asic_type != CHIP_ARCTURUS)
 +              gfx_v9_0_cp_gfx_enable(adev, enable);
        gfx_v9_0_cp_compute_enable(adev, enable);
  }
  
@@@ -3808,8 -3300,7 +3817,8 @@@ static int gfx_v9_0_hw_init(void *handl
        int r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  
 -      gfx_v9_0_init_golden_registers(adev);
 +      if (!amdgpu_sriov_vf(adev))
 +              gfx_v9_0_init_golden_registers(adev);
  
        gfx_v9_0_constants_init(adev);
  
        if (r)
                return r;
  
 -      r = gfx_v9_0_ngg_en(adev);
 -      if (r)
 -              return r;
 +      if (adev->asic_type != CHIP_ARCTURUS) {
 +              r = gfx_v9_0_ngg_en(adev);
 +              if (r)
 +                      return r;
 +      }
  
        return r;
  }
@@@ -3977,9 -3466,8 +3986,9 @@@ static int gfx_v9_0_soft_reset(void *ha
                /* stop the rlc */
                adev->gfx.rlc.funcs->stop(adev);
  
 -              /* Disable GFX parsing/prefetching */
 -              gfx_v9_0_cp_gfx_enable(adev, false);
 +              if (adev->asic_type != CHIP_ARCTURUS)
 +                      /* Disable GFX parsing/prefetching */
 +                      gfx_v9_0_cp_gfx_enable(adev, false);
  
                /* Disable MEC parsing/prefetching */
                gfx_v9_0_cp_compute_enable(adev, false);
@@@ -4322,10 -3810,7 +4331,10 @@@ static int gfx_v9_0_early_init(void *ha
  {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  
 -      adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
 +      if (adev->asic_type == CHIP_ARCTURUS)
 +              adev->gfx.num_gfx_rings = 0;
 +      else
 +              adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
        adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
        gfx_v9_0_set_ring_funcs(adev);
        gfx_v9_0_set_irq_funcs(adev);
  }
  
  static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 +              struct ras_err_data *err_data,
                struct amdgpu_iv_entry *entry);
  
  static int gfx_v9_0_ecc_late_init(void *handle)
@@@ -4846,16 -4330,14 +4855,16 @@@ static void gfx_v9_0_get_clockgating_st
        if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
                *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
  
 -      /* AMD_CG_SUPPORT_GFX_3D_CGCG */
 -      data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
 -      if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
 -              *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
 +      if (adev->asic_type != CHIP_ARCTURUS) {
 +              /* AMD_CG_SUPPORT_GFX_3D_CGCG */
 +              data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
 +              if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
 +                      *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
  
 -      /* AMD_CG_SUPPORT_GFX_3D_CGLS */
 -      if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
 -              *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
 +              /* AMD_CG_SUPPORT_GFX_3D_CGLS */
 +              if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
 +                      *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
 +      }
  }
  
  static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
@@@ -5651,420 -5133,12 +5660,420 @@@ static int gfx_v9_0_priv_inst_irq(struc
  }
  
  static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 +              struct ras_err_data *err_data,
                struct amdgpu_iv_entry *entry)
  {
        /* TODO ue will trigger an interrupt. */
        kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 +      if (adev->gfx.funcs->query_ras_error_count)
 +              adev->gfx.funcs->query_ras_error_count(adev, err_data);
        amdgpu_ras_reset_gpu(adev, 0);
 -      return AMDGPU_RAS_UE;
 +      return AMDGPU_RAS_SUCCESS;
 +}
 +
 +static const struct {
 +      const char *name;
 +      uint32_t ip;
 +      uint32_t inst;
 +      uint32_t seg;
 +      uint32_t reg_offset;
 +      uint32_t per_se_instance;
 +      int32_t num_instance;
 +      uint32_t sec_count_mask;
 +      uint32_t ded_count_mask;
 +} gfx_ras_edc_regs[] = {
 +      { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1,
 +        REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
 +        REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
 +      { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1,
 +        REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT),
 +        REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) },
 +      { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
 +        REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 },
 +      { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
 +        REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 },
 +      { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1,
 +        REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT),
 +        REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) },
 +      { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
 +        REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 },
 +      { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
 +        REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
 +        REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) },
 +      { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1,
 +        REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT),
 +        REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) },
 +      { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1,
 +        REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 },
 +      { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1,
 +        REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 },
 +      { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1,
 +        REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 },
 +      { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC),
 +        REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) },
 +      { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 },
 +      { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
 +        0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
 +        REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
 +      { "GDS_OA_PHY_PHY_CMD_RAM_MEM",
 +        SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
 +        REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
 +      { "GDS_OA_PHY_PHY_DATA_RAM_MEM",
 +        SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 },
 +      { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
 +        SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
 +      { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
 +        SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
 +      { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
 +        SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
 +      { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
 +        SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
 +        REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
 +      { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1,
 +        REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 },
 +      { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
 +        REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
 +      { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 },
 +      { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 },
 +      { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 },
 +      { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 },
 +      { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
 +        REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 },
 +      { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
 +        REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 },
 +      { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
 +        REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
 +      { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
 +        REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
 +      { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
 +        REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
 +      { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
 +        REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
 +      { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
 +        REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
 +      { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 },
 +      { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 },
 +      { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 },
 +      { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 },
 +      { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 },
 +      { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 },
 +      { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 },
 +      { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
 +        REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 },
 +      { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
 +        16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 },
 +      { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
 +        0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
 +        0 },
 +      { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
 +        16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 },
 +      { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
 +        0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
 +        0 },
 +      { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
 +        16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 },
 +      { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72,
 +        REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 },
 +      { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
 +      { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
 +      { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 },
 +      { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 },
 +      { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 },
 +      { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
 +      { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
 +        REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
 +      { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
 +        REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
 +      { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
 +        REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
 +      { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 },
 +      { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT),
 +        REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) },
 +      { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT),
 +        REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) },
 +      { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT),
 +        REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) },
 +      { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT),
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) },
 +      { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT),
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) },
 +      { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT),
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) },
 +      { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT),
 +        REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) },
 +      { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
 +        1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
 +      { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
 +      { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
 +        1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
 +      { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
 +      { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
 +        1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
 +      { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
 +      { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
 +      { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
 +      { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
 +      { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
 +      { "SQC_INST_BANKA_UTCL1_MISS_FIFO",
 +        SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
 +        REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
 +        0 },
 +      { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 },
 +      { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 },
 +      { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 },
 +      { "SQC_DATA_BANKA_DIRTY_BIT_RAM",
 +        SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
 +        REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 },
 +      { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
 +        REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
 +      { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
 +      { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
 +      { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
 +      { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
 +        REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
 +      { "SQC_INST_BANKB_UTCL1_MISS_FIFO",
 +        SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
 +        REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
 +        0 },
 +      { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 },
 +      { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 },
 +      { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
 +        6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 },
 +      { "SQC_DATA_BANKB_DIRTY_BIT_RAM",
 +        SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
 +        REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 },
 +      { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
 +      { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
 +      { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
 +      { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
 +      { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
 +      { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 },
 +      { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 },
 +      { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 },
 +      { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 },
 +      { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 },
 +      { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
 +      { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
 +      { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
 +      { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 },
 +      { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 },
 +      { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 },
 +      { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 },
 +      { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 },
 +      { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
 +        REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 },
 +};
 +
 +static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
 +                                   void *inject_if)
 +{
 +      struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
 +      int ret;
 +      struct ta_ras_trigger_error_input block_info = { 0 };
 +
 +      if (adev->asic_type != CHIP_VEGA20)
 +              return -EINVAL;
 +
 +      if (!ras_gfx_subblocks[info->head.sub_block_index].name)
 +              return -EPERM;
 +
 +      if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type &
 +            info->head.type)) {
 +              DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",
 +                      ras_gfx_subblocks[info->head.sub_block_index].name,
 +                      info->head.type);
 +              return -EPERM;
 +      }
 +
 +      if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type &
 +            info->head.type)) {
 +              DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",
 +                      ras_gfx_subblocks[info->head.sub_block_index].name,
 +                      info->head.type);
 +              return -EPERM;
 +      }
 +
 +      block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
 +      block_info.sub_block_index =
 +              ras_gfx_subblocks[info->head.sub_block_index].ta_subblock;
 +      block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
 +      block_info.address = info->address;
 +      block_info.value = info->value;
 +
 +      mutex_lock(&adev->grbm_idx_mutex);
 +      ret = psp_ras_trigger_error(&adev->psp, &block_info);
 +      mutex_unlock(&adev->grbm_idx_mutex);
 +
 +      return ret;
 +}
 +
 +static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
 +                                        void *ras_error_status)
 +{
 +      struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 +      uint32_t sec_count, ded_count;
 +      uint32_t i;
 +      uint32_t reg_value;
 +      uint32_t se_id, instance_id;
 +
 +      if (adev->asic_type != CHIP_VEGA20)
 +              return -EINVAL;
 +
 +      err_data->ue_count = 0;
 +      err_data->ce_count = 0;
 +
 +      mutex_lock(&adev->grbm_idx_mutex);
 +      for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) {
 +              for (instance_id = 0; instance_id < 256; instance_id++) {
 +                      for (i = 0;
 +                           i < sizeof(gfx_ras_edc_regs) / sizeof(gfx_ras_edc_regs[0]);
 +                           i++) {
 +                              if (se_id != 0 &&
 +                                  !gfx_ras_edc_regs[i].per_se_instance)
 +                                      continue;
 +                              if (instance_id >= gfx_ras_edc_regs[i].num_instance)
 +                                      continue;
 +
 +                              gfx_v9_0_select_se_sh(adev, se_id, 0,
 +                                                    instance_id);
 +
 +                              reg_value = RREG32(
 +                                      adev->reg_offset[gfx_ras_edc_regs[i].ip]
 +                                                      [gfx_ras_edc_regs[i].inst]
 +                                                      [gfx_ras_edc_regs[i].seg] +
 +                                      gfx_ras_edc_regs[i].reg_offset);
 +                              sec_count = reg_value &
 +                                          gfx_ras_edc_regs[i].sec_count_mask;
 +                              ded_count = reg_value &
 +                                          gfx_ras_edc_regs[i].ded_count_mask;
 +                              if (sec_count) {
 +                                      DRM_INFO(
 +                                              "Instance[%d][%d]: SubBlock %s, SEC %d\n",
 +                                              se_id, instance_id,
 +                                              gfx_ras_edc_regs[i].name,
 +                                              sec_count);
 +                                      err_data->ce_count++;
 +                              }
 +
 +                              if (ded_count) {
 +                                      DRM_INFO(
 +                                              "Instance[%d][%d]: SubBlock %s, DED %d\n",
 +                                              se_id, instance_id,
 +                                              gfx_ras_edc_regs[i].name,
 +                                              ded_count);
 +                                      err_data->ue_count++;
 +                              }
 +                      }
 +              }
 +      }
 +      gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 +      mutex_unlock(&adev->grbm_idx_mutex);
 +
 +      return 0;
  }
  
  static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev,
@@@ -6109,7 -5183,7 +6118,7 @@@ static const struct amdgpu_ring_funcs g
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
 -      .vmhub = AMDGPU_GFXHUB,
 +      .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
        .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
        .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
@@@ -6160,7 -5234,7 +6169,7 @@@ static const struct amdgpu_ring_funcs g
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
 -      .vmhub = AMDGPU_GFXHUB,
 +      .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v9_0_ring_get_rptr_compute,
        .get_wptr = gfx_v9_0_ring_get_wptr_compute,
        .set_wptr = gfx_v9_0_ring_set_wptr_compute,
@@@ -6195,7 -5269,7 +6204,7 @@@ static const struct amdgpu_ring_funcs g
        .align_mask = 0xff,
        .nop = PACKET3(PACKET3_NOP, 0x3FFF),
        .support_64bit_ptrs = true,
 -      .vmhub = AMDGPU_GFXHUB,
 +      .vmhub = AMDGPU_GFXHUB_0,
        .get_rptr = gfx_v9_0_ring_get_rptr_compute,
        .get_wptr = gfx_v9_0_ring_get_wptr_compute,
        .set_wptr = gfx_v9_0_ring_set_wptr_compute,
@@@ -6275,7 -5349,6 +6284,7 @@@ static void gfx_v9_0_set_rlc_funcs(stru
        case CHIP_VEGA12:
        case CHIP_VEGA20:
        case CHIP_RAVEN:
 +      case CHIP_ARCTURUS:
                adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
                break;
        default:
@@@ -6293,7 -5366,6 +6302,7 @@@ static void gfx_v9_0_set_gds_init(struc
                adev->gds.gds_size = 0x10000;
                break;
        case CHIP_RAVEN:
 +      case CHIP_ARCTURUS:
                adev->gds.gds_size = 0x1000;
                break;
        default:
                else
                        adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
                break;
 +      case CHIP_ARCTURUS:
 +              adev->gds.gds_compute_max_wave_id = 0xfff;
 +              break;
        default:
                /* this really depends on the chip */
                adev->gds.gds_compute_max_wave_id = 0x7ff;
@@@ -6362,21 -5431,12 +6371,21 @@@ static int gfx_v9_0_get_cu_info(struct 
  {
        int i, j, k, counter, active_cu_number = 0;
        u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
 -      unsigned disable_masks[4 * 2];
 +      unsigned disable_masks[4 * 4];
  
        if (!adev || !cu_info)
                return -EINVAL;
  
 -      amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
 +      /*
 +       * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
 +       */
 +      if (adev->gfx.config.max_shader_engines *
 +              adev->gfx.config.max_sh_per_se > 16)
 +              return -EINVAL;
 +
 +      amdgpu_gfx_parse_disable_cu(disable_masks,
 +                                  adev->gfx.config.max_shader_engines,
 +                                  adev->gfx.config.max_sh_per_se);
  
        mutex_lock(&adev->grbm_idx_mutex);
        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
                        ao_bitmap = 0;
                        counter = 0;
                        gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
 -                      if (i < 4 && j < 2)
 -                              gfx_v9_0_set_user_cu_inactive_bitmap(
 -                                      adev, disable_masks[i * 2 + j]);
 +                      gfx_v9_0_set_user_cu_inactive_bitmap(
 +                              adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
                        bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
 -                      cu_info->bitmap[i][j] = bitmap;
 +
 +                      /*
 +                       * The bitmap(and ao_cu_bitmap) in cu_info structure is
 +                       * 4x4 size array, and it's usually suitable for Vega
 +                       * ASICs which has 4*2 SE/SH layout.
 +                       * But for Arcturus, SE/SH layout is changed to 8*1.
 +                       * To mostly reduce the impact, we make it compatible
 +                       * with current bitmap array as below:
 +                       *    SE4,SH0 --> bitmap[0][1]
 +                       *    SE5,SH0 --> bitmap[1][1]
 +                       *    SE6,SH0 --> bitmap[2][1]
 +                       *    SE7,SH0 --> bitmap[3][1]
 +                       */
 +                      cu_info->bitmap[i % 4][j + i / 4] = bitmap;
  
                        for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
                                if (bitmap & mask) {
                        active_cu_number += counter;
                        if (i < 2 && j < 2)
                                ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
 -                      cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
 +                      cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
                }
        }
        gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
index 454552fe2563e182fb3a182c348f67574eaf86ed,4e3fc284f6aca24db230a9f1dcea271d4bf0e5f5..66387caf966e2b01954fde2620af4ac66ab89245
@@@ -662,13 -662,13 +662,14 @@@ static int kfd_fill_gpu_cache_info(stru
        case CHIP_VEGA10:
        case CHIP_VEGA12:
        case CHIP_VEGA20:
 +      case CHIP_ARCTURUS:
                pcache_info = vega10_cache_info;
                num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
                break;
        case CHIP_RAVEN:
                pcache_info = raven_cache_info;
                num_of_cache_types = ARRAY_SIZE(raven_cache_info);
+               break;
        case CHIP_NAVI10:
                pcache_info = navi10_cache_info;
                num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
@@@ -788,7 -788,7 +789,7 @@@ int kfd_create_crat_image_acpi(void **c
   * is put in the code to ensure we don't overwrite.
   */
  #define VCRAT_SIZE_FOR_CPU    (2 * PAGE_SIZE)
 -#define VCRAT_SIZE_FOR_GPU    (3 * PAGE_SIZE)
 +#define VCRAT_SIZE_FOR_GPU    (4 * PAGE_SIZE)
  
  /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
   *
index 939b9258d5135b4b3654b2cfa0fb508e99706bd9,58c403eda04e70631fb78e848bb982b5fad6f0c4..2070e8a57ed806d1a1f2a05b90728d0ca5e2434c
@@@ -671,9 -671,6 +671,9 @@@ static void ttm_bo_release(struct kref 
        struct ttm_bo_device *bdev = bo->bdev;
        struct ttm_mem_type_manager *man = &bdev->man[bo->mem.mem_type];
  
 +      if (bo->bdev->driver->release_notify)
 +              bo->bdev->driver->release_notify(bo);
 +
        drm_vma_offset_remove(&bdev->vma_manager, &bo->vma_node);
        ttm_mem_io_lock(man, false);
        ttm_mem_io_free_vm(bo);
@@@ -1742,7 -1739,6 +1742,6 @@@ int ttm_bo_device_init(struct ttm_bo_de
        mutex_lock(&ttm_global_mutex);
        list_add_tail(&bdev->device_list, &glob->device_list);
        mutex_unlock(&ttm_global_mutex);
-       bdev->vm_ops = &ttm_bo_vm_ops;
  
        return 0;
  out_no_sys:
index 81077e5b4b7ed48149bb95004a85cced3b77ebf4,c9b8ba492f2479549938b47622bad1144fdc1221..d69121c43e58127d8d63d2174e5f0e28a3b2c32e
@@@ -390,16 -390,6 +390,16 @@@ struct ttm_bo_driver 
         * notify driver that a BO was deleted from LRU.
         */
        void (*del_from_lru_notify)(struct ttm_buffer_object *bo);
 +
 +      /**
 +       * Notify the driver that we're about to release a BO
 +       *
 +       * @bo: BO that is about to be released
 +       *
 +       * Gives the driver a chance to do any cleanup, including
 +       * adding fences that may force a delayed delete
 +       */
 +      void (*release_notify)(struct ttm_buffer_object *bo);
  };
  
  /**
@@@ -452,9 -442,6 +452,6 @@@ extern struct ttm_bo_global 
   * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver.
   * @man: An array of mem_type_managers.
   * @vma_manager: Address space manager
-  * @vm_ops: Pointer to the struct vm_operations_struct used for this
-  * device's VM operations. The driver may override this before the first
-  * mmap() call.
   * lru_lock: Spinlock that protects the buffer+device lru lists and
   * ddestroy lists.
   * @dev_mapping: A pointer to the struct address_space representing the
@@@ -473,7 -460,6 +470,6 @@@ struct ttm_bo_device 
        struct ttm_bo_global *glob;
        struct ttm_bo_driver *driver;
        struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES];
-       const struct vm_operations_struct *vm_ops;
  
        /*
         * Protected by internal locks.
        bool no_retry;
  };
  
- extern const struct vm_operations_struct ttm_bo_vm_ops;
  /**
   * struct ttm_lru_bulk_move_pos
   *