drm/amdgpu: power down/up uvd4 when smu disabled.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 7fb9137dd89b1c2bc064c3ea516c243721b5dafe..a1caa966223b3ea5b71c5c88f83e73d275d758bb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -198,7 +198,6 @@ static int uvd_v4_2_hw_init(void *handle)
        amdgpu_ring_commit(ring);
 
 done:
-
        if (!r)
                DRM_INFO("UVD initialized successfully.\n");
 
@@ -694,8 +693,24 @@ static int uvd_v4_2_set_powergating_state(void *handle,
 
        if (state == AMD_PG_STATE_GATE) {
                uvd_v4_2_stop(adev);
+               if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
+                       if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4)) {
+                               WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |
+                                                       UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK |
+                                                       UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
+                               mdelay(20);
+                       }
+               }
                return 0;
        } else {
+               if (adev->pg_flags & AMD_PG_SUPPORT_UVD && amdgpu_dpm == 0) {
+                       if (RREG32_SMC(ixCURRENT_PG_STATUS) & 0x4) {
+                               WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |
+                                               UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK |
+                                               UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK));
+                               mdelay(30);
+                       }
+               }
                return uvd_v4_2_start(adev);
        }
 }