Merge branches 'at91', 'cache', 'cup', 'ep93xx', 'ixp4xx', 'nuc', 'pending-dma-stream...
authorRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 25 Feb 2010 22:06:43 +0000 (22:06 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 25 Feb 2010 22:06:43 +0000 (22:06 +0000)
108 files changed:
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/common/dmabounce.c
arch/arm/common/vic.c
arch/arm/configs/at572d940hfek_defconfig [new file with mode: 0644]
arch/arm/include/asm/cacheflush.h
arch/arm/include/asm/dma-mapping.h
arch/arm/include/asm/page.h
arch/arm/include/asm/smp_plat.h
arch/arm/kernel/asm-offsets.c
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/Makefile
arch/arm/mach-at91/at572d940hf.c [new file with mode: 0644]
arch/arm/mach-at91/at572d940hf_devices.c [new file with mode: 0644]
arch/arm/mach-at91/board-at572d940hf_ek.c [new file with mode: 0644]
arch/arm/mach-at91/clock.c
arch/arm/mach-at91/clock.h
arch/arm/mach-at91/generic.h
arch/arm/mach-at91/include/mach/at572d940hf.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at572d940hf_matrix.h [new file with mode: 0644]
arch/arm/mach-at91/include/mach/at91_pmc.h
arch/arm/mach-at91/include/mach/board.h
arch/arm/mach-at91/include/mach/cpu.h
arch/arm/mach-at91/include/mach/hardware.h
arch/arm/mach-at91/include/mach/timex.h
arch/arm/mach-ep93xx/Kconfig
arch/arm/mach-ep93xx/Makefile
arch/arm/mach-ep93xx/clock.c
arch/arm/mach-ep93xx/core.c
arch/arm/mach-ep93xx/dma-m2p.c
arch/arm/mach-ep93xx/edb93xx.c
arch/arm/mach-ep93xx/gpio.c
arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
arch/arm/mach-ep93xx/simone.c [new file with mode: 0644]
arch/arm/mach-ep93xx/snappercl15.c [new file with mode: 0644]
arch/arm/mach-ixp4xx/common.c
arch/arm/mach-nuc93x/Kconfig [new file with mode: 0644]
arch/arm/mach-nuc93x/Makefile [new file with mode: 0644]
arch/arm/mach-nuc93x/Makefile.boot [new file with mode: 0644]
arch/arm/mach-nuc93x/clock.c [new file with mode: 0644]
arch/arm/mach-nuc93x/clock.h [new file with mode: 0644]
arch/arm/mach-nuc93x/cpu.c [new file with mode: 0644]
arch/arm/mach-nuc93x/cpu.h [new file with mode: 0644]
arch/arm/mach-nuc93x/dev.c [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/clkdev.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/entry-macro.S [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/hardware.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/io.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/irqs.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/map.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/memory.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/regs-clock.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/regs-ebi.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/regs-irq.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/regs-serial.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/regs-timer.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/system.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/timex.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/uncompress.h [new file with mode: 0644]
arch/arm/mach-nuc93x/include/mach/vmalloc.h [new file with mode: 0644]
arch/arm/mach-nuc93x/irq.c [new file with mode: 0644]
arch/arm/mach-nuc93x/mach-nuc932evb.c [new file with mode: 0644]
arch/arm/mach-nuc93x/nuc932.c [new file with mode: 0644]
arch/arm/mach-nuc93x/nuc932.h [new file with mode: 0644]
arch/arm/mach-nuc93x/time.c [new file with mode: 0644]
arch/arm/mach-u300/clock.c
arch/arm/mach-u300/core.c
arch/arm/mach-u300/gpio.c
arch/arm/mach-u300/include/mach/dma_channels.h [new file with mode: 0644]
arch/arm/mach-ux500/board-mop500.c
arch/arm/mach-ux500/cpu-u8500.c
arch/arm/mach-ux500/include/mach/debug-macro.S
arch/arm/mach-w90x900/cpu.c
arch/arm/mm/cache-fa.S
arch/arm/mm/cache-v3.S
arch/arm/mm/cache-v4.S
arch/arm/mm/cache-v4wb.S
arch/arm/mm/cache-v4wt.S
arch/arm/mm/cache-v6.S
arch/arm/mm/cache-v7.S
arch/arm/mm/copypage-feroceon.c
arch/arm/mm/copypage-v3.c
arch/arm/mm/copypage-v4mc.c
arch/arm/mm/copypage-v4wb.c
arch/arm/mm/copypage-v4wt.c
arch/arm/mm/copypage-v6.c
arch/arm/mm/copypage-xsc3.c
arch/arm/mm/copypage-xscale.c
arch/arm/mm/dma-mapping.c
arch/arm/mm/flush.c
arch/arm/mm/proc-arm1020.S
arch/arm/mm/proc-arm1020e.S
arch/arm/mm/proc-arm1022.S
arch/arm/mm/proc-arm1026.S
arch/arm/mm/proc-arm920.S
arch/arm/mm/proc-arm922.S
arch/arm/mm/proc-arm925.S
arch/arm/mm/proc-arm926.S
arch/arm/mm/proc-arm940.S
arch/arm/mm/proc-arm946.S
arch/arm/mm/proc-feroceon.S
arch/arm/mm/proc-mohawk.S
arch/arm/mm/proc-xsc3.S
arch/arm/mm/proc-xscale.S
arch/arm/plat-nomadik/include/plat/i2c.h [new file with mode: 0644]
drivers/mmc/host/mmci.c
drivers/rtc/rtc-pl031.c
drivers/spi/amba-pl022.c

index c2238cd474c784e52872627586632f65608281a1..b0c3c0d89e0590b5a384460b3a5d021fc6ce616f 100644 (file)
@@ -550,6 +550,15 @@ config ARCH_W90X900
          <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
                ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 
+config ARCH_NUC93X
+       bool "Nuvoton NUC93X CPU"
+       select CPU_ARM926T
+       select HAVE_CLK
+       select COMMON_CLKDEV
+       help
+         Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
+         low-power and high performance MPEG-4/JPEG multimedia controller chip.
+
 config ARCH_PNX4008
        bool "Philips Nexperia PNX4008 Mobile"
        select CPU_ARM926T
@@ -760,6 +769,8 @@ source "arch/arm/plat-pxa/Kconfig"
 
 source "arch/arm/mach-mmp/Kconfig"
 
+source "arch/arm/mach-nuc93x/Kconfig"
+
 source "arch/arm/mach-sa1100/Kconfig"
 
 source "arch/arm/plat-omap/Kconfig"
index e9da08483b3cdb74bd687cf3601ec4dccf395c25..3eaef160d4681431be434ab4f792b7361100d073 100644 (file)
@@ -170,6 +170,7 @@ machine-$(CONFIG_ARCH_U300)         := u300
 machine-$(CONFIG_ARCH_U8500)           := ux500
 machine-$(CONFIG_ARCH_VERSATILE)       := versatile
 machine-$(CONFIG_ARCH_W90X900)         := w90x900
+machine-$(CONFIG_ARCH_NUC93X)          := nuc93x
 machine-$(CONFIG_FOOTBRIDGE)           := footbridge
 machine-$(CONFIG_ARCH_MXC91231)                := mxc91231
 
index cc32c1e54a59825dc93fcbba098fcdbd51d9c8f0..cc0a932bbea90780f659becc4ee7d93087ab61cf 100644 (file)
@@ -277,7 +277,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
                 * We don't need to sync the DMA buffer since
                 * it was allocated via the coherent allocators.
                 */
-               dma_cache_maint(ptr, size, dir);
+               __dma_single_cpu_to_dev(ptr, size, dir);
        }
 
        return dma_addr;
@@ -315,6 +315,8 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
                        __cpuc_flush_dcache_area(ptr, size);
                }
                free_safe_buffer(dev->archdata.dmabounce, buf);
+       } else {
+               __dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir);
        }
 }
 
index f232941de8abc4c56e9074d3f83ebbe672907be3..1cf999ade4bc181855379a10d724eac917b83da7 100644 (file)
@@ -18,6 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
-static void vic_ack_irq(unsigned int irq)
-{
-       void __iomem *base = get_irq_chip_data(irq);
-       irq &= 31;
-       writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-       /* moreover, clear the soft-triggered, in case it was the reason */
-       writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
-}
-
-static void vic_mask_irq(unsigned int irq)
-{
-       void __iomem *base = get_irq_chip_data(irq);
-       irq &= 31;
-       writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-}
-
-static void vic_unmask_irq(unsigned int irq)
-{
-       void __iomem *base = get_irq_chip_data(irq);
-       irq &= 31;
-       writel(1 << irq, base + VIC_INT_ENABLE);
-}
-
-/**
- * vic_init2 - common initialisation code
- * @base: Base of the VIC.
- *
- * Common initialisation code for registeration
- * and resume.
-*/
-static void vic_init2(void __iomem *base)
-{
-       int i;
-
-       for (i = 0; i < 16; i++) {
-               void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-               writel(VIC_VECT_CNTL_ENABLE | i, reg);
-       }
-
-       writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-}
-
 #if defined(CONFIG_PM)
 /**
  * struct vic_device - VIC PM device
@@ -99,13 +58,34 @@ struct vic_device {
 /* we cannot allocate memory when VICs are initially registered */
 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 
+static int vic_id;
+
 static inline struct vic_device *to_vic(struct sys_device *sys)
 {
        return container_of(sys, struct vic_device, sysdev);
 }
+#endif /* CONFIG_PM */
 
-static int vic_id;
+/**
+ * vic_init2 - common initialisation code
+ * @base: Base of the VIC.
+ *
+ * Common initialisation code for registeration
+ * and resume.
+*/
+static void vic_init2(void __iomem *base)
+{
+       int i;
+
+       for (i = 0; i < 16; i++) {
+               void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+               writel(VIC_VECT_CNTL_ENABLE | i, reg);
+       }
+
+       writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+}
 
+#if defined(CONFIG_PM)
 static int vic_class_resume(struct sys_device *dev)
 {
        struct vic_device *vic = to_vic(dev);
@@ -158,31 +138,6 @@ struct sysdev_class vic_class = {
        .resume         = vic_class_resume,
 };
 
-/**
- * vic_pm_register - Register a VIC for later power management control
- * @base: The base address of the VIC.
- * @irq: The base IRQ for the VIC.
- * @resume_sources: bitmask of interrupts allowed for resume sources.
- *
- * Register the VIC with the system device tree so that it can be notified
- * of suspend and resume requests and ensure that the correct actions are
- * taken to re-instate the settings on resume.
- */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
-{
-       struct vic_device *v;
-
-       if (vic_id >= ARRAY_SIZE(vic_devices))
-               printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-       else {
-               v = &vic_devices[vic_id];
-               v->base = base;
-               v->resume_sources = resume_sources;
-               v->irq = irq;
-               vic_id++;
-       }
-}
-
 /**
  * vic_pm_init - initicall to register VIC pm
  *
@@ -219,9 +174,60 @@ static int __init vic_pm_init(void)
 
        return 0;
 }
-
 late_initcall(vic_pm_init);
 
+/**
+ * vic_pm_register - Register a VIC for later power management control
+ * @base: The base address of the VIC.
+ * @irq: The base IRQ for the VIC.
+ * @resume_sources: bitmask of interrupts allowed for resume sources.
+ *
+ * Register the VIC with the system device tree so that it can be notified
+ * of suspend and resume requests and ensure that the correct actions are
+ * taken to re-instate the settings on resume.
+ */
+static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+{
+       struct vic_device *v;
+
+       if (vic_id >= ARRAY_SIZE(vic_devices))
+               printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
+       else {
+               v = &vic_devices[vic_id];
+               v->base = base;
+               v->resume_sources = resume_sources;
+               v->irq = irq;
+               vic_id++;
+       }
+}
+#else
+static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
+#endif /* CONFIG_PM */
+
+static void vic_ack_irq(unsigned int irq)
+{
+       void __iomem *base = get_irq_chip_data(irq);
+       irq &= 31;
+       writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+       /* moreover, clear the soft-triggered, in case it was the reason */
+       writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
+}
+
+static void vic_mask_irq(unsigned int irq)
+{
+       void __iomem *base = get_irq_chip_data(irq);
+       irq &= 31;
+       writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+}
+
+static void vic_unmask_irq(unsigned int irq)
+{
+       void __iomem *base = get_irq_chip_data(irq);
+       irq &= 31;
+       writel(1 << irq, base + VIC_INT_ENABLE);
+}
+
+#if defined(CONFIG_PM)
 static struct vic_device *vic_from_irq(unsigned int irq)
 {
         struct vic_device *v = vic_devices;
@@ -255,10 +261,7 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
 
        return 0;
 }
-
 #else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
-
 #define vic_set_wake NULL
 #endif /* CONFIG_PM */
 
@@ -270,9 +273,62 @@ static struct irq_chip vic_chip = {
        .set_wake = vic_set_wake,
 };
 
-/* The PL190 cell from ARM has been modified by ST, so handle both here */
-static void vik_init_st(void __iomem *base, unsigned int irq_start,
-                        u32 vic_sources);
+/*
+ * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
+ * The original cell has 32 interrupts, while the modified one has 64,
+ * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
+ * the probe function is called twice, with base set to offset 000
+ *  and 020 within the page. We call this "second block".
+ */
+static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
+                               u32 vic_sources)
+{
+       unsigned int i;
+       int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
+
+       /* Disable all interrupts initially. */
+
+       writel(0, base + VIC_INT_SELECT);
+       writel(0, base + VIC_INT_ENABLE);
+       writel(~0, base + VIC_INT_ENABLE_CLEAR);
+       writel(0, base + VIC_IRQ_STATUS);
+       writel(0, base + VIC_ITCR);
+       writel(~0, base + VIC_INT_SOFT_CLEAR);
+
+       /*
+        * Make sure we clear all existing interrupts. The vector registers
+        * in this cell are after the second block of general registers,
+        * so we can address them using standard offsets, but only from
+        * the second base address, which is 0x20 in the page
+        */
+       if (vic_2nd_block) {
+               writel(0, base + VIC_PL190_VECT_ADDR);
+               for (i = 0; i < 19; i++) {
+                       unsigned int value;
+
+                       value = readl(base + VIC_PL190_VECT_ADDR);
+                       writel(value, base + VIC_PL190_VECT_ADDR);
+               }
+               /* ST has 16 vectors as well, but we don't enable them by now */
+               for (i = 0; i < 16; i++) {
+                       void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                       writel(0, reg);
+               }
+
+               writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+       }
+
+       for (i = 0; i < 32; i++) {
+               if (vic_sources & (1 << i)) {
+                       unsigned int irq = irq_start + i;
+
+                       set_irq_chip(irq, &vic_chip);
+                       set_irq_chip_data(irq, base);
+                       set_irq_handler(irq, handle_level_irq);
+                       set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+               }
+       }
+}
 
 /**
  * vic_init - initialise a vectored interrupt controller
@@ -299,7 +355,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
        switch(vendor) {
        case AMBA_VENDOR_ST:
-               vik_init_st(base, irq_start, vic_sources);
+               vic_init_st(base, irq_start, vic_sources);
                return;
        default:
                printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
@@ -343,60 +399,3 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
        vic_pm_register(base, irq_start, resume_sources);
 }
-
-/*
- * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
- * The original cell has 32 interrupts, while the modified one has 64,
- * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
- * the probe function is called twice, with base set to offset 000
- *  and 020 within the page. We call this "second block".
- */
-static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
-                               u32 vic_sources)
-{
-       unsigned int i;
-       int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
-
-       /* Disable all interrupts initially. */
-
-       writel(0, base + VIC_INT_SELECT);
-       writel(0, base + VIC_INT_ENABLE);
-       writel(~0, base + VIC_INT_ENABLE_CLEAR);
-       writel(0, base + VIC_IRQ_STATUS);
-       writel(0, base + VIC_ITCR);
-       writel(~0, base + VIC_INT_SOFT_CLEAR);
-
-       /*
-        * Make sure we clear all existing interrupts. The vector registers
-        * in this cell are after the second block of general registers,
-        * so we can address them using standard offsets, but only from
-        * the second base address, which is 0x20 in the page
-        */
-       if (vic_2nd_block) {
-               writel(0, base + VIC_PL190_VECT_ADDR);
-               for (i = 0; i < 19; i++) {
-                       unsigned int value;
-
-                       value = readl(base + VIC_PL190_VECT_ADDR);
-                       writel(value, base + VIC_PL190_VECT_ADDR);
-               }
-               /* ST has 16 vectors as well, but we don't enable them by now */
-               for (i = 0; i < 16; i++) {
-                       void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                       writel(0, reg);
-               }
-
-               writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-       }
-
-       for (i = 0; i < 32; i++) {
-               if (vic_sources & (1 << i)) {
-                       unsigned int irq = irq_start + i;
-
-                       set_irq_chip(irq, &vic_chip);
-                       set_irq_chip_data(irq, base);
-                       set_irq_handler(irq, handle_level_irq);
-                       set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-               }
-       }
-}
diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig
new file mode 100644 (file)
index 0000000..76d724b
--- /dev/null
@@ -0,0 +1,1640 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc7
+# Fri Dec  5 10:58:47 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-AT572D940HF"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+# CONFIG_TASK_DELAY_ACCT is not set
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_ARCH_AT572D940HF=y
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT572D940HF Board Type
+#
+CONFIG_MACH_AT572D940HFEB=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
+CONFIG_NUM_SERIAL=3
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+CONFIG_RESOURCES_64BIT=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=48M console=ttyS0 initrd=0x21100000,3145728 root=/dev/ram0 rw ip=172.16.1.181"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_TCPPROBE=m
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_DEBUG_DEVICES=y
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=m
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_FTL=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=m
+CONFIG_RFD_FTL=m
+CONFIG_SSFDC=m
+CONFIG_MTD_OOPS=m
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_RAM=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_ABSENT=m
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x4000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+CONFIG_MTD_PLATRAM=m
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=m
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+CONFIG_MTD_M25P80=m
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_BLOCK2MTD=m
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=m
+CONFIG_MTD_NAND_DISKONCHIP=m
+# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
+# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
+# CONFIG_MTD_NAND_ATMEL is not set
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_ALAUDA=m
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
+CONFIG_ATMEL_SSC=m
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+CONFIG_WLAN_PRE80211=y
+CONFIG_STRIP=m
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+# CONFIG_MOUSE_BCM5974 is not set
+CONFIG_MOUSE_VSXXXAA=m
+CONFIG_MOUSE_GPIO=m
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_N_HDLC=m
+# CONFIG_RISCOM8 is not set
+CONFIG_SPECIALIX=m
+CONFIG_RIO=m
+# CONFIG_RIO_OLDPCI is not set
+CONFIG_STALDRV=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_IPMI_HANDLER=m
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_HW_RANDOM=y
+CONFIG_NVRAM=m
+CONFIG_R3964=m
+CONFIG_RAW_DRIVER=m
+CONFIG_MAX_RAW_DEVS=256
+CONFIG_TCG_TPM=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_ATMEL=m
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_DS1682=m
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=m
+CONFIG_SENSORS_PCF8574=m
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+CONFIG_SENSORS_PCF8591=m
+CONFIG_SENSORS_MAX6875=m
+CONFIG_SENSORS_TSL2550=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_BITBANG=m
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_AT25=m
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+# CONFIG_SND_PCM_OSS_PLUGINS is not set
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_VIRMIDI=m
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+# CONFIG_SND_AT73C213 is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BRIGHT=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DELL=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_DPCM=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+CONFIG_USB_STORAGE_KARMA=y
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+CONFIG_USB_SERIAL_SPCP8X5=m
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=m
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=m
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+CONFIG_RTC_DRV_DS1305=y
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+CONFIG_REISERFS_CHECK=y
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+# CONFIG_UBIFS_FS is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LDM_DEBUG=y
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
index 730aefcfbee3eb8e0c46ea0a6dc0b9ba0fd1e27f..be8b4d79cf414690504a6e4d8669a8ed2b0a8e67 100644 (file)
  *     DMA Cache Coherency
  *     ===================
  *
- *     dma_inv_range(start, end)
- *
- *             Invalidate (discard) the specified virtual address range.
- *             May not write back any entries.  If 'start' or 'end'
- *             are not cache line aligned, those lines must be written
- *             back.
- *             - start  - virtual start address
- *             - end    - virtual end address
- *
- *     dma_clean_range(start, end)
- *
- *             Clean (write back) the specified virtual address range.
- *             - start  - virtual start address
- *             - end    - virtual end address
- *
  *     dma_flush_range(start, end)
  *
  *             Clean and invalidate the specified virtual address range.
@@ -213,8 +198,9 @@ struct cpu_cache_fns {
        void (*coherent_user_range)(unsigned long, unsigned long);
        void (*flush_kern_dcache_area)(void *, size_t);
 
-       void (*dma_inv_range)(const void *, const void *);
-       void (*dma_clean_range)(const void *, const void *);
+       void (*dma_map_area)(const void *, size_t, int);
+       void (*dma_unmap_area)(const void *, size_t, int);
+
        void (*dma_flush_range)(const void *, const void *);
 };
 
@@ -244,8 +230,8 @@ extern struct cpu_cache_fns cpu_cache;
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
-#define dmac_inv_range                 cpu_cache.dma_inv_range
-#define dmac_clean_range               cpu_cache.dma_clean_range
+#define dmac_map_area                  cpu_cache.dma_map_area
+#define dmac_unmap_area                cpu_cache.dma_unmap_area
 #define dmac_flush_range               cpu_cache.dma_flush_range
 
 #else
@@ -270,12 +256,12 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
-#define dmac_inv_range                 __glue(_CACHE,_dma_inv_range)
-#define dmac_clean_range               __glue(_CACHE,_dma_clean_range)
+#define dmac_map_area                  __glue(_CACHE,_dma_map_area)
+#define dmac_unmap_area                __glue(_CACHE,_dma_unmap_area)
 #define dmac_flush_range               __glue(_CACHE,_dma_flush_range)
 
-extern void dmac_inv_range(const void *, const void *);
-extern void dmac_clean_range(const void *, const void *);
+extern void dmac_map_area(const void *, size_t, int);
+extern void dmac_unmap_area(const void *, size_t, int);
 extern void dmac_flush_range(const void *, const void *);
 
 #endif
@@ -316,12 +302,8 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
  * processes address space.  Really, we want to allow our "user
  * space" model to handle this.
  */
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-       do {                                                    \
-               memcpy(dst, src, len);                          \
-               flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
-       } while (0)
-
+extern void copy_to_user_page(struct vm_area_struct *, struct page *,
+       unsigned long, void *, const void *, unsigned long);
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
        do {                                                    \
                memcpy(dst, src, len);                          \
@@ -355,17 +337,6 @@ vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
        }
 }
 
-static inline void
-vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                        unsigned long uaddr, void *kaddr,
-                        unsigned long len, int write)
-{
-       if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
-               unsigned long addr = (unsigned long)kaddr;
-               __cpuc_coherent_kern_range(addr, addr + len);
-       }
-}
-
 #ifndef CONFIG_CPU_CACHE_VIPT
 #define flush_cache_mm(mm) \
                vivt_flush_cache_mm(mm)
@@ -373,15 +344,10 @@ vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                vivt_flush_cache_range(vma,start,end)
 #define flush_cache_page(vma,addr,pfn) \
                vivt_flush_cache_page(vma,addr,pfn)
-#define flush_ptrace_access(vma,page,ua,ka,len,write) \
-               vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
 #else
 extern void flush_cache_mm(struct mm_struct *mm);
 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
-extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                               unsigned long uaddr, void *kaddr,
-                               unsigned long len, int write);
 #endif
 
 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
index a96300bf83fd65f3c6058da9194eb71ef5e5a35f..256ee1c9f51aae017d2cef9139965aa3d4512cc9 100644 (file)
@@ -57,18 +57,58 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
 #endif
 
 /*
- * DMA-consistent mapping functions.  These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices.  This is the "generic" version.  The PCI specific version
- * is in pci.h
+ * The DMA API is built upon the notion of "buffer ownership".  A buffer
+ * is either exclusively owned by the CPU (and therefore may be accessed
+ * by it) or exclusively owned by the DMA device.  These helper functions
+ * represent the transitions between these two ownership states.
  *
- * Note: Drivers should NOT use this function directly, as it will break
- * platforms with CONFIG_DMABOUNCE.
- * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
+ * Note, however, that on later ARMs, this notion does not work due to
+ * speculative prefetches.  We model our approach on the assumption that
+ * the CPU does do speculative prefetches, which means we clean caches
+ * before transfers and delay cache invalidation until transfer completion.
+ *
+ * Private support functions: these are not part of the API and are
+ * liable to change.  Drivers must not use these.
  */
-extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
-extern void dma_cache_maint_page(struct page *page, unsigned long offset,
-                                size_t size, int rw);
+static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size,
+       enum dma_data_direction dir)
+{
+       extern void ___dma_single_cpu_to_dev(const void *, size_t,
+               enum dma_data_direction);
+
+       if (!arch_is_coherent())
+               ___dma_single_cpu_to_dev(kaddr, size, dir);
+}
+
+static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size,
+       enum dma_data_direction dir)
+{
+       extern void ___dma_single_dev_to_cpu(const void *, size_t,
+               enum dma_data_direction);
+
+       if (!arch_is_coherent())
+               ___dma_single_dev_to_cpu(kaddr, size, dir);
+}
+
+static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
+       size_t size, enum dma_data_direction dir)
+{
+       extern void ___dma_page_cpu_to_dev(struct page *, unsigned long,
+               size_t, enum dma_data_direction);
+
+       if (!arch_is_coherent())
+               ___dma_page_cpu_to_dev(page, off, size, dir);
+}
+
+static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
+       size_t size, enum dma_data_direction dir)
+{
+       extern void ___dma_page_dev_to_cpu(struct page *, unsigned long,
+               size_t, enum dma_data_direction);
+
+       if (!arch_is_coherent())
+               ___dma_page_dev_to_cpu(page, off, size, dir);
+}
 
 /*
  * Return whether the given device DMA address mask can be supported
@@ -304,8 +344,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
 {
        BUG_ON(!valid_dma_direction(dir));
 
-       if (!arch_is_coherent())
-               dma_cache_maint(cpu_addr, size, dir);
+       __dma_single_cpu_to_dev(cpu_addr, size, dir);
 
        return virt_to_dma(dev, cpu_addr);
 }
@@ -329,8 +368,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 {
        BUG_ON(!valid_dma_direction(dir));
 
-       if (!arch_is_coherent())
-               dma_cache_maint_page(page, offset, size, dir);
+       __dma_page_cpu_to_dev(page, offset, size, dir);
 
        return page_to_dma(dev, page) + offset;
 }
@@ -352,7 +390,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
                size_t size, enum dma_data_direction dir)
 {
-       /* nothing to do */
+       __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
 }
 
 /**
@@ -372,7 +410,8 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
 static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
                size_t size, enum dma_data_direction dir)
 {
-       /* nothing to do */
+       __dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK,
+               size, dir);
 }
 #endif /* CONFIG_DMABOUNCE */
 
@@ -400,7 +439,10 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
 {
        BUG_ON(!valid_dma_direction(dir));
 
-       dmabounce_sync_for_cpu(dev, handle, offset, size, dir);
+       if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir))
+               return;
+
+       __dma_single_dev_to_cpu(dma_to_virt(dev, handle) + offset, size, dir);
 }
 
 static inline void dma_sync_single_range_for_device(struct device *dev,
@@ -412,8 +454,7 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
        if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
                return;
 
-       if (!arch_is_coherent())
-               dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
+       __dma_single_cpu_to_dev(dma_to_virt(dev, handle) + offset, size, dir);
 }
 
 static inline void dma_sync_single_for_cpu(struct device *dev,
index 3a32af4cce30ac2ec0da9eb3089cbcf0082b193f..a485ac3c8696d2cdbc2e9a857ba4298de63e1428 100644 (file)
 #endif
 
 struct page;
+struct vm_area_struct;
 
 struct cpu_user_fns {
        void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr);
        void (*cpu_copy_user_highpage)(struct page *to, struct page *from,
-                       unsigned long vaddr);
+                       unsigned long vaddr, struct vm_area_struct *vma);
 };
 
 #ifdef MULTI_USER
@@ -137,7 +138,7 @@ extern struct cpu_user_fns cpu_user;
 
 extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr);
 extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
-                       unsigned long vaddr);
+                       unsigned long vaddr, struct vm_area_struct *vma);
 #endif
 
 #define clear_user_highpage(page,vaddr)                \
@@ -145,7 +146,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 
 #define __HAVE_ARCH_COPY_USER_HIGHPAGE
 #define copy_user_highpage(to,from,vaddr,vma)  \
-       __cpu_copy_user_highpage(to, from, vaddr)
+       __cpu_copy_user_highpage(to, from, vaddr, vma)
 
 #define clear_page(page)       memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
index 59303e2008457763334a6e2306de382280030ab7..e6215305544aa9c63db768c53a7c194fe38c6747 100644 (file)
@@ -13,4 +13,9 @@ static inline int tlb_ops_need_broadcast(void)
        return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+static inline int cache_ops_need_broadcast(void)
+{
+       return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
+}
+
 #endif
index 4a881258bb171f7c14828d12fdc4ef9bf91b0186..883511522fca9e83be970c2611fd2ce5a1a75a41 100644 (file)
@@ -12,6 +12,7 @@
  */
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/dma-mapping.h>
 #include <asm/mach/arch.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
@@ -112,5 +113,9 @@ int main(void)
 #ifdef MULTI_PABORT
   DEFINE(PROCESSOR_PABT_FUNC,  offsetof(struct processor, _prefetch_abort));
 #endif
+  BLANK();
+  DEFINE(DMA_BIDIRECTIONAL,    DMA_BIDIRECTIONAL);
+  DEFINE(DMA_TO_DEVICE,                DMA_TO_DEVICE);
+  DEFINE(DMA_FROM_DEVICE,      DMA_FROM_DEVICE);
   return 0; 
 }
index 0b2ee953f1641d75d4d0fc9ddcc655758a9b02df..2db43a5ddd9b7b752b054ded6ff3c32f2c6c3de7 100644 (file)
@@ -89,6 +89,12 @@ config ARCH_AT91CAP9
        select GENERIC_CLOCKEVENTS
        select HAVE_FB_ATMEL
 
+config ARCH_AT572D940HF
+       bool "AT572D940HF"
+       select CPU_ARM926T
+       select GENERIC_TIME
+       select GENERIC_CLOCKEVENTS
+
 config ARCH_AT91X40
        bool "AT91x40"
 
@@ -390,6 +396,23 @@ endif
 
 # ----------------------------------------------------------
 
+if ARCH_AT572D940HF
+
+comment "AT572D940HF Board Type"
+
+config MACH_AT572D940HFEB
+       bool "AT572D940HF-EK"
+       depends on ARCH_AT572D940HF
+       select HAVE_AT91_DATAFLASH_CARD
+       select HAVE_NAND_ATMEL_BUSWIDTH_16
+       help
+         Select this if you are using Atmel's AT572D940HF-EK evaluation kit.
+         <http://www.atmel.com/products/diopsis/default.asp>
+
+endif
+
+# ----------------------------------------------------------
+
 if ARCH_AT91X40
 
 comment "AT91X40 Board Type"
index 709fbad4a3ee2b28b14ec7fd0281dc4382702c76..027dd570dcc30231059d3530f5a33293f168dce7 100644 (file)
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
 obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o
  obj-$(CONFIG_ARCH_AT91SAM9G45)        += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)    += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)     += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
@@ -69,6 +70,9 @@ obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
 
+# AT572D940HF board-specific support
+obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o
+
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)    += board-eb01.o
 
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c
new file mode 100644 (file)
index 0000000..a6b9c68
--- /dev/null
@@ -0,0 +1,377 @@
+/*
+ * arch/arm/mach-at91/at572d940hf.c
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at572d940hf.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+static struct map_desc at572d940hf_io_desc[] __initdata = {
+       {
+               .virtual        = AT91_VA_BASE_SYS,
+               .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
+               .pfn            = __phys_to_pfn(AT572D940HF_SRAM_BASE),
+               .length         = AT572D940HF_SRAM_SIZE,
+               .type           = MT_DEVICE,
+       },
+};
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+       .name           = "pioA_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_PIOA,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+       .name           = "pioB_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_PIOB,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+       .name           = "pioC_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_PIOC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk macb_clk = {
+       .name           = "macb_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_EMAC,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+       .name           = "usart0_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_US0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+       .name           = "usart1_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_US1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+       .name           = "usart2_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_US2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+       .name           = "mci_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_MCI,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udc_clk = {
+       .name           = "udc_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_UDP,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+       .name           = "twi0_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_TWI0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+       .name           = "spi0_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_SPI0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+       .name           = "spi1_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_SPI1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+       .name           = "ssc0_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_SSC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+       .name           = "ssc1_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_SSC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc2_clk = {
+       .name           = "ssc2_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_SSC2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc0_clk = {
+       .name           = "tc0_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_TC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+       .name           = "tc1_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_TC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+       .name           = "tc2_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_TC2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+       .name           = "ohci_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_UHP,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc3_clk = {
+       .name           = "ssc3_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_SSC3,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+       .name           = "twi1_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_TWI1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can0_clk = {
+       .name           = "can0_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_CAN0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can1_clk = {
+       .name           = "can1_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_CAN1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mAgicV_clk = {
+       .name           = "mAgicV_clk",
+       .pmc_mask       = 1 << AT572D940HF_ID_MSIRQ0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+
+
+static struct clk *periph_clocks[] __initdata = {
+       &pioA_clk,
+       &pioB_clk,
+       &pioC_clk,
+       &macb_clk,
+       &usart0_clk,
+       &usart1_clk,
+       &usart2_clk,
+       &mmc_clk,
+       &udc_clk,
+       &twi0_clk,
+       &spi0_clk,
+       &spi1_clk,
+       &ssc0_clk,
+       &ssc1_clk,
+       &ssc2_clk,
+       &tc0_clk,
+       &tc1_clk,
+       &tc2_clk,
+       &ohci_clk,
+       &ssc3_clk,
+       &twi1_clk,
+       &can0_clk,
+       &can1_clk,
+       &mAgicV_clk,
+       /* irq0 .. irq2 */
+};
+
+/*
+ * The five programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+       .name           = "pck0",
+       .pmc_mask       = AT91_PMC_PCK0,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 0,
+};
+static struct clk pck1 = {
+       .name           = "pck1",
+       .pmc_mask       = AT91_PMC_PCK1,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 1,
+};
+static struct clk pck2 = {
+       .name           = "pck2",
+       .pmc_mask       = AT91_PMC_PCK2,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 2,
+};
+static struct clk pck3 = {
+       .name           = "pck3",
+       .pmc_mask       = AT91_PMC_PCK3,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 3,
+};
+
+static struct clk mAgicV_mem_clk = {
+       .name           = "mAgicV_mem_clk",
+       .pmc_mask       = AT91_PMC_PCK4,
+       .type           = CLK_TYPE_PROGRAMMABLE,
+       .id             = 4,
+};
+
+/* HClocks */
+static struct clk hck0 = {
+       .name           = "hck0",
+       .pmc_mask       = AT91_PMC_HCK0,
+       .type           = CLK_TYPE_SYSTEM,
+       .id             = 0,
+};
+static struct clk hck1 = {
+       .name           = "hck1",
+       .pmc_mask       = AT91_PMC_HCK1,
+       .type           = CLK_TYPE_SYSTEM,
+       .id             = 1,
+};
+
+static void __init at572d940hf_register_clocks(void)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+               clk_register(periph_clocks[i]);
+
+       clk_register(&pck0);
+       clk_register(&pck1);
+       clk_register(&pck2);
+       clk_register(&pck3);
+       clk_register(&mAgicV_mem_clk);
+
+       clk_register(&hck0);
+       clk_register(&hck1);
+}
+
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at572d940hf_gpio[] = {
+       {
+               .id             = AT572D940HF_ID_PIOA,
+               .offset         = AT91_PIOA,
+               .clock          = &pioA_clk,
+       }, {
+               .id             = AT572D940HF_ID_PIOB,
+               .offset         = AT91_PIOB,
+               .clock          = &pioB_clk,
+       }, {
+               .id             = AT572D940HF_ID_PIOC,
+               .offset         = AT91_PIOC,
+               .clock          = &pioC_clk,
+       }
+};
+
+static void at572d940hf_reset(void)
+{
+       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+}
+
+
+/* --------------------------------------------------------------------
+ *  AT572D940HF processor initialization
+ * -------------------------------------------------------------------- */
+
+void __init at572d940hf_initialize(unsigned long main_clock)
+{
+       /* Map peripherals */
+       iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
+
+       at91_arch_reset = at572d940hf_reset;
+       at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
+                       | (1 << AT572D940HF_ID_IRQ2);
+
+       /* Init clock subsystem */
+       at91_clock_init(main_clock);
+
+       /* Register the processor-specific clocks */
+       at572d940hf_register_clocks();
+
+       /* Register GPIO subsystem */
+       at91_gpio_init(at572d940hf_gpio, 3);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
+       7,      /* Advanced Interrupt Controller */
+       7,      /* System Peripherals */
+       0,      /* Parallel IO Controller A */
+       0,      /* Parallel IO Controller B */
+       0,      /* Parallel IO Controller C */
+       3,      /* Ethernet */
+       6,      /* USART 0 */
+       6,      /* USART 1 */
+       6,      /* USART 2 */
+       0,      /* Multimedia Card Interface */
+       4,      /* USB Device Port */
+       0,      /* Two-Wire Interface 0 */
+       6,      /* Serial Peripheral Interface 0 */
+       6,      /* Serial Peripheral Interface 1 */
+       5,      /* Serial Synchronous Controller 0 */
+       5,      /* Serial Synchronous Controller 1 */
+       5,      /* Serial Synchronous Controller 2 */
+       0,      /* Timer Counter 0 */
+       0,      /* Timer Counter 1 */
+       0,      /* Timer Counter 2 */
+       3,      /* USB Host port */
+       3,      /* Serial Synchronous Controller 3 */
+       0,      /* Two-Wire Interface 1 */
+       0,      /* CAN Controller 0 */
+       0,      /* CAN Controller 1 */
+       0,      /* mAgicV HALT line */
+       0,      /* mAgicV SIRQ0 line */
+       0,      /* mAgicV exception line */
+       0,      /* mAgicV end of DMA line */
+       0,      /* Advanced Interrupt Controller */
+       0,      /* Advanced Interrupt Controller */
+       0,      /* Advanced Interrupt Controller */
+};
+
+void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+       if (!priority)
+               priority = at572d940hf_default_irq_priority;
+
+       /* Initialize the AIC interrupt controller */
+       at91_aic_init(priority);
+
+       /* Enable GPIO interrupts */
+       at91_gpio_irq_setup();
+}
+
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
new file mode 100644 (file)
index 0000000..0fc20a2
--- /dev/null
@@ -0,0 +1,970 @@
+/*
+ * arch/arm/mach-at91/at572d940hf_devices.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ * Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at572d940hf.h>
+#include <mach/at572d940hf_matrix.h>
+#include <mach/at91sam9_smc.h>
+
+#include "generic.h"
+#include "sam9_smc.h"
+
+
+/* --------------------------------------------------------------------
+ *  USB Host
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+static struct at91_usbh_data usbh_data;
+
+static struct resource usbh_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_UHP_BASE,
+               .end    = AT572D940HF_UHP_BASE + SZ_1M - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_UHP,
+               .end    = AT572D940HF_ID_UHP,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_usbh_device = {
+       .name           = "at91_ohci",
+       .id             = -1,
+       .dev            = {
+                               .dma_mask               = &ohci_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+                               .platform_data          = &usbh_data,
+       },
+       .resource       = usbh_resources,
+       .num_resources  = ARRAY_SIZE(usbh_resources),
+};
+
+void __init at91_add_device_usbh(struct at91_usbh_data *data)
+{
+       if (!data)
+               return;
+
+       usbh_data = *data;
+       platform_device_register(&at572d940hf_usbh_device);
+
+}
+#else
+void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  USB Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_USB_GADGET_AT91
+static struct at91_udc_data udc_data;
+
+static struct resource udc_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_UDP,
+               .end    = AT572D940HF_BASE_UDP + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_UDP,
+               .end    = AT572D940HF_ID_UDP,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_udc_device = {
+       .name           = "at91_udc",
+       .id             = -1,
+       .dev            = {
+                               .platform_data          = &udc_data,
+       },
+       .resource       = udc_resources,
+       .num_resources  = ARRAY_SIZE(udc_resources),
+};
+
+void __init at91_add_device_udc(struct at91_udc_data *data)
+{
+       if (!data)
+               return;
+
+       if (data->vbus_pin) {
+               at91_set_gpio_input(data->vbus_pin, 0);
+               at91_set_deglitch(data->vbus_pin, 1);
+       }
+
+       /* Pullup pin is handled internally */
+
+       udc_data = *data;
+       platform_device_register(&at572d940hf_udc_device);
+}
+#else
+void __init at91_add_device_udc(struct at91_udc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
+static u64 eth_dmamask = DMA_BIT_MASK(32);
+static struct at91_eth_data eth_data;
+
+static struct resource eth_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_EMAC,
+               .end    = AT572D940HF_BASE_EMAC + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_EMAC,
+               .end    = AT572D940HF_ID_EMAC,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_eth_device = {
+       .name           = "macb",
+       .id             = -1,
+       .dev            = {
+                       .dma_mask               = &eth_dmamask,
+                       .coherent_dma_mask      = DMA_BIT_MASK(32),
+                       .platform_data          = &eth_data,
+       },
+       .resource       = eth_resources,
+       .num_resources  = ARRAY_SIZE(eth_resources),
+};
+
+void __init at91_add_device_eth(struct at91_eth_data *data)
+{
+       if (!data)
+               return;
+
+       if (data->phy_irq_pin) {
+               at91_set_gpio_input(data->phy_irq_pin, 0);
+               at91_set_deglitch(data->phy_irq_pin, 1);
+       }
+
+       /* Only RMII is supported */
+       data->is_rmii = 1;
+
+       /* Pins used for RMII */
+       at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXCK_EREFCK */
+       at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
+       at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERX0 */
+       at91_set_A_periph(AT91_PIN_PA19, 0);    /* ERX1 */
+       at91_set_A_periph(AT91_PIN_PA20, 0);    /* ERXER */
+       at91_set_A_periph(AT91_PIN_PA23, 0);    /* ETXEN */
+       at91_set_A_periph(AT91_PIN_PA21, 0);    /* ETX0 */
+       at91_set_A_periph(AT91_PIN_PA22, 0);    /* ETX1 */
+       at91_set_A_periph(AT91_PIN_PA13, 0);    /* EMDIO */
+       at91_set_A_periph(AT91_PIN_PA14, 0);    /* EMDC */
+
+       eth_data = *data;
+       platform_device_register(&at572d940hf_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct at91_eth_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+static u64 mmc_dmamask = DMA_BIT_MASK(32);
+static struct at91_mmc_data mmc_data;
+
+static struct resource mmc_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_MCI,
+               .end    = AT572D940HF_BASE_MCI + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_MCI,
+               .end    = AT572D940HF_ID_MCI,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_mmc_device = {
+       .name           = "at91_mci",
+       .id             = -1,
+       .dev            = {
+                               .dma_mask               = &mmc_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+                               .platform_data          = &mmc_data,
+       },
+       .resource       = mmc_resources,
+       .num_resources  = ARRAY_SIZE(mmc_resources),
+};
+
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+{
+       if (!data)
+               return;
+
+       /* input/irq */
+       if (data->det_pin) {
+               at91_set_gpio_input(data->det_pin, 1);
+               at91_set_deglitch(data->det_pin, 1);
+       }
+       if (data->wp_pin)
+               at91_set_gpio_input(data->wp_pin, 1);
+       if (data->vcc_pin)
+               at91_set_gpio_output(data->vcc_pin, 0);
+
+       /* CLK */
+       at91_set_A_periph(AT91_PIN_PC22, 0);
+
+       /* CMD */
+       at91_set_A_periph(AT91_PIN_PC23, 1);
+
+       /* DAT0, maybe DAT1..DAT3 */
+       at91_set_A_periph(AT91_PIN_PC24, 1);
+       if (data->wire4) {
+               at91_set_A_periph(AT91_PIN_PC25, 1);
+               at91_set_A_periph(AT91_PIN_PC26, 1);
+               at91_set_A_periph(AT91_PIN_PC27, 1);
+       }
+
+       mmc_data = *data;
+       platform_device_register(&at572d940hf_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
+static struct atmel_nand_data nand_data;
+
+#define NAND_BASE      AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
+       {
+               .start  = NAND_BASE,
+               .end    = NAND_BASE + SZ_256M - 1,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct platform_device at572d940hf_nand_device = {
+       .name           = "atmel_nand",
+       .id             = -1,
+       .dev            = {
+                               .platform_data  = &nand_data,
+       },
+       .resource       = nand_resources,
+       .num_resources  = ARRAY_SIZE(nand_resources),
+};
+
+void __init at91_add_device_nand(struct atmel_nand_data *data)
+{
+       unsigned long csa;
+
+       if (!data)
+               return;
+
+       csa = at91_sys_read(AT91_MATRIX_EBICSA);
+       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+       /* enable pin */
+       if (data->enable_pin)
+               at91_set_gpio_output(data->enable_pin, 1);
+
+       /* ready/busy pin */
+       if (data->rdy_pin)
+               at91_set_gpio_input(data->rdy_pin, 1);
+
+       /* card detect pin */
+       if (data->det_pin)
+               at91_set_gpio_input(data->det_pin, 1);
+
+       at91_set_A_periph(AT91_PIN_PB28, 0);            /* A[22] */
+       at91_set_B_periph(AT91_PIN_PA28, 0);            /* NANDOE */
+       at91_set_B_periph(AT91_PIN_PA29, 0);            /* NANDWE */
+
+       nand_data = *data;
+       platform_device_register(&at572d940hf_nand_device);
+}
+
+#else
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+/*
+ * Prefer the GPIO code since the TWI controller isn't robust
+ * (gets overruns and underruns under load) and can only issue
+ * repeated STARTs in one scenario (the driver doesn't yet handle them).
+ */
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+
+static struct i2c_gpio_platform_data pdata = {
+       .sda_pin                = AT91_PIN_PC7,
+       .sda_is_open_drain      = 1,
+       .scl_pin                = AT91_PIN_PC8,
+       .scl_is_open_drain      = 1,
+       .udelay                 = 2,            /* ~100 kHz */
+};
+
+static struct platform_device at572d940hf_twi_device {
+       .name                   = "i2c-gpio",
+       .id                     = -1,
+       .dev.platform_data      = &pdata,
+};
+
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+       at91_set_GPIO_periph(AT91_PIN_PC7, 1);          /* TWD (SDA) */
+       at91_set_multi_drive(AT91_PIN_PC7, 1);
+
+       at91_set_GPIO_periph(AT91_PIN_PA8, 1);          /* TWCK (SCL) */
+       at91_set_multi_drive(AT91_PIN_PC8, 1);
+
+       i2c_register_board_info(0, devices, nr_devices);
+       platform_device_register(&at572d940hf_twi_device);
+}
+
+#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+
+static struct resource twi0_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_TWI0,
+               .end    = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_TWI0,
+               .end    = AT572D940HF_ID_TWI0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_twi0_device = {
+       .name           = "at91_i2c",
+       .id             = 0,
+       .resource       = twi0_resources,
+       .num_resources  = ARRAY_SIZE(twi0_resources),
+};
+
+static struct resource twi1_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_TWI1,
+               .end    = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_TWI1,
+               .end    = AT572D940HF_ID_TWI1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_twi1_device = {
+       .name           = "at91_i2c",
+       .id             = 1,
+       .resource       = twi1_resources,
+       .num_resources  = ARRAY_SIZE(twi1_resources),
+};
+
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+       /* pins used for TWI0 interface */
+       at91_set_A_periph(AT91_PIN_PC7, 0);             /* TWD */
+       at91_set_multi_drive(AT91_PIN_PC7, 1);
+
+       at91_set_A_periph(AT91_PIN_PC8, 0);             /* TWCK */
+       at91_set_multi_drive(AT91_PIN_PC8, 1);
+
+       /* pins used for TWI1 interface */
+       at91_set_A_periph(AT91_PIN_PC20, 0);            /* TWD */
+       at91_set_multi_drive(AT91_PIN_PC20, 1);
+
+       at91_set_A_periph(AT91_PIN_PC21, 0);            /* TWCK */
+       at91_set_multi_drive(AT91_PIN_PC21, 1);
+
+       i2c_register_board_info(0, devices, nr_devices);
+       platform_device_register(&at572d940hf_twi0_device);
+       platform_device_register(&at572d940hf_twi1_device);
+}
+#else
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+static struct resource spi0_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_SPI0,
+               .end    = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_SPI0,
+               .end    = AT572D940HF_ID_SPI0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_spi0_device = {
+       .name           = "atmel_spi",
+       .id             = 0,
+       .dev            = {
+                               .dma_mask               = &spi_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+       .resource       = spi0_resources,
+       .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
+
+static struct resource spi1_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_SPI1,
+               .end    = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_SPI1,
+               .end    = AT572D940HF_ID_SPI1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_spi1_device = {
+       .name           = "atmel_spi",
+       .id             = 1,
+       .dev            = {
+                               .dma_mask               = &spi_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+       },
+       .resource       = spi1_resources,
+       .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
+
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+       int i;
+       unsigned long cs_pin;
+       short enable_spi0 = 0;
+       short enable_spi1 = 0;
+
+       /* Choose SPI chip-selects */
+       for (i = 0; i < nr_devices; i++) {
+               if (devices[i].controller_data)
+                       cs_pin = (unsigned long) devices[i].controller_data;
+               else if (devices[i].bus_num == 0)
+                       cs_pin = spi0_standard_cs[devices[i].chip_select];
+               else
+                       cs_pin = spi1_standard_cs[devices[i].chip_select];
+
+               if (devices[i].bus_num == 0)
+                       enable_spi0 = 1;
+               else
+                       enable_spi1 = 1;
+
+               /* enable chip-select pin */
+               at91_set_gpio_output(cs_pin, 1);
+
+               /* pass chip-select pin to driver */
+               devices[i].controller_data = (void *) cs_pin;
+       }
+
+       spi_register_board_info(devices, nr_devices);
+
+       /* Configure SPI bus(es) */
+       if (enable_spi0) {
+               at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
+               at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
+               at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
+
+               at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk");
+               platform_device_register(&at572d940hf_spi0_device);
+       }
+       if (enable_spi1) {
+               at91_set_A_periph(AT91_PIN_PC0, 0);     /* SPI1_MISO */
+               at91_set_A_periph(AT91_PIN_PC1, 0);     /* SPI1_MOSI */
+               at91_set_A_periph(AT91_PIN_PC2, 0);     /* SPI1_SPCK */
+
+               at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk");
+               platform_device_register(&at572d940hf_spi1_device);
+       }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_TCB,
+               .end    = AT572D940HF_BASE_TCB + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_TC0,
+               .end    = AT572D940HF_ID_TC0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [2] = {
+               .start  = AT572D940HF_ID_TC1,
+               .end    = AT572D940HF_ID_TC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [3] = {
+               .start  = AT572D940HF_ID_TC2,
+               .end    = AT572D940HF_ID_TC2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device at572d940hf_tcb_device = {
+       .name           = "atmel_tcb",
+       .id             = 0,
+       .resource       = tcb_resources,
+       .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+       /* this chip has a separate clock and irq for each TC channel */
+       at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk");
+       at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk");
+       at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk");
+       platform_device_register(&at572d940hf_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  RTT
+ * -------------------------------------------------------------------- */
+
+static struct resource rtt_resources[] = {
+       {
+               .start  = AT91_BASE_SYS + AT91_RTT,
+               .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+               .flags  = IORESOURCE_MEM,
+       }
+};
+
+static struct platform_device at572d940hf_rtt_device = {
+       .name           = "at91_rtt",
+       .id             = 0,
+       .resource       = rtt_resources,
+       .num_resources  = ARRAY_SIZE(rtt_resources),
+};
+
+static void __init at91_add_device_rtt(void)
+{
+       platform_device_register(&at572d940hf_rtt_device);
+}
+
+
+/* --------------------------------------------------------------------
+ *  Watchdog
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct platform_device at572d940hf_wdt_device = {
+       .name           = "at91_wdt",
+       .id             = -1,
+       .num_resources  = 0,
+};
+
+static void __init at91_add_device_watchdog(void)
+{
+       platform_device_register(&at572d940hf_wdt_device);
+}
+#else
+static void __init at91_add_device_watchdog(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+       [0] = {
+               .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+               .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT91_ID_SYS,
+               .end    = AT91_ID_SYS,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data dbgu_data = {
+       .use_dma_tx     = 0,
+       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+       .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+
+static u64 dbgu_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_dbgu_device = {
+       .name           = "atmel_usart",
+       .id             = 0,
+       .dev            = {
+                               .dma_mask               = &dbgu_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+                               .platform_data          = &dbgu_data,
+       },
+       .resource       = dbgu_resources,
+       .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+
+static inline void configure_dbgu_pins(void)
+{
+       at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
+       at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
+}
+
+static struct resource uart0_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_US0,
+               .end    = AT572D940HF_BASE_US0 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_US0,
+               .end    = AT572D940HF_ID_US0,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data uart0_data = {
+       .use_dma_tx     = 1,
+       .use_dma_rx     = 1,
+};
+
+static u64 uart0_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart0_device = {
+       .name           = "atmel_usart",
+       .id             = 1,
+       .dev            = {
+                               .dma_mask               = &uart0_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+                               .platform_data          = &uart0_data,
+       },
+       .resource       = uart0_resources,
+       .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+
+static inline void configure_usart0_pins(unsigned pins)
+{
+       at91_set_A_periph(AT91_PIN_PA8, 1);             /* TXD0 */
+       at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
+
+       if (pins & ATMEL_UART_RTS)
+               at91_set_A_periph(AT91_PIN_PA10, 0);    /* RTS0 */
+       if (pins & ATMEL_UART_CTS)
+               at91_set_A_periph(AT91_PIN_PA9, 0);     /* CTS0 */
+}
+
+static struct resource uart1_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_US1,
+               .end    = AT572D940HF_BASE_US1 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_US1,
+               .end    = AT572D940HF_ID_US1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data uart1_data = {
+       .use_dma_tx     = 1,
+       .use_dma_rx     = 1,
+};
+
+static u64 uart1_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart1_device = {
+       .name           = "atmel_usart",
+       .id             = 2,
+       .dev            = {
+                               .dma_mask               = &uart1_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+                               .platform_data          = &uart1_data,
+       },
+       .resource       = uart1_resources,
+       .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+
+static inline void configure_usart1_pins(unsigned pins)
+{
+       at91_set_A_periph(AT91_PIN_PC10, 1);            /* TXD1 */
+       at91_set_A_periph(AT91_PIN_PC9 , 0);            /* RXD1 */
+
+       if (pins & ATMEL_UART_RTS)
+               at91_set_A_periph(AT91_PIN_PC12, 0);    /* RTS1 */
+       if (pins & ATMEL_UART_CTS)
+               at91_set_A_periph(AT91_PIN_PC11, 0);    /* CTS1 */
+}
+
+static struct resource uart2_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_BASE_US2,
+               .end    = AT572D940HF_BASE_US2 + SZ_16K - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = AT572D940HF_ID_US2,
+               .end    = AT572D940HF_ID_US2,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct atmel_uart_data uart2_data = {
+       .use_dma_tx     = 1,
+       .use_dma_rx     = 1,
+};
+
+static u64 uart2_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart2_device = {
+       .name           = "atmel_usart",
+       .id             = 3,
+       .dev            = {
+                               .dma_mask               = &uart2_dmamask,
+                               .coherent_dma_mask      = DMA_BIT_MASK(32),
+                               .platform_data          = &uart2_data,
+       },
+       .resource       = uart2_resources,
+       .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+
+static inline void configure_usart2_pins(unsigned pins)
+{
+       at91_set_A_periph(AT91_PIN_PC15, 1);            /* TXD2 */
+       at91_set_A_periph(AT91_PIN_PC14, 0);            /* RXD2 */
+
+       if (pins & ATMEL_UART_RTS)
+               at91_set_A_periph(AT91_PIN_PC17, 0);    /* RTS2 */
+       if (pins & ATMEL_UART_CTS)
+               at91_set_A_periph(AT91_PIN_PC16, 0);    /* CTS2 */
+}
+
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];  /* the UARTs to use */
+struct platform_device *atmel_default_console_device;  /* the serial console device */
+
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
+{
+       struct platform_device *pdev;
+
+       switch (id) {
+               case 0:         /* DBGU */
+                       pdev = &at572d940hf_dbgu_device;
+                       configure_dbgu_pins();
+                       at91_clock_associate("mck", &pdev->dev, "usart");
+                       break;
+               case AT572D940HF_ID_US0:
+                       pdev = &at572d940hf_uart0_device;
+                       configure_usart0_pins(pins);
+                       at91_clock_associate("usart0_clk", &pdev->dev, "usart");
+                       break;
+               case AT572D940HF_ID_US1:
+                       pdev = &at572d940hf_uart1_device;
+                       configure_usart1_pins(pins);
+                       at91_clock_associate("usart1_clk", &pdev->dev, "usart");
+                       break;
+               case AT572D940HF_ID_US2:
+                       pdev = &at572d940hf_uart2_device;
+                       configure_usart2_pins(pins);
+                       at91_clock_associate("usart2_clk", &pdev->dev, "usart");
+                       break;
+               default:
+                       return;
+       }
+       pdev->id = portnr;              /* update to mapped ID */
+
+       if (portnr < ATMEL_MAX_UART)
+               at91_uarts[portnr] = pdev;
+}
+
+void __init at91_set_serial_console(unsigned portnr)
+{
+       if (portnr < ATMEL_MAX_UART)
+               atmel_default_console_device = at91_uarts[portnr];
+}
+
+void __init at91_add_device_serial(void)
+{
+       int i;
+
+       for (i = 0; i < ATMEL_MAX_UART; i++) {
+               if (at91_uarts[i])
+                       platform_device_register(at91_uarts[i]);
+       }
+
+       if (!atmel_default_console_device)
+               printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+
+#else
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
+void __init at91_set_serial_console(unsigned portnr) {}
+void __init at91_add_device_serial(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  mAgic
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_MAGICV
+static struct resource mAgic_resources[] = {
+       {
+               .start = AT91_MAGIC_PM_BASE,
+               .end   = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = AT91_MAGIC_DM_I_BASE,
+               .end   = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = AT91_MAGIC_DM_F_BASE,
+               .end   = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = AT91_MAGIC_DM_DB_BASE,
+               .end   = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = AT91_MAGIC_REGS_BASE,
+               .end   = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = AT91_MAGIC_EXTPAGE_BASE,
+               .end   = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start  = AT572D940HF_ID_MSIRQ0,
+               .end    = AT572D940HF_ID_MSIRQ0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .start  = AT572D940HF_ID_MHALT,
+               .end    = AT572D940HF_ID_MHALT,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .start  = AT572D940HF_ID_MEXC,
+               .end    = AT572D940HF_ID_MEXC,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .start  = AT572D940HF_ID_MEDMA,
+               .end    = AT572D940HF_ID_MEDMA,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device mAgic_device = {
+       .name           = "mAgic",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(mAgic_resources),
+       .resource       = mAgic_resources,
+};
+
+void __init at91_add_device_mAgic(void)
+{
+       platform_device_register(&mAgic_device);
+}
+#else
+void __init at91_add_device_mAgic(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+       at91_add_device_rtt();
+       at91_add_device_watchdog();
+       at91_add_device_tc();
+       return 0;
+}
+
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
new file mode 100644 (file)
index 0000000..5daff27
--- /dev/null
@@ -0,0 +1,328 @@
+/*
+ * linux/arch/arm/mach-at91/board-at572d940hf_ek.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ds1305.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+
+static void __init eb_map_io(void)
+{
+       /* Initialize processor: 12.500 MHz crystal */
+       at572d940hf_initialize(12000000);
+
+       /* DBGU on ttyS0. (Rx & Tx only) */
+       at91_register_uart(0, 0, 0);
+
+       /* USART0 on ttyS1. (Rx & Tx only) */
+       at91_register_uart(AT572D940HF_ID_US0, 1, 0);
+
+       /* USART1 on ttyS2. (Rx & Tx only) */
+       at91_register_uart(AT572D940HF_ID_US1, 2, 0);
+
+       /* USART2 on ttyS3. (Tx & Rx only */
+       at91_register_uart(AT572D940HF_ID_US2, 3, 0);
+
+       /* set serial console to ttyS0 (ie, DBGU) */
+       at91_set_serial_console(0);
+}
+
+static void __init eb_init_irq(void)
+{
+       at572d940hf_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host Port
+ */
+static struct at91_usbh_data __initdata eb_usbh_data = {
+       .ports          = 2,
+};
+
+
+/*
+ * USB Device Port
+ */
+static struct at91_udc_data __initdata eb_udc_data = {
+       .vbus_pin       = 0,            /* no VBUS detection,UDC always on */
+       .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata eb_mmc_data = {
+       .wire4          = 1,
+/*     .det_pin        = ... not connected */
+/*     .wp_pin         = ... not connected */
+/*     .vcc_pin        = ... not connected */
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata eb_eth_data = {
+       .phy_irq_pin    = AT91_PIN_PB25,
+       .is_rmii        = 1,
+};
+
+/*
+ * NOR flash
+ */
+
+static struct mtd_partition eb_nor_partitions[] = {
+       {
+               .name           = "Raw Environment",
+               .offset         = 0,
+               .size           = SZ_4M,
+               .mask_flags     = 0,
+       },
+       {
+               .name           = "OS FS",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = 3 * SZ_1M,
+               .mask_flags     = 0,
+       },
+       {
+               .name           = "APP FS",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = MTDPART_SIZ_FULL,
+               .mask_flags     = 0,
+       },
+};
+
+static void nor_flash_set_vpp(struct map_info* mi, int i) {
+};
+
+static struct physmap_flash_data nor_flash_data = {
+       .width          = 4,
+       .parts          = eb_nor_partitions,
+       .nr_parts       = ARRAY_SIZE(eb_nor_partitions),
+       .set_vpp        = nor_flash_set_vpp,
+};
+
+static struct resource nor_flash_resources[] = {
+       {
+               .start  = AT91_CHIPSELECT_0,
+               .end    = AT91_CHIPSELECT_0 + SZ_16M - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device nor_flash = {
+       .name           = "physmap-flash",
+       .id             = 0,
+       .dev            = {
+                               .platform_data = &nor_flash_data,
+                       },
+       .resource       = nor_flash_resources,
+       .num_resources  = ARRAY_SIZE(nor_flash_resources),
+};
+
+static struct sam9_smc_config __initdata eb_nor_smc_config = {
+       .ncs_read_setup         = 1,
+       .nrd_setup              = 1,
+       .ncs_write_setup        = 1,
+       .nwe_setup              = 1,
+
+       .ncs_read_pulse         = 7,
+       .nrd_pulse              = 7,
+       .ncs_write_pulse        = 7,
+       .nwe_pulse              = 7,
+
+       .read_cycle             = 9,
+       .write_cycle            = 9,
+
+       .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32,
+       .tdf_cycles             = 1,
+};
+
+static void __init eb_add_device_nor(void)
+{
+       /* configure chip-select 0 (NOR) */
+       sam9_smc_configure(0, &eb_nor_smc_config);
+       platform_device_register(&nor_flash);
+}
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata eb_nand_partition[] = {
+       {
+               .name   = "Partition 1",
+               .offset = 0,
+               .size   = SZ_16M,
+       },
+       {
+               .name   = "Partition 2",
+               .offset = MTDPART_OFS_NXTBLK,
+               .size   = MTDPART_SIZ_FULL,
+       }
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+       *num_partitions = ARRAY_SIZE(eb_nand_partition);
+       return eb_nand_partition;
+}
+
+static struct atmel_nand_data __initdata eb_nand_data = {
+       .ale            = 22,
+       .cle            = 21,
+/*     .det_pin        = ... not connected */
+/*     .rdy_pin        = AT91_PIN_PC16, */
+       .enable_pin     = AT91_PIN_PA15,
+       .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+       .bus_width_16   = 1,
+#else
+       .bus_width_16   = 0,
+#endif
+};
+
+static struct sam9_smc_config __initdata eb_nand_smc_config = {
+       .ncs_read_setup         = 0,
+       .nrd_setup              = 0,
+       .ncs_write_setup        = 1,
+       .nwe_setup              = 1,
+
+       .ncs_read_pulse         = 3,
+       .nrd_pulse              = 3,
+       .ncs_write_pulse        = 3,
+       .nwe_pulse              = 3,
+
+       .read_cycle             = 5,
+       .write_cycle            = 5,
+
+       .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+       .tdf_cycles             = 12,
+};
+
+static void __init eb_add_device_nand(void)
+{
+       /* setup bus-width (8 or 16) */
+       if (eb_nand_data.bus_width_16)
+               eb_nand_smc_config.mode |= AT91_SMC_DBW_16;
+       else
+               eb_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+       /* configure chip-select 3 (NAND) */
+       sam9_smc_configure(3, &eb_nand_smc_config);
+
+       at91_add_device_nand(&eb_nand_data);
+}
+
+
+/*
+ * SPI devices
+ */
+static struct resource rtc_resources[] = {
+       [0] = {
+               .start  = AT572D940HF_ID_IRQ1,
+               .end    = AT572D940HF_ID_IRQ1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct ds1305_platform_data ds1306_data = {
+       .is_ds1306      = true,
+       .en_1hz         = false,
+};
+
+static struct spi_board_info eb_spi_devices[] = {
+       {       /* RTC Dallas DS1306 */
+               .modalias       = "rtc-ds1305",
+               .chip_select    = 3,
+               .mode           = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA,
+               .max_speed_hz   = 500000,
+               .bus_num        = 0,
+               .irq            = AT572D940HF_ID_IRQ1,
+               .platform_data  = (void *) &ds1306_data,
+       },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+       {       /* Dataflash card */
+               .modalias       = "mtd_dataflash",
+               .chip_select    = 0,
+               .max_speed_hz   = 15 * 1000 * 1000,
+               .bus_num        = 0,
+       },
+#endif
+};
+
+static void __init eb_board_init(void)
+{
+       /* Serial */
+       at91_add_device_serial();
+       /* USB Host */
+       at91_add_device_usbh(&eb_usbh_data);
+       /* USB Device */
+       at91_add_device_udc(&eb_udc_data);
+       /* I2C */
+       at91_add_device_i2c(NULL, 0);
+       /* NOR */
+       eb_add_device_nor();
+       /* NAND */
+       eb_add_device_nand();
+       /* SPI */
+       at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices));
+       /* MMC */
+       at91_add_device_mmc(0, &eb_mmc_data);
+       /* Ethernet */
+       at91_add_device_eth(&eb_eth_data);
+       /* mAgic */
+       at91_add_device_mAgic();
+}
+
+MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
+       /* Maintainer: Atmel <costa.antonior@gmail.com> */
+       .phys_io        = AT91_BASE_SYS,
+       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+       .boot_params    = AT91_SDRAM_BASE + 0x100,
+       .timer          = &at91sam926x_timer,
+       .map_io         = eb_map_io,
+       .init_irq       = eb_init_irq,
+       .init_machine   = eb_board_init,
+MACHINE_END
index c042dcf4725fc8ec3166cb9ddc7436109f1fca6c..7f7da439341fabc4e85b6febeb8b1f3e2cd6f4ee 100644 (file)
@@ -29,6 +29,7 @@
 #include <mach/cpu.h>
 
 #include "clock.h"
+#include "generic.h"
 
 
 /*
@@ -628,7 +629,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
-                  cpu_is_at91sam9g10()) {
+                  cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
        } else if (cpu_is_at91cap9()) {
@@ -711,12 +712,13 @@ int __init at91_clock_init(unsigned long main_clock)
        /*
         * USB HS clock init
         */
-       if (cpu_has_utmi())
+       if (cpu_has_utmi()) {
                /*
                 * multiplier is hard-wired to 40
                 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                 */
                utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+       }
 
        /*
         * USB FS clock init
@@ -746,7 +748,7 @@ int __init at91_clock_init(unsigned long main_clock)
                mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
                        freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
        } else {
-               mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+               mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
        }
 
        /* Register the PMC's standard clocks */
index 1ba3b95ff3594f10cd30c7b433b38e0f0e497d4e..6cf4b78e175d7a47775463d03f4f6c7146a2910e 100644 (file)
@@ -22,7 +22,7 @@ struct clk {
        struct clk      *parent;
        u32             pmc_mask;
        void            (*mode)(struct clk *, int);
-       unsigned        id:2;           /* PCK0..3, or 32k/main/a/b */
+       unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
        unsigned        type;           /* clock type */
        u16             users;
 };
index 88e413b38480233f40d61bf5b8edbb1a8d46d432..65c3dc5ba0d0c608e649565121ac59e3ce4d1159 100644 (file)
@@ -17,6 +17,7 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
 extern void __init at91sam9g45_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91cap9_initialize(unsigned long main_clock);
+extern void __init at572d940hf_initialize(unsigned long main_clock);
 
  /* Interrupts */
 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -27,6 +28,7 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91cap9_init_interrupts(unsigned int priority[]);
+extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 
  /* Timer */
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
new file mode 100644 (file)
index 0000000..2d9b0af
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * include/mach/at572d940hf.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef AT572D940HF_H
+#define AT572D940HF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ            0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS            1       /* System Peripherals */
+#define AT572D940HF_ID_PIOA    2       /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB    3       /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC    4       /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC    5       /* MACB ethernet controller */
+#define AT572D940HF_ID_US0     6       /* USART 0 */
+#define AT572D940HF_ID_US1     7       /* USART 1 */
+#define AT572D940HF_ID_US2     8       /* USART 2 */
+#define AT572D940HF_ID_MCI     9       /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP     10      /* USB Device Port */
+#define AT572D940HF_ID_TWI0    11      /* Two-Wire Interface 0 */
+#define AT572D940HF_ID_SPI0    12      /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1    13      /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC0    14      /* Serial Synchronous Controller 0 */
+#define AT572D940HF_ID_SSC1    15      /* Serial Synchronous Controller 1 */
+#define AT572D940HF_ID_SSC2    16      /* Serial Synchronous Controller 2 */
+#define AT572D940HF_ID_TC0     17      /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1     18      /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2     19      /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP     20      /* USB Host port */
+#define AT572D940HF_ID_SSC3    21      /* Serial Synchronous Controller 3 */
+#define AT572D940HF_ID_TWI1    22      /* Two-Wire Interface 1 */
+#define AT572D940HF_ID_CAN0    23      /* CAN Controller 0 */
+#define AT572D940HF_ID_CAN1    24      /* CAN Controller 1 */
+#define AT572D940HF_ID_MHALT   25      /* mAgicV HALT line */
+#define AT572D940HF_ID_MSIRQ0  26      /* mAgicV SIRQ0 line */
+#define AT572D940HF_ID_MEXC    27      /* mAgicV exception line */
+#define AT572D940HF_ID_MEDMA   28      /* mAgicV end of DMA line */
+#define AT572D940HF_ID_IRQ0    29      /* External Interrupt Source (IRQ0) */
+#define AT572D940HF_ID_IRQ1    30      /* External Interrupt Source (IRQ1) */
+#define AT572D940HF_ID_IRQ2    31      /* External Interrupt Source (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB   0xfffa0000
+#define AT572D940HF_BASE_TC0   0xfffa0000
+#define AT572D940HF_BASE_TC1   0xfffa0040
+#define AT572D940HF_BASE_TC2   0xfffa0080
+#define AT572D940HF_BASE_UDP   0xfffa4000
+#define AT572D940HF_BASE_MCI   0xfffa8000
+#define AT572D940HF_BASE_TWI0  0xfffac000
+#define AT572D940HF_BASE_US0   0xfffb0000
+#define AT572D940HF_BASE_US1   0xfffb4000
+#define AT572D940HF_BASE_US2   0xfffb8000
+#define AT572D940HF_BASE_SSC0  0xfffbc000
+#define AT572D940HF_BASE_SSC1  0xfffc0000
+#define AT572D940HF_BASE_SSC2  0xfffc4000
+#define AT572D940HF_BASE_SPI0  0xfffc8000
+#define AT572D940HF_BASE_SPI1  0xfffcc000
+#define AT572D940HF_BASE_SSC3  0xfffd0000
+#define AT572D940HF_BASE_TWI1  0xfffd4000
+#define AT572D940HF_BASE_EMAC  0xfffd8000
+#define AT572D940HF_BASE_CAN0  0xfffdc000
+#define AT572D940HF_BASE_CAN1  0xfffe0000
+#define AT91_BASE_SYS          0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA      (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB      (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC      (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_RTT       (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT       (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT       (0xfffffd40 - AT91_BASE_SYS)
+
+#define AT91_USART0    AT572D940HF_ID_US0
+#define AT91_USART1    AT572D940HF_ID_US1
+#define AT91_USART2    AT572D940HF_ID_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_SRAM_BASE  0x00300000      /* Internal SRAM base address */
+#define AT572D940HF_SRAM_SIZE  (48 * SZ_1K)    /* Internal SRAM size (48Kb) */
+
+#define AT572D940HF_ROM_BASE   0x00400000      /* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE   SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT572D940HF_UHP_BASE   0x00500000      /* USB Host controller */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
new file mode 100644 (file)
index 0000000..b6751df
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * include/mach//at572d940hf_matrix.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef AT572D940HF_MATRIX_H
+#define AT572D940HF_MATRIX_H
+
+#define AT91_MATRIX_MCFG0      (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1      (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2      (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3      (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4      (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5      (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+
+#define                AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                        AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                        AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                        AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                        AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                        AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define                AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define                AT91_MATRIX_FIXED_DEFMSTR       (0x7  << 18)    /* Fixed Index of Default Master */
+#define                AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                        AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                        AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0      (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1      (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2      (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3      (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4      (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+
+#define                AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define                AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define                AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define                AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define                AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define                AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define                AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+
+#define AT91_MATRIX_MRCR       (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define                AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define                AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SFR0       (AT91_MATRIX + 0x110)   /* Special Function Register 0 */
+#define AT91_MATRIX_SFR1       (AT91_MATRIX + 0x114)   /* Special Function Register 1 */
+#define AT91_MATRIX_SFR2       (AT91_MATRIX + 0x118)   /* Special Function Register 2 */
+#define AT91_MATRIX_SFR3       (AT91_MATRIX + 0x11C)   /* Special Function Register 3 */
+#define AT91_MATRIX_SFR4       (AT91_MATRIX + 0x120)   /* Special Function Register 4 */
+#define AT91_MATRIX_SFR5       (AT91_MATRIX + 0x124)   /* Special Function Register 5 */
+#define AT91_MATRIX_SFR6       (AT91_MATRIX + 0x128)   /* Special Function Register 6 */
+#define AT91_MATRIX_SFR7       (AT91_MATRIX + 0x12C)   /* Special Function Register 7 */
+#define AT91_MATRIX_SFR8       (AT91_MATRIX + 0x130)   /* Special Function Register 8 */
+#define AT91_MATRIX_SFR9       (AT91_MATRIX + 0x134)   /* Special Function Register 9 */
+#define AT91_MATRIX_SFR10      (AT91_MATRIX + 0x138)   /* Special Function Register 10 */
+#define AT91_MATRIX_SFR11      (AT91_MATRIX + 0x13C)   /* Special Function Register 11 */
+#define AT91_MATRIX_SFR12      (AT91_MATRIX + 0x140)   /* Special Function Register 12 */
+#define AT91_MATRIX_SFR13      (AT91_MATRIX + 0x144)   /* Special Function Register 13 */
+#define AT91_MATRIX_SFR14      (AT91_MATRIX + 0x148)   /* Special Function Register 14 */
+#define AT91_MATRIX_SFR15      (AT91_MATRIX + 0x14C)   /* Special Function Register 15 */
+
+
+/*
+ * The following registers / bits are not defined in the Datasheet (Revision A)
+ */
+
+#define AT91_MATRIX_TCR                (AT91_MATRIX + 0x100)   /* TCM Configuration Register */
+#define                AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                        AT91_MATRIX_ITCM_0              (0 << 0)
+#define                        AT91_MATRIX_ITCM_16             (5 << 0)
+#define                        AT91_MATRIX_ITCM_32             (6 << 0)
+#define                        AT91_MATRIX_ITCM_64             (7 << 0)
+#define                AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                        AT91_MATRIX_DTCM_0              (0 << 4)
+#define                        AT91_MATRIX_DTCM_16             (5 << 4)
+#define                        AT91_MATRIX_DTCM_32             (6 << 4)
+#define                        AT91_MATRIX_DTCM_64             (7 << 4)
+
+#define AT91_MATRIX_EBICSA     (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define                AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                        AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                        AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define                AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                        AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                        AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define                AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                        AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                        AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define                AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                        AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                        AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define                AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+
+#endif
index 64589eaaaee8f8d57ae9044ed587eaa2bd329f66..e46f93e34aab4666b14932a9c6c451847b2c8b54 100644 (file)
@@ -32,6 +32,7 @@
 #define                AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
 #define                AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
 #define                AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define                AT91_PMC_PCK4           (1 << 12)               /* Programmable Clock 4 [AT572D940HF only] */
 #define                AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define                AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
index bb6f6a7ba5e0bf387ed00985caa03e65f2e988a2..ceaec6c16eb2d801e68f50f8ea6975293027af42 100644 (file)
@@ -87,7 +87,7 @@ struct at91_eth_data {
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-       || defined(CONFIG_ARCH_AT91SAM9G45)
+       || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
 #define eth_platform_data      at91_eth_data
 #endif
 
@@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
+ /* AT572D940HF DSP */
+extern void __init at91_add_device_mAgic(void);
+
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
 
index c22df30ed5e5d5784a6d7f09350ea17cd6b53706..5a0650101d45f20112b46cb31bddb1b32000a430 100644 (file)
@@ -33,6 +33,8 @@
 #define ARCH_ID_AT91SAM9XE256  0x329a93a0
 #define ARCH_ID_AT91SAM9XE512  0x329aa3a0
 
+#define ARCH_ID_AT572D940HF    0x0e0303e0
+
 #define ARCH_ID_AT91M40800     0x14080044
 #define ARCH_ID_AT91R40807     0x44080746
 #define ARCH_ID_AT91M40807     0x14080745
@@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91cap9_revC() (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT572D940HF
+#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
+#else
+#define cpu_is_at572d940hf() (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
index a0df8b022df27bd3ede5e22aa2d3dff3f9c98fd3..3d64a75e3ed5be8a0566b343653b3af965a47c6f 100644 (file)
@@ -32,6 +32,8 @@
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
+#elif defined(CONFIG_ARCH_AT572D940HF)
+#include <mach/at572d940hf.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
index 31ac2d97f14cb24b85371b259a2c70b27fc6a461..05a6e8af80c4e1f3c4b4983c88821c1e1bd0ad26 100644 (file)
 #define AT91X40_MASTER_CLOCK   40000000
 #define CLOCK_TICK_RATE                (AT91X40_MASTER_CLOCK)
 
+#elif defined(CONFIG_ARCH_AT572D940HF)
+
+#define AT572D940HF_MASTER_CLOCK       80000000
+#define CLOCK_TICK_RATE                (AT572D940HF_MASTER_CLOCK/16)
+
 #endif
 
 #endif
index 9167c3d2a5edaf02ef6b74df0a00cab5572341ba..3a08b18f6433e28a35d3e2b4568bc6758c502082 100644 (file)
@@ -161,6 +161,20 @@ config MACH_MICRO9S
          Say 'Y' here if you want your kernel to support the
          Contec Micro9-Slim board.
 
+config MACH_SIM_ONE
+        bool "Support Simplemachines Sim.One board"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the
+          Simplemachines Sim.One board.
+
+config MACH_SNAPPER_CL15
+       bool "Support Bluewater Systems Snapper CL15 Module"
+       depends on EP93XX_SDCE0_PHYS_OFFSET
+       help
+         Say 'Y' here if you want your kernel to support the Bluewater
+         Systems Snapper CL15 Module.
+
 config MACH_TS72XX
        bool "Support Technologic Systems TS-72xx SBC"
        depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
index eae6199a9891af49845774d9ddfc5f9b9e903007..33ee2c863d1808a1015098975fed81fe238e30d7 100644 (file)
@@ -10,4 +10,6 @@ obj-$(CONFIG_MACH_ADSSPHERE)  += adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)     += edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)   += gesbc9312.o
 obj-$(CONFIG_MACH_MICRO9)      += micro9.o
+obj-$(CONFIG_MACH_SIM_ONE)     += simone.o
+obj-$(CONFIG_MACH_SNAPPER_CL15)        += snappercl15.o
 obj-$(CONFIG_MACH_TS72XX)      += ts72xx.o
index 1d0f9d8aff2e93583ba5ff0793f80d0f991f4786..49fa9f8fef4a4eb2a9f9f3a6aade40dc12b31ebe 100644 (file)
@@ -10,6 +10,8 @@
  * your option) any later version.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -447,30 +449,34 @@ static int __init ep93xx_clock_init(void)
        u32 value;
        int i;
 
-       value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
-       if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
+       /* Determine the bootloader configured pll1 rate */
+       value = __raw_readl(EP93XX_SYSCON_CLKSET1);
+       if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
                clk_pll1.rate = clk_xtali.rate;
-       } else {
+       else
                clk_pll1.rate = calc_pll_rate(value);
-       }
+
+       /* Initialize the pll1 derived clocks */
        clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
        clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
        clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
        ep93xx_dma_clock_init();
 
-       value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
-       if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
+       /* Determine the bootloader configured pll2 rate */
+       value = __raw_readl(EP93XX_SYSCON_CLKSET2);
+       if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
                clk_pll2.rate = clk_xtali.rate;
-       } else if (value & 0x00040000) {                /* PLL2 enabled?  */
+       else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
                clk_pll2.rate = calc_pll_rate(value);
-       } else {
+       else
                clk_pll2.rate = 0;
-       }
+
+       /* Initialize the pll2 derived clocks */
        clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 
-       printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
+       pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
                clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
-       printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
+       pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
                clk_f.rate / 1000000, clk_h.rate / 1000000,
                clk_p.rate / 1000000);
 
index 1f0d66561bbe158b49fdd9c3e47d3b400e340ecb..90fb591cbffa6066e0b5fb732a0079834471c357 100644 (file)
  * your option) any later version.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/timex.h>
+#include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
@@ -35,7 +38,6 @@
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
 
 #include <asm/hardware/vic.h>
 
@@ -82,13 +84,40 @@ void __init ep93xx_map_io(void)
  * to use this timer for something else.  We also use timer 4 for keeping
  * track of lost jiffies.
  */
-static unsigned int last_jiffy_time;
-
+#define EP93XX_TIMER_REG(x)            (EP93XX_TIMER_BASE + (x))
+#define EP93XX_TIMER1_LOAD             EP93XX_TIMER_REG(0x00)
+#define EP93XX_TIMER1_VALUE            EP93XX_TIMER_REG(0x04)
+#define EP93XX_TIMER1_CONTROL          EP93XX_TIMER_REG(0x08)
+#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
+#define EP93XX_TIMER123_CONTROL_MODE   (1 << 6)
+#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
+#define EP93XX_TIMER1_CLEAR            EP93XX_TIMER_REG(0x0c)
+#define EP93XX_TIMER2_LOAD             EP93XX_TIMER_REG(0x20)
+#define EP93XX_TIMER2_VALUE            EP93XX_TIMER_REG(0x24)
+#define EP93XX_TIMER2_CONTROL          EP93XX_TIMER_REG(0x28)
+#define EP93XX_TIMER2_CLEAR            EP93XX_TIMER_REG(0x2c)
+#define EP93XX_TIMER4_VALUE_LOW                EP93XX_TIMER_REG(0x60)
+#define EP93XX_TIMER4_VALUE_HIGH       EP93XX_TIMER_REG(0x64)
+#define EP93XX_TIMER4_VALUE_HIGH_ENABLE        (1 << 8)
+#define EP93XX_TIMER3_LOAD             EP93XX_TIMER_REG(0x80)
+#define EP93XX_TIMER3_VALUE            EP93XX_TIMER_REG(0x84)
+#define EP93XX_TIMER3_CONTROL          EP93XX_TIMER_REG(0x88)
+#define EP93XX_TIMER3_CLEAR            EP93XX_TIMER_REG(0x8c)
+
+#define EP93XX_TIMER123_CLOCK          508469
+#define EP93XX_TIMER4_CLOCK            983040
+
+#define TIMER1_RELOAD                  ((EP93XX_TIMER123_CLOCK / HZ) - 1)
 #define TIMER4_TICKS_PER_JIFFY         DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
 
+static unsigned int last_jiffy_time;
+
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
+       /* Writing any value clears the timer interrupt */
        __raw_writel(1, EP93XX_TIMER1_CLEAR);
+
+       /* Recover lost jiffies */
        while ((signed long)
                (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
                                                >= TIMER4_TICKS_PER_JIFFY) {
@@ -107,13 +136,18 @@ static struct irqaction ep93xx_timer_irq = {
 
 static void __init ep93xx_timer_init(void)
 {
+       u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
+                   EP93XX_TIMER123_CONTROL_CLKSEL;
+
        /* Enable periodic HZ timer.  */
-       __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
-       __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
-       __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
+       __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
+       __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
+       __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
+                       EP93XX_TIMER1_CONTROL);
 
        /* Enable lost jiffy timer.  */
-       __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
+       __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
+                       EP93XX_TIMER4_VALUE_HIGH);
 
        setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 }
@@ -134,238 +168,17 @@ struct sys_timer ep93xx_timer = {
 };
 
 
-/*************************************************************************
- * GPIO handling for EP93xx
- *************************************************************************/
-static unsigned char gpio_int_unmasked[3];
-static unsigned char gpio_int_enabled[3];
-static unsigned char gpio_int_type1[3];
-static unsigned char gpio_int_type2[3];
-static unsigned char gpio_int_debounce[3];
-
-/* Port ordering is: A B F */
-static const u8 int_type1_register_offset[3]   = { 0x90, 0xac, 0x4c };
-static const u8 int_type2_register_offset[3]   = { 0x94, 0xb0, 0x50 };
-static const u8 eoi_register_offset[3]         = { 0x98, 0xb4, 0x54 };
-static const u8 int_en_register_offset[3]      = { 0x9c, 0xb8, 0x58 };
-static const u8 int_debounce_register_offset[3]        = { 0xa8, 0xc4, 0x64 };
-
-void ep93xx_gpio_update_int_params(unsigned port)
-{
-       BUG_ON(port > 2);
-
-       __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
-
-       __raw_writeb(gpio_int_type2[port],
-               EP93XX_GPIO_REG(int_type2_register_offset[port]));
-
-       __raw_writeb(gpio_int_type1[port],
-               EP93XX_GPIO_REG(int_type1_register_offset[port]));
-
-       __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
-               EP93XX_GPIO_REG(int_en_register_offset[port]));
-}
-
-void ep93xx_gpio_int_mask(unsigned line)
-{
-       gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
-}
-
-void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
-{
-       int line = irq_to_gpio(irq);
-       int port = line >> 3;
-       int port_mask = 1 << (line & 7);
-
-       if (enable)
-               gpio_int_debounce[port] |= port_mask;
-       else
-               gpio_int_debounce[port] &= ~port_mask;
-
-       __raw_writeb(gpio_int_debounce[port],
-               EP93XX_GPIO_REG(int_debounce_register_offset[port]));
-}
-EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
-
 /*************************************************************************
  * EP93xx IRQ handling
  *************************************************************************/
-static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-       unsigned char status;
-       int i;
-
-       status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
-       for (i = 0; i < 8; i++) {
-               if (status & (1 << i)) {
-                       int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
-                       generic_handle_irq(gpio_irq);
-               }
-       }
-
-       status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
-       for (i = 0; i < 8; i++) {
-               if (status & (1 << i)) {
-                       int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
-                       generic_handle_irq(gpio_irq);
-               }
-       }
-}
-
-static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-       /*
-        * map discontiguous hw irq range to continous sw irq range:
-        *
-        *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
-        */
-       int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
-       int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
-
-       generic_handle_irq(gpio_irq);
-}
-
-static void ep93xx_gpio_irq_ack(unsigned int irq)
-{
-       int line = irq_to_gpio(irq);
-       int port = line >> 3;
-       int port_mask = 1 << (line & 7);
-
-       if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
-               gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-               ep93xx_gpio_update_int_params(port);
-       }
-
-       __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
-{
-       int line = irq_to_gpio(irq);
-       int port = line >> 3;
-       int port_mask = 1 << (line & 7);
-
-       if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-               gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-
-       gpio_int_unmasked[port] &= ~port_mask;
-       ep93xx_gpio_update_int_params(port);
-
-       __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask(unsigned int irq)
-{
-       int line = irq_to_gpio(irq);
-       int port = line >> 3;
-
-       gpio_int_unmasked[port] &= ~(1 << (line & 7));
-       ep93xx_gpio_update_int_params(port);
-}
-
-static void ep93xx_gpio_irq_unmask(unsigned int irq)
-{
-       int line = irq_to_gpio(irq);
-       int port = line >> 3;
-
-       gpio_int_unmasked[port] |= 1 << (line & 7);
-       ep93xx_gpio_update_int_params(port);
-}
-
-
-/*
- * gpio_int_type1 controls whether the interrupt is level (0) or
- * edge (1) triggered, while gpio_int_type2 controls whether it
- * triggers on low/falling (0) or high/rising (1).
- */
-static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-       struct irq_desc *desc = irq_desc + irq;
-       const int gpio = irq_to_gpio(irq);
-       const int port = gpio >> 3;
-       const int port_mask = 1 << (gpio & 7);
-
-       gpio_direction_input(gpio);
-
-       switch (type) {
-       case IRQ_TYPE_EDGE_RISING:
-               gpio_int_type1[port] |= port_mask;
-               gpio_int_type2[port] |= port_mask;
-               desc->handle_irq = handle_edge_irq;
-               break;
-       case IRQ_TYPE_EDGE_FALLING:
-               gpio_int_type1[port] |= port_mask;
-               gpio_int_type2[port] &= ~port_mask;
-               desc->handle_irq = handle_edge_irq;
-               break;
-       case IRQ_TYPE_LEVEL_HIGH:
-               gpio_int_type1[port] &= ~port_mask;
-               gpio_int_type2[port] |= port_mask;
-               desc->handle_irq = handle_level_irq;
-               break;
-       case IRQ_TYPE_LEVEL_LOW:
-               gpio_int_type1[port] &= ~port_mask;
-               gpio_int_type2[port] &= ~port_mask;
-               desc->handle_irq = handle_level_irq;
-               break;
-       case IRQ_TYPE_EDGE_BOTH:
-               gpio_int_type1[port] |= port_mask;
-               /* set initial polarity based on current input level */
-               if (gpio_get_value(gpio))
-                       gpio_int_type2[port] &= ~port_mask; /* falling */
-               else
-                       gpio_int_type2[port] |= port_mask; /* rising */
-               desc->handle_irq = handle_edge_irq;
-               break;
-       default:
-               pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
-                      type, gpio);
-               return -EINVAL;
-       }
-
-       gpio_int_enabled[port] |= port_mask;
-
-       desc->status &= ~IRQ_TYPE_SENSE_MASK;
-       desc->status |= type & IRQ_TYPE_SENSE_MASK;
-
-       ep93xx_gpio_update_int_params(port);
-
-       return 0;
-}
-
-static struct irq_chip ep93xx_gpio_irq_chip = {
-       .name           = "GPIO",
-       .ack            = ep93xx_gpio_irq_ack,
-       .mask_ack       = ep93xx_gpio_irq_mask_ack,
-       .mask           = ep93xx_gpio_irq_mask,
-       .unmask         = ep93xx_gpio_irq_unmask,
-       .set_type       = ep93xx_gpio_irq_type,
-};
-
+extern void ep93xx_gpio_init_irq(void);
 
 void __init ep93xx_init_irq(void)
 {
-       int gpio_irq;
-
        vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
        vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
 
-       for (gpio_irq = gpio_to_irq(0);
-            gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
-               set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
-               set_irq_handler(gpio_irq, handle_level_irq);
-               set_irq_flags(gpio_irq, IRQF_VALID);
-       }
-
-       set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
-       set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+       ep93xx_gpio_init_irq();
 }
 
 
@@ -572,9 +385,9 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
         * CMOS driver.
         */
        if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
-               pr_warning("ep93xx: sda != EEDAT, open drain has no effect\n");
+               pr_warning("sda != EEDAT, open drain has no effect\n");
        if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
-               pr_warning("ep93xx: scl != EECLK, open drain has no effect\n");
+               pr_warning("scl != EECLK, open drain has no effect\n");
 
        __raw_writel((data->sda_is_open_drain << 1) |
                     (data->scl_is_open_drain << 0),
index dbcac9c40a28883df558565be3c7e52c37426053..8904ca4e2e24fc9a4984bd0b88ce9d3eab52e7ea 100644 (file)
@@ -28,6 +28,8 @@
  * with this implementation.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -173,7 +175,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
 
        switch (m2p_channel_state(ch)) {
        case STATE_IDLE:
-               pr_crit("m2p_irq: dma interrupt without a dma buffer\n");
+               pr_crit("dma interrupt without a dma buffer\n");
                BUG();
                break;
 
@@ -197,7 +199,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
                break;
 
        case STATE_NEXT:
-               pr_crit("m2p_irq: dma interrupt while next\n");
+               pr_crit("dma interrupt while next\n");
                BUG();
                break;
        }
index a4a7be3080002cb2c1577eeb2cb1cfb40ec4b68c..d22d67ac8b9938cd444fa6d212cf0acdaa8beba8 100644 (file)
@@ -118,12 +118,33 @@ static void __init edb93xx_register_i2c(void)
        }
 }
 
+
+/*************************************************************************
+ * EDB93xx pwm
+ *************************************************************************/
+static void __init edb93xx_register_pwm(void)
+{
+       if (machine_is_edb9301() ||
+           machine_is_edb9302() || machine_is_edb9302a()) {
+               /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */
+               ep93xx_register_pwm(0, 1);
+       } else if (machine_is_edb9307() || machine_is_edb9307a()) {
+               /* EP9307 only has pwm.0 (PWMOUT) */
+               ep93xx_register_pwm(1, 0);
+       } else {
+               /* EP9312 and EP9315 have both */
+               ep93xx_register_pwm(1, 1);
+       }
+}
+
+
 static void __init edb93xx_init_machine(void)
 {
        ep93xx_init_devices();
        edb93xx_register_flash();
        ep93xx_register_eth(&edb93xx_eth_data, 1);
        edb93xx_register_i2c();
+       edb93xx_register_pwm();
 }
 
 
index 1ea8871e03a96db862ef27ebca06fc325baeb6aa..cc377ae8c4281324926f6d8f9c6ac645cd53b487 100644 (file)
@@ -13,6 +13,8 @@
  *  published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/seq_file.h>
 
 #include <mach/hardware.h>
 
+/*************************************************************************
+ * GPIO handling for EP93xx
+ *************************************************************************/
+static unsigned char gpio_int_unmasked[3];
+static unsigned char gpio_int_enabled[3];
+static unsigned char gpio_int_type1[3];
+static unsigned char gpio_int_type2[3];
+static unsigned char gpio_int_debounce[3];
+
+/* Port ordering is: A B F */
+static const u8 int_type1_register_offset[3]   = { 0x90, 0xac, 0x4c };
+static const u8 int_type2_register_offset[3]   = { 0x94, 0xb0, 0x50 };
+static const u8 eoi_register_offset[3]         = { 0x98, 0xb4, 0x54 };
+static const u8 int_en_register_offset[3]      = { 0x9c, 0xb8, 0x58 };
+static const u8 int_debounce_register_offset[3]        = { 0xa8, 0xc4, 0x64 };
+
+void ep93xx_gpio_update_int_params(unsigned port)
+{
+       BUG_ON(port > 2);
+
+       __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
+
+       __raw_writeb(gpio_int_type2[port],
+               EP93XX_GPIO_REG(int_type2_register_offset[port]));
+
+       __raw_writeb(gpio_int_type1[port],
+               EP93XX_GPIO_REG(int_type1_register_offset[port]));
+
+       __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
+               EP93XX_GPIO_REG(int_en_register_offset[port]));
+}
+
+void ep93xx_gpio_int_mask(unsigned line)
+{
+       gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
+}
+
+void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
+{
+       int line = irq_to_gpio(irq);
+       int port = line >> 3;
+       int port_mask = 1 << (line & 7);
+
+       if (enable)
+               gpio_int_debounce[port] |= port_mask;
+       else
+               gpio_int_debounce[port] &= ~port_mask;
+
+       __raw_writeb(gpio_int_debounce[port],
+               EP93XX_GPIO_REG(int_debounce_register_offset[port]));
+}
+EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
+
+static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+       unsigned char status;
+       int i;
+
+       status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
+       for (i = 0; i < 8; i++) {
+               if (status & (1 << i)) {
+                       int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
+                       generic_handle_irq(gpio_irq);
+               }
+       }
+
+       status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
+       for (i = 0; i < 8; i++) {
+               if (status & (1 << i)) {
+                       int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
+                       generic_handle_irq(gpio_irq);
+               }
+       }
+}
+
+static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+       /*
+        * map discontiguous hw irq range to continous sw irq range:
+        *
+        *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
+        */
+       int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
+       int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
+
+       generic_handle_irq(gpio_irq);
+}
+
+static void ep93xx_gpio_irq_ack(unsigned int irq)
+{
+       int line = irq_to_gpio(irq);
+       int port = line >> 3;
+       int port_mask = 1 << (line & 7);
+
+       if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+               gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+               ep93xx_gpio_update_int_params(port);
+       }
+
+       __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+
+static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
+{
+       int line = irq_to_gpio(irq);
+       int port = line >> 3;
+       int port_mask = 1 << (line & 7);
+
+       if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+               gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+
+       gpio_int_unmasked[port] &= ~port_mask;
+       ep93xx_gpio_update_int_params(port);
+
+       __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+
+static void ep93xx_gpio_irq_mask(unsigned int irq)
+{
+       int line = irq_to_gpio(irq);
+       int port = line >> 3;
+
+       gpio_int_unmasked[port] &= ~(1 << (line & 7));
+       ep93xx_gpio_update_int_params(port);
+}
+
+static void ep93xx_gpio_irq_unmask(unsigned int irq)
+{
+       int line = irq_to_gpio(irq);
+       int port = line >> 3;
+
+       gpio_int_unmasked[port] |= 1 << (line & 7);
+       ep93xx_gpio_update_int_params(port);
+}
+
+/*
+ * gpio_int_type1 controls whether the interrupt is level (0) or
+ * edge (1) triggered, while gpio_int_type2 controls whether it
+ * triggers on low/falling (0) or high/rising (1).
+ */
+static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+       struct irq_desc *desc = irq_desc + irq;
+       const int gpio = irq_to_gpio(irq);
+       const int port = gpio >> 3;
+       const int port_mask = 1 << (gpio & 7);
+
+       gpio_direction_input(gpio);
+
+       switch (type) {
+       case IRQ_TYPE_EDGE_RISING:
+               gpio_int_type1[port] |= port_mask;
+               gpio_int_type2[port] |= port_mask;
+               desc->handle_irq = handle_edge_irq;
+               break;
+       case IRQ_TYPE_EDGE_FALLING:
+               gpio_int_type1[port] |= port_mask;
+               gpio_int_type2[port] &= ~port_mask;
+               desc->handle_irq = handle_edge_irq;
+               break;
+       case IRQ_TYPE_LEVEL_HIGH:
+               gpio_int_type1[port] &= ~port_mask;
+               gpio_int_type2[port] |= port_mask;
+               desc->handle_irq = handle_level_irq;
+               break;
+       case IRQ_TYPE_LEVEL_LOW:
+               gpio_int_type1[port] &= ~port_mask;
+               gpio_int_type2[port] &= ~port_mask;
+               desc->handle_irq = handle_level_irq;
+               break;
+       case IRQ_TYPE_EDGE_BOTH:
+               gpio_int_type1[port] |= port_mask;
+               /* set initial polarity based on current input level */
+               if (gpio_get_value(gpio))
+                       gpio_int_type2[port] &= ~port_mask; /* falling */
+               else
+                       gpio_int_type2[port] |= port_mask; /* rising */
+               desc->handle_irq = handle_edge_irq;
+               break;
+       default:
+               pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
+               return -EINVAL;
+       }
+
+       gpio_int_enabled[port] |= port_mask;
+
+       desc->status &= ~IRQ_TYPE_SENSE_MASK;
+       desc->status |= type & IRQ_TYPE_SENSE_MASK;
+
+       ep93xx_gpio_update_int_params(port);
+
+       return 0;
+}
+
+static struct irq_chip ep93xx_gpio_irq_chip = {
+       .name           = "GPIO",
+       .ack            = ep93xx_gpio_irq_ack,
+       .mask_ack       = ep93xx_gpio_irq_mask_ack,
+       .mask           = ep93xx_gpio_irq_mask,
+       .unmask         = ep93xx_gpio_irq_unmask,
+       .set_type       = ep93xx_gpio_irq_type,
+};
+
+void __init ep93xx_gpio_init_irq(void)
+{
+       int gpio_irq;
+
+       for (gpio_irq = gpio_to_irq(0);
+            gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
+               set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
+               set_irq_handler(gpio_irq, handle_level_irq);
+               set_irq_flags(gpio_irq, IRQF_VALID);
+       }
+
+       set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
+       set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+}
+
+
+/*************************************************************************
+ * gpiolib interface for EP93xx on-chip GPIOs
+ *************************************************************************/
 struct ep93xx_gpio_chip {
        struct gpio_chip        chip;
 
@@ -31,10 +262,6 @@ struct ep93xx_gpio_chip {
 
 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
 
-/* From core.c */
-extern void ep93xx_gpio_int_mask(unsigned line);
-extern void ep93xx_gpio_update_int_params(unsigned port);
-
 static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
index d55194a4c0934391cb096027969a08791e37cadf..93e2ecc79ceb14896e2665acc97a15eac0fd162d 100644 (file)
 
 /* APB peripherals */
 #define EP93XX_TIMER_BASE              EP93XX_APB_IOMEM(0x00010000)
-#define EP93XX_TIMER_REG(x)            (EP93XX_TIMER_BASE + (x))
-#define EP93XX_TIMER1_LOAD             EP93XX_TIMER_REG(0x00)
-#define EP93XX_TIMER1_VALUE            EP93XX_TIMER_REG(0x04)
-#define EP93XX_TIMER1_CONTROL          EP93XX_TIMER_REG(0x08)
-#define EP93XX_TIMER1_CLEAR            EP93XX_TIMER_REG(0x0c)
-#define EP93XX_TIMER2_LOAD             EP93XX_TIMER_REG(0x20)
-#define EP93XX_TIMER2_VALUE            EP93XX_TIMER_REG(0x24)
-#define EP93XX_TIMER2_CONTROL          EP93XX_TIMER_REG(0x28)
-#define EP93XX_TIMER2_CLEAR            EP93XX_TIMER_REG(0x2c)
-#define EP93XX_TIMER4_VALUE_LOW                EP93XX_TIMER_REG(0x60)
-#define EP93XX_TIMER4_VALUE_HIGH       EP93XX_TIMER_REG(0x64)
-#define EP93XX_TIMER3_LOAD             EP93XX_TIMER_REG(0x80)
-#define EP93XX_TIMER3_VALUE            EP93XX_TIMER_REG(0x84)
-#define EP93XX_TIMER3_CONTROL          EP93XX_TIMER_REG(0x88)
-#define EP93XX_TIMER3_CLEAR            EP93XX_TIMER_REG(0x8c)
 
 #define EP93XX_I2S_BASE                        EP93XX_APB_IOMEM(0x00020000)
 
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1  (1<<16)
 #define EP93XX_SYSCON_HALT             EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY          EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1       EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2       EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1          EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1    (1<<23)
+#define EP93XX_SYSCON_CLKSET2          EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2    (1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN  (1<<18)
 #define EP93XX_SYSCON_DEVCFG           EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST     (1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG     (1<<30)
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
new file mode 100644 (file)
index 0000000..cd93990
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/mach-ep93xx/simone.c
+ * Simplemachines Sim.One support.
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * Based on the 2.6.24.7 support:
+ *   Copyright (C) 2009 Simplemachines
+ *   MMC support by Peter Ivanov <ivanovp@gmail.com>, 2007
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/fb.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct physmap_flash_data simone_flash_data = {
+       .width          = 2,
+};
+
+static struct resource simone_flash_resource = {
+       .start          = EP93XX_CS6_PHYS_BASE,
+       .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
+       .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device simone_flash = {
+       .name           = "physmap-flash",
+       .id             = 0,
+       .num_resources  = 1,
+       .resource       = &simone_flash_resource,
+       .dev = {
+               .platform_data  = &simone_flash_data,
+       },
+};
+
+static struct ep93xx_eth_data simone_eth_data = {
+       .phy_id         = 1,
+};
+
+static struct ep93xxfb_mach_info simone_fb_info = {
+       .num_modes      = EP93XXFB_USE_MODEDB,
+       .bpp            = 16,
+       .flags          = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
+};
+
+static struct i2c_gpio_platform_data simone_i2c_gpio_data = {
+       .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+       .sda_is_open_drain      = 0,
+       .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+       .scl_is_open_drain      = 0,
+       .udelay                 = 0,
+       .timeout                = 0,
+};
+
+static struct i2c_board_info __initdata simone_i2c_board_info[] = {
+       {
+               I2C_BOARD_INFO("ds1337", 0x68),
+       },
+};
+
+static void __init simone_init_machine(void)
+{
+       ep93xx_init_devices();
+
+       platform_device_register(&simone_flash);
+       ep93xx_register_eth(&simone_eth_data, 1);
+       ep93xx_register_fb(&simone_fb_info);
+       ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
+                           ARRAY_SIZE(simone_i2c_board_info));
+}
+
+MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
+/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+       .phys_io        = EP93XX_APB_PHYS_BASE,
+       .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+       .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+       .map_io         = ep93xx_map_io,
+       .init_irq       = ep93xx_init_irq,
+       .timer          = &ep93xx_timer,
+       .init_machine   = simone_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
new file mode 100644 (file)
index 0000000..51134b0
--- /dev/null
@@ -0,0 +1,172 @@
+/*
+ * arch/arm/mach-ep93xx/snappercl15.c
+ * Bluewater Systems Snapper CL15 system module
+ *
+ * Copyright (C) 2009 Bluewater Systems Ltd
+ * Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * NAND code adapted from driver by:
+ *   Andre Renaud <andre@bluewatersys.com>
+ *   James R. McKaskill
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/fb.h>
+
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+
+#include <mach/hardware.h>
+#include <mach/fb.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#define SNAPPERCL15_NAND_BASE  (EP93XX_CS7_PHYS_BASE + SZ_16M)
+
+#define SNAPPERCL15_NAND_WPN   (1 << 8)  /* Write protect (active low) */
+#define SNAPPERCL15_NAND_ALE   (1 << 9)  /* Address latch */
+#define SNAPPERCL15_NAND_CLE   (1 << 10) /* Command latch */
+#define SNAPPERCL15_NAND_CEN   (1 << 11) /* Chip enable (active low) */
+#define SNAPPERCL15_NAND_RDY   (1 << 14) /* Device ready */
+
+#define NAND_CTRL_ADDR(chip)   (chip->IO_ADDR_W + 0x40)
+
+static void snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                     unsigned int ctrl)
+{
+       struct nand_chip *chip = mtd->priv;
+       static u16 nand_state = SNAPPERCL15_NAND_WPN;
+       u16 set;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN;
+
+               if (ctrl & NAND_NCE)
+                       set &= ~SNAPPERCL15_NAND_CEN;
+               if (ctrl & NAND_CLE)
+                       set |= SNAPPERCL15_NAND_CLE;
+               if (ctrl & NAND_ALE)
+                       set |= SNAPPERCL15_NAND_ALE;
+
+               nand_state &= ~(SNAPPERCL15_NAND_CEN |
+                               SNAPPERCL15_NAND_CLE |
+                               SNAPPERCL15_NAND_ALE);
+               nand_state |= set;
+               __raw_writew(nand_state, NAND_CTRL_ADDR(chip));
+       }
+
+       if (cmd != NAND_CMD_NONE)
+               __raw_writew((cmd & 0xff) | nand_state, chip->IO_ADDR_W);
+}
+
+static int snappercl15_nand_dev_ready(struct mtd_info *mtd)
+{
+       struct nand_chip *chip = mtd->priv;
+
+       return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
+}
+
+static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL};
+
+static struct mtd_partition snappercl15_nand_parts[] = {
+       {
+               .name           = "Kernel",
+               .offset         = 0,
+               .size           = SZ_2M,
+       },
+       {
+               .name           = "Filesystem",
+               .offset         = MTDPART_OFS_APPEND,
+               .size           = MTDPART_SIZ_FULL,
+       },
+};
+
+static struct platform_nand_data snappercl15_nand_data = {
+       .chip = {
+               .nr_chips               = 1,
+               .part_probe_types       = snappercl15_nand_part_probes,
+               .partitions             = snappercl15_nand_parts,
+               .nr_partitions          = ARRAY_SIZE(snappercl15_nand_parts),
+               .options                = NAND_NO_AUTOINCR,
+               .chip_delay             = 25,
+       },
+       .ctrl = {
+               .dev_ready              = snappercl15_nand_dev_ready,
+               .cmd_ctrl               = snappercl15_nand_cmd_ctrl,
+       },
+};
+
+static struct resource snappercl15_nand_resource[] = {
+       {
+               .start          = SNAPPERCL15_NAND_BASE,
+               .end            = SNAPPERCL15_NAND_BASE + SZ_4K - 1,
+               .flags          = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device snappercl15_nand_device = {
+       .name                   = "gen_nand",
+       .id                     = -1,
+       .dev.platform_data      = &snappercl15_nand_data,
+       .resource               = snappercl15_nand_resource,
+       .num_resources          = ARRAY_SIZE(snappercl15_nand_resource),
+};
+
+static struct ep93xx_eth_data snappercl15_eth_data = {
+       .phy_id                 = 1,
+};
+
+static struct i2c_gpio_platform_data snappercl15_i2c_gpio_data = {
+       .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+       .sda_is_open_drain      = 0,
+       .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+       .scl_is_open_drain      = 0,
+       .udelay                 = 0,
+       .timeout                = 0,
+};
+
+static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
+       {
+               /* Audio codec */
+               I2C_BOARD_INFO("tlv320aic23", 0x1a),
+       },
+};
+
+static struct ep93xxfb_mach_info snappercl15_fb_info = {
+       .num_modes              = EP93XXFB_USE_MODEDB,
+       .bpp                    = 16,
+};
+
+static void __init snappercl15_init_machine(void)
+{
+       ep93xx_init_devices();
+       ep93xx_register_eth(&snappercl15_eth_data, 1);
+       ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data,
+                           ARRAY_SIZE(snappercl15_i2c_data));
+       ep93xx_register_fb(&snappercl15_fb_info);
+       platform_device_register(&snappercl15_nand_device);
+}
+
+MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
+       /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+       .phys_io        = EP93XX_APB_PHYS_BASE,
+       .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+       .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+       .map_io         = ep93xx_map_io,
+       .init_irq       = ep93xx_init_irq,
+       .timer          = &ep93xx_timer,
+       .init_machine   = snappercl15_init_machine,
+MACHINE_END
index 3bbf40f6d964b277a7a153fa6a93e694c73ff9da..71728d36d501887f35fdff0ed67dd6714e2f9a3b 100644 (file)
@@ -426,6 +426,17 @@ static void __init ixp4xx_clocksource_init(void)
        clocksource_register(&clocksource_ixp4xx);
 }
 
+/*
+ * sched_clock()
+ */
+unsigned long long sched_clock(void)
+{
+       cycle_t cyc = ixp4xx_get_cycles(NULL);
+       struct clocksource *cs = &clocksource_ixp4xx;
+
+       return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+}
+
 /*
  * clockevents
  */
diff --git a/arch/arm/mach-nuc93x/Kconfig b/arch/arm/mach-nuc93x/Kconfig
new file mode 100644 (file)
index 0000000..2bc40a2
--- /dev/null
@@ -0,0 +1,19 @@
+if ARCH_NUC93X
+
+config CPU_NUC932
+       bool
+       help
+         Support for NUC932 of Nuvoton NUC93X CPUs.
+
+menu "NUC932 Machines"
+
+config MACH_NUC932EVB
+       bool "Nuvoton NUC932 Evaluation Board"
+       default y
+       select CPU_NUC932
+       help
+          Say Y here if you are using the Nuvoton NUC932EVB
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-nuc93x/Makefile b/arch/arm/mach-nuc93x/Makefile
new file mode 100644 (file)
index 0000000..440e2de
--- /dev/null
@@ -0,0 +1,14 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y                          := irq.o time.o dev.o cpu.o clock.o
+# NUC932 CPU support files
+
+obj-$(CONFIG_CPU_NUC932)       += nuc932.o
+
+# machine support
+
+obj-$(CONFIG_MACH_NUC932EVB)   += mach-nuc932evb.o
diff --git a/arch/arm/mach-nuc93x/Makefile.boot b/arch/arm/mach-nuc93x/Makefile.boot
new file mode 100644 (file)
index 0000000..a057b54
--- /dev/null
@@ -0,0 +1,3 @@
+zreladdr-y     := 0x00008000
+params_phys-y  := 0x00000100
+
diff --git a/arch/arm/mach-nuc93x/clock.c b/arch/arm/mach-nuc93x/clock.c
new file mode 100644 (file)
index 0000000..0521efb
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * linux/arch/arm/mach-nuc93x/clock.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+
+#include "clock.h"
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+int clk_enable(struct clk *clk)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&clocks_lock, flags);
+       if (clk->enabled++ == 0)
+               (clk->enable)(clk, 1);
+       spin_unlock_irqrestore(&clocks_lock, flags);
+
+       return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+       unsigned long flags;
+
+       WARN_ON(clk->enabled == 0);
+
+       spin_lock_irqsave(&clocks_lock, flags);
+       if (--clk->enabled == 0)
+               (clk->enable)(clk, 0);
+       spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+       return 27000000;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void nuc93x_clk_enable(struct clk *clk, int enable)
+{
+       unsigned int clocks = clk->cken;
+       unsigned long clken;
+
+       clken = __raw_readl(NUC93X_VA_CLKPWR);
+
+       if (enable)
+               clken |= clocks;
+       else
+               clken &= ~clocks;
+
+       __raw_writel(clken, NUC93X_VA_CLKPWR);
+}
+
+void clks_register(struct clk_lookup *clks, size_t num)
+{
+       int i;
+
+       for (i = 0; i < num; i++)
+               clkdev_add(&clks[i]);
+}
diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h
new file mode 100644 (file)
index 0000000..18e51be
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ * linux/arch/arm/mach-nuc93x/clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <asm/clkdev.h>
+
+void nuc93x_clk_enable(struct clk *clk, int enable);
+void clks_register(struct clk_lookup *clks, size_t num);
+
+struct clk {
+       unsigned long           cken;
+       unsigned int            enabled;
+       void                    (*enable)(struct clk *, int enable);
+};
+
+#define DEFINE_CLK(_name, _ctrlbit)                    \
+struct clk clk_##_name = {                             \
+               .enable = nuc93x_clk_enable,            \
+               .cken   = (1 << _ctrlbit),              \
+       }
+
+#define DEF_CLKLOOK(_clk, _devname, _conname)          \
+       {                                               \
+               .clk            = _clk,                 \
+               .dev_id         = _devname,             \
+               .con_id         = _conname,             \
+       }
+
diff --git a/arch/arm/mach-nuc93x/cpu.c b/arch/arm/mach-nuc93x/cpu.c
new file mode 100644 (file)
index 0000000..f6ff5d8
--- /dev/null
@@ -0,0 +1,135 @@
+/*
+ * linux/arch/arm/mach-nuc93x/cpu.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC93x series cpu common support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/serial_8250.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-ebi.h>
+
+#include "cpu.h"
+#include "clock.h"
+
+/* Initial IO mappings */
+
+static struct map_desc nuc93x_iodesc[] __initdata = {
+       IODESC_ENT(IRQ),
+       IODESC_ENT(GCR),
+       IODESC_ENT(UART),
+       IODESC_ENT(TIMER),
+       IODESC_ENT(EBI),
+};
+
+/* Initial nuc932 clock declarations. */
+static DEFINE_CLK(audio, 2);
+static DEFINE_CLK(sd, 3);
+static DEFINE_CLK(jpg, 4);
+static DEFINE_CLK(video, 5);
+static DEFINE_CLK(vpost, 6);
+static DEFINE_CLK(2d, 7);
+static DEFINE_CLK(gpu, 8);
+static DEFINE_CLK(gdma, 9);
+static DEFINE_CLK(adc, 10);
+static DEFINE_CLK(uart, 11);
+static DEFINE_CLK(spi, 12);
+static DEFINE_CLK(pwm, 13);
+static DEFINE_CLK(timer, 14);
+static DEFINE_CLK(wdt, 15);
+static DEFINE_CLK(ac97, 16);
+static DEFINE_CLK(i2s, 16);
+static DEFINE_CLK(usbck, 17);
+static DEFINE_CLK(usb48, 18);
+static DEFINE_CLK(usbh, 19);
+static DEFINE_CLK(i2c, 20);
+static DEFINE_CLK(ext, 0);
+
+static struct clk_lookup nuc932_clkregs[] = {
+       DEF_CLKLOOK(&clk_audio, "nuc932-audio", NULL),
+       DEF_CLKLOOK(&clk_sd, "nuc932-sd", NULL),
+       DEF_CLKLOOK(&clk_jpg, "nuc932-jpg", "NULL"),
+       DEF_CLKLOOK(&clk_video, "nuc932-video", "NULL"),
+       DEF_CLKLOOK(&clk_vpost, "nuc932-vpost", NULL),
+       DEF_CLKLOOK(&clk_2d, "nuc932-2d", NULL),
+       DEF_CLKLOOK(&clk_gpu, "nuc932-gpu", NULL),
+       DEF_CLKLOOK(&clk_gdma, "nuc932-gdma", "NULL"),
+       DEF_CLKLOOK(&clk_adc, "nuc932-adc", NULL),
+       DEF_CLKLOOK(&clk_uart, NULL, "uart"),
+       DEF_CLKLOOK(&clk_spi, "nuc932-spi", NULL),
+       DEF_CLKLOOK(&clk_pwm, "nuc932-pwm", NULL),
+       DEF_CLKLOOK(&clk_timer, NULL, "timer"),
+       DEF_CLKLOOK(&clk_wdt, "nuc932-wdt", NULL),
+       DEF_CLKLOOK(&clk_ac97, "nuc932-ac97", NULL),
+       DEF_CLKLOOK(&clk_i2s, "nuc932-i2s", NULL),
+       DEF_CLKLOOK(&clk_usbck, "nuc932-usbck", NULL),
+       DEF_CLKLOOK(&clk_usb48, "nuc932-usb48", NULL),
+       DEF_CLKLOOK(&clk_usbh, "nuc932-usbh", NULL),
+       DEF_CLKLOOK(&clk_i2c, "nuc932-i2c", NULL),
+       DEF_CLKLOOK(&clk_ext, NULL, "ext"),
+};
+
+/* Initial serial platform data */
+
+struct plat_serial8250_port nuc93x_uart_data[] = {
+       NUC93X_8250PORT(UART0),
+       {},
+};
+
+struct platform_device nuc93x_serial_device = {
+       .name                   = "serial8250",
+       .id                     = PLAT8250_DEV_PLATFORM,
+       .dev                    = {
+               .platform_data  = nuc93x_uart_data,
+       },
+};
+
+/*Init NUC93x evb io*/
+
+void __init nuc93x_map_io(struct map_desc *mach_desc, int mach_size)
+{
+       unsigned long idcode = 0x0;
+
+       iotable_init(mach_desc, mach_size);
+       iotable_init(nuc93x_iodesc, ARRAY_SIZE(nuc93x_iodesc));
+
+       idcode = __raw_readl(NUC93XPDID);
+       if (idcode == NUC932_CPUID)
+               printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
+       else
+               printk(KERN_ERR "CPU type detect error!\n");
+
+}
+
+/*Init NUC93x clock*/
+
+void __init nuc93x_init_clocks(void)
+{
+       clks_register(nuc932_clkregs, ARRAY_SIZE(nuc932_clkregs));
+}
+
diff --git a/arch/arm/mach-nuc93x/cpu.h b/arch/arm/mach-nuc93x/cpu.h
new file mode 100644 (file)
index 0000000..9def281
--- /dev/null
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-nuc93x/cpu.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Header file for NUC93X CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define IODESC_ENT(y)                                  \
+{                                                      \
+       .virtual = (unsigned long)NUC93X_VA_##y,        \
+       .pfn     = __phys_to_pfn(NUC93X_PA_##y),        \
+       .length  = NUC93X_SZ_##y,                       \
+       .type    = MT_DEVICE,                           \
+}
+
+#define NUC93X_8250PORT(name)                                  \
+{                                                              \
+       .membase        = name##_BA,                            \
+       .mapbase        = name##_PA,                            \
+       .irq            = IRQ_##name,                           \
+       .uartclk        = 57139200,                             \
+       .regshift       = 2,                                    \
+       .iotype         = UPIO_MEM,                             \
+       .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
+}
+
+/*Cpu identifier register*/
+
+#define NUC93XPDID     NUC93X_VA_GCR
+#define NUC932_CPUID   0x29550091
+
+/* extern file from cpu.c */
+
+extern void nuc93x_clock_source(struct device *dev, unsigned char *src);
+extern void nuc93x_init_clocks(void);
+extern void nuc93x_map_io(struct map_desc *mach_desc, int mach_size);
+extern void nuc93x_board_init(struct platform_device **device, int size);
+extern struct platform_device nuc93x_serial_device;
+
diff --git a/arch/arm/mach-nuc93x/dev.c b/arch/arm/mach-nuc93x/dev.c
new file mode 100644 (file)
index 0000000..a962ae9
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * linux/arch/arm/mach-nuc93x/dev.c
+ *
+ * Copyright (C) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+
+#include "cpu.h"
+
+/*Here should be your evb resourse,such as LCD*/
+
+static struct platform_device *nuc93x_public_dev[] __initdata = {
+       &nuc93x_serial_device,
+};
+
+/* Provide adding specific CPU platform devices API */
+
+void __init nuc93x_board_init(struct platform_device **device, int size)
+{
+       platform_add_devices(device, size);
+       platform_add_devices(nuc93x_public_dev, ARRAY_SIZE(nuc93x_public_dev));
+}
+
diff --git a/arch/arm/mach-nuc93x/include/mach/clkdev.h b/arch/arm/mach-nuc93x/include/mach/clkdev.h
new file mode 100644 (file)
index 0000000..04b37a8
--- /dev/null
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/entry-macro.S b/arch/arm/mach-nuc93x/include/mach/entry-macro.S
new file mode 100644 (file)
index 0000000..1352cbd
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/entry-macro.S
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ */
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+
+       .macro  get_irqnr_preamble, base, tmp
+       .endm
+
+       .macro  arch_ret_to_user, tmp1, tmp2
+       .endm
+
+       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+               mov     \base, #AIC_BA
+
+               ldr     \irqnr, [ \base, #AIC_IPER]
+               ldr     \irqnr, [ \base, #AIC_ISNR]
+               cmp     \irqnr, #0
+
+       .endm
+
+       /* currently don't need an disable_fiq macro */
+
+       .macro  disable_fiq
+       .endm
diff --git a/arch/arm/mach-nuc93x/include/mach/hardware.h b/arch/arm/mach-nuc93x/include/mach/hardware.h
new file mode 100644 (file)
index 0000000..fb5c6fc
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/hardware.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/map.h>
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h
new file mode 100644 (file)
index 0000000..72e5051
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/io.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+
+#define __mem_pci(a)   (a)
+#define __io(a)                __typesafe_io(a)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/irqs.h b/arch/arm/mach-nuc93x/include/mach/irqs.h
new file mode 100644 (file)
index 0000000..7c4aa71
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/irqs.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define NUC93X_IRQ(x)  (x)
+
+/* Main cpu interrupts */
+
+#define IRQ_WDT                NUC93X_IRQ(1)
+#define IRQ_IRQ0       NUC93X_IRQ(2)
+#define IRQ_IRQ1       NUC93X_IRQ(3)
+#define IRQ_IRQ2       NUC93X_IRQ(4)
+#define IRQ_IRQ3       NUC93X_IRQ(5)
+#define IRQ_USBH       NUC93X_IRQ(6)
+#define IRQ_APU                NUC93X_IRQ(7)
+#define IRQ_VPOST      NUC93X_IRQ(8)
+#define IRQ_ADC                NUC93X_IRQ(9)
+#define IRQ_UART0      NUC93X_IRQ(10)
+#define IRQ_TIMER0     NUC93X_IRQ(11)
+#define IRQ_GPU0       NUC93X_IRQ(12)
+#define IRQ_GPU1       NUC93X_IRQ(13)
+#define IRQ_GPU2       NUC93X_IRQ(14)
+#define IRQ_GPU3       NUC93X_IRQ(15)
+#define IRQ_GPU4       NUC93X_IRQ(16)
+#define IRQ_VIN                NUC93X_IRQ(17)
+#define IRQ_USBD       NUC93X_IRQ(18)
+#define IRQ_VRAMLD     NUC93X_IRQ(19)
+#define IRQ_GDMA0      NUC93X_IRQ(20)
+#define IRQ_GDMA1      NUC93X_IRQ(21)
+#define IRQ_SDIO       NUC93X_IRQ(22)
+#define IRQ_FMI                NUC93X_IRQ(22)
+#define IRQ_JPEG       NUC93X_IRQ(23)
+#define IRQ_SPI0       NUC93X_IRQ(24)
+#define IRQ_SPI1       NUC93X_IRQ(25)
+#define IRQ_RTC                NUC93X_IRQ(26)
+#define IRQ_PWM0       NUC93X_IRQ(27)
+#define IRQ_PWM1       NUC93X_IRQ(28)
+#define IRQ_PWM2       NUC93X_IRQ(29)
+#define IRQ_PWM3       NUC93X_IRQ(30)
+#define IRQ_I2SAC97    NUC93X_IRQ(31)
+#define IRQ_CAP0       IRQ_PWM0
+#define IRQ_CAP1       IRQ_PWM1
+#define IRQ_CAP2       IRQ_PWM2
+#define IRQ_CAP3       IRQ_PWM3
+#define NR_IRQS                (IRQ_I2SAC97 + 1)
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/map.h b/arch/arm/mach-nuc93x/include/mach/map.h
new file mode 100644 (file)
index 0000000..fd0b5e8
--- /dev/null
@@ -0,0 +1,139 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/map.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+#define MAP_OFFSET     (0xfff00000)
+#define CLK_OFFSET     (0x10)
+
+#ifndef __ASSEMBLY__
+#define NUC93X_ADDR(x) ((void __iomem *)(0xF0000000 + ((x)&(~MAP_OFFSET))))
+#else
+#define NUC93X_ADDR(x) (0xF0000000 + ((x)&(~MAP_OFFSET)))
+#endif
+
+ /*
+  * nuc932 hardware register definition
+  */
+
+#define NUC93X_PA_IRQ          (0xFFF83000)
+#define NUC93X_PA_GCR          (0xFFF00000)
+#define NUC93X_PA_EBI          (0xFFF01000)
+#define NUC93X_PA_UART         (0xFFF80000)
+#define NUC93X_PA_TIMER                (0xFFF81000)
+#define NUC93X_PA_GPIO         (0xFFF84000)
+#define NUC93X_PA_GDMA         (0xFFF03000)
+#define NUC93X_PA_USBHOST      (0xFFF0d000)
+#define NUC93X_PA_I2C          (0xFFF89000)
+#define NUC93X_PA_LCD          (0xFFF06000)
+#define NUC93X_PA_GE           (0xFFF05000)
+#define NUC93X_PA_ADC          (0xFFF85000)
+#define NUC93X_PA_RTC          (0xFFF87000)
+#define NUC93X_PA_PWM          (0xFFF82000)
+#define NUC93X_PA_ACTL         (0xFFF0a000)
+#define NUC93X_PA_USBDEV       (0xFFF0C000)
+#define NUC93X_PA_JEPEG                (0xFFF0e000)
+#define NUC93X_PA_CACHE_T      (0xFFF60000)
+#define NUC93X_PA_VRAM         (0xFFF0b000)
+#define NUC93X_PA_DMAC         (0xFFF09000)
+#define NUC93X_PA_I2SM         (0xFFF08000)
+#define NUC93X_PA_CACHE                (0xFFF02000)
+#define NUC93X_PA_GPU          (0xFFF04000)
+#define NUC93X_PA_VIDEOIN      (0xFFF07000)
+#define NUC93X_PA_SPI0         (0xFFF86000)
+#define NUC93X_PA_SPI1         (0xFFF88000)
+
+ /*
+  * nuc932 virtual address mapping.
+  * interrupt controller is the first thing we put in, to make
+  * the assembly code for the irq detection easier
+  */
+
+#define NUC93X_VA_IRQ          NUC93X_ADDR(0x00000000)
+#define NUC93X_SZ_IRQ          SZ_4K
+
+#define NUC93X_VA_GCR          NUC93X_ADDR(NUC93X_PA_IRQ)
+#define NUC93X_VA_CLKPWR       (NUC93X_VA_GCR+CLK_OFFSET)
+#define NUC93X_SZ_GCR          SZ_4K
+
+/* EBI management */
+
+#define NUC93X_VA_EBI          NUC93X_ADDR(NUC93X_PA_EBI)
+#define NUC93X_SZ_EBI          SZ_4K
+
+/* UARTs */
+
+#define NUC93X_VA_UART         NUC93X_ADDR(NUC93X_PA_UART)
+#define NUC93X_SZ_UART         SZ_4K
+
+/* Timers */
+
+#define NUC93X_VA_TIMER        NUC93X_ADDR(NUC93X_PA_TIMER)
+#define NUC93X_SZ_TIMER        SZ_4K
+
+/* GPIO ports */
+
+#define NUC93X_VA_GPIO         NUC93X_ADDR(NUC93X_PA_GPIO)
+#define NUC93X_SZ_GPIO         SZ_4K
+
+/* GDMA control */
+
+#define NUC93X_VA_GDMA         NUC93X_ADDR(NUC93X_PA_GDMA)
+#define NUC93X_SZ_GDMA         SZ_4K
+
+/* I2C hardware controller */
+
+#define NUC93X_VA_I2C          NUC93X_ADDR(NUC93X_PA_I2C)
+#define NUC93X_SZ_I2C          SZ_4K
+
+/* LCD controller*/
+
+#define NUC93X_VA_LCD          NUC93X_ADDR(NUC93X_PA_LCD)
+#define NUC93X_SZ_LCD          SZ_4K
+
+/* 2D controller*/
+
+#define NUC93X_VA_GE           NUC93X_ADDR(NUC93X_PA_GE)
+#define NUC93X_SZ_GE           SZ_4K
+
+/* ADC */
+
+#define NUC93X_VA_ADC          NUC93X_ADDR(NUC93X_PA_ADC)
+#define NUC93X_SZ_ADC          SZ_4K
+
+/* RTC */
+
+#define NUC93X_VA_RTC          NUC93X_ADDR(NUC93X_PA_RTC)
+#define NUC93X_SZ_RTC          SZ_4K
+
+/* Pulse Width Modulation(PWM) Registers */
+
+#define NUC93X_VA_PWM          NUC93X_ADDR(NUC93X_PA_PWM)
+#define NUC93X_SZ_PWM          SZ_4K
+
+/* Audio Controller controller */
+
+#define NUC93X_VA_ACTL         NUC93X_ADDR(NUC93X_PA_ACTL)
+#define NUC93X_SZ_ACTL         SZ_4K
+
+/* USB Device port */
+
+#define NUC93X_VA_USBDEV       NUC93X_ADDR(NUC93X_PA_USBDEV)
+#define NUC93X_SZ_USBDEV       SZ_4K
+
+/* USB host controller*/
+#define NUC93X_VA_USBHOST      NUC93X_ADDR(NUC93X_PA_USBHOST)
+#define NUC93X_SZ_USBHOST      SZ_4K
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h
new file mode 100644 (file)
index 0000000..323ab0d
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/memory.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET    UL(0x00000000)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-clock.h b/arch/arm/mach-nuc93x/include/mach/regs-clock.h
new file mode 100644 (file)
index 0000000..5cb2954
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H
+
+/* Clock Control Registers  */
+#define CLK_BA         NUC93X_VA_CLKPWR
+#define REG_CLKEN      (CLK_BA + 0x00)
+#define REG_CLKSEL     (CLK_BA + 0x04)
+#define REG_CLKDIV     (CLK_BA + 0x08)
+#define REG_PLLCON0    (CLK_BA + 0x0C)
+#define REG_PLLCON1    (CLK_BA + 0x10)
+#define REG_PMCON      (CLK_BA + 0x14)
+#define REG_IRQWAKECON (CLK_BA + 0x18)
+#define REG_IRQWAKEFLAG        (CLK_BA + 0x1C)
+#define REG_IPSRST     (CLK_BA + 0x20)
+#define REG_CLKEN1     (CLK_BA + 0x24)
+#define REG_CLKDIV1    (CLK_BA + 0x28)
+
+/* Define PLL freq setting */
+#define PLL_DISABLE            0x12B63
+#define        PLL_66MHZ               0x2B63
+#define        PLL_100MHZ              0x4F64
+#define PLL_120MHZ             0x4F63
+#define        PLL_166MHZ              0x4124
+#define        PLL_200MHZ              0x4F24
+
+/* Define AHB:CPUFREQ ratio */
+#define        AHB_CPUCLK_1_1          0x00
+#define        AHB_CPUCLK_1_2          0x01
+#define        AHB_CPUCLK_1_4          0x02
+#define        AHB_CPUCLK_1_8          0x03
+
+/* Define APB:AHB ratio */
+#define APB_AHB_1_2            0x01
+#define APB_AHB_1_4            0x02
+#define APB_AHB_1_8            0x03
+
+/* Define clock skew */
+#define DEFAULTSKEW            0x48
+
+#endif /*  __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h
new file mode 100644 (file)
index 0000000..3c72550
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-ebi.h
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_EBI_H
+#define __ASM_ARCH_REGS_EBI_H
+
+/* EBI Control Registers */
+
+#define EBI_BA         NUC93X_VA_EBI
+#define REG_EBICON     (EBI_BA + 0x00)
+#define REG_ROMCON     (EBI_BA + 0x04)
+#define REG_SDCONF0    (EBI_BA + 0x08)
+#define REG_SDCONF1    (EBI_BA + 0x0C)
+#define REG_SDTIME0    (EBI_BA + 0x10)
+#define REG_SDTIME1    (EBI_BA + 0x14)
+#define REG_EXT0CON    (EBI_BA + 0x18)
+#define REG_EXT1CON    (EBI_BA + 0x1C)
+#define REG_EXT2CON    (EBI_BA + 0x20)
+#define REG_EXT3CON    (EBI_BA + 0x24)
+#define REG_EXT4CON    (EBI_BA + 0x28)
+#define REG_CKSKEW     (EBI_BA + 0x2C)
+
+#endif /*  __ASM_ARCH_REGS_EBI_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-irq.h b/arch/arm/mach-nuc93x/include/mach/regs-irq.h
new file mode 100644 (file)
index 0000000..2302159
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef ___ASM_ARCH_REGS_IRQ_H
+#define ___ASM_ARCH_REGS_IRQ_H
+
+/* Advance Interrupt Controller (AIC) Registers */
+
+#define AIC_BA                 NUC93X_VA_IRQ
+
+#define REG_AIC_IRQSC          (AIC_BA+0x80)
+#define REG_AIC_GEN            (AIC_BA+0x84)
+#define REG_AIC_GASR           (AIC_BA+0x88)
+#define REG_AIC_GSCR           (AIC_BA+0x8C)
+#define REG_AIC_IRSR           (AIC_BA+0x100)
+#define REG_AIC_IASR           (AIC_BA+0x104)
+#define REG_AIC_ISR            (AIC_BA+0x108)
+#define REG_AIC_IPER           (AIC_BA+0x10C)
+#define REG_AIC_ISNR           (AIC_BA+0x110)
+#define REG_AIC_IMR            (AIC_BA+0x114)
+#define REG_AIC_OISR           (AIC_BA+0x118)
+#define REG_AIC_MECR           (AIC_BA+0x120)
+#define REG_AIC_MDCR           (AIC_BA+0x124)
+#define REG_AIC_SSCR           (AIC_BA+0x128)
+#define REG_AIC_SCCR           (AIC_BA+0x12C)
+#define REG_AIC_EOSCR          (AIC_BA+0x130)
+#define AIC_IPER               (0x10C)
+#define AIC_ISNR               (0x110)
+
+#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-serial.h b/arch/arm/mach-nuc93x/include/mach/regs-serial.h
new file mode 100644 (file)
index 0000000..767a047
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-serial.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARM_REGS_SERIAL_H
+#define __ASM_ARM_REGS_SERIAL_H
+
+#define UART0_BA       NUC93X_VA_UART
+#define UART1_BA       (NUC93X_VA_UART+0x100)
+
+#define UART0_PA       NUC93X_PA_UART
+#define UART1_PA       (NUC93X_PA_UART+0x100)
+
+
+#ifndef __ASSEMBLY__
+
+struct nuc93x_uart_clksrc {
+       const char      *name;
+       unsigned int    divisor;
+       unsigned int    min_baud;
+       unsigned int    max_baud;
+};
+
+struct nuc93x_uartcfg {
+       unsigned char   hwport;
+       unsigned char   unused;
+       unsigned short  flags;
+       unsigned long   uart_flags;
+
+       unsigned long   ucon;
+       unsigned long   ulcon;
+       unsigned long   ufcon;
+
+       struct nuc93x_uart_clksrc *clocks;
+       unsigned int    clocks_size;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_REGS_SERIAL_H */
+
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-timer.h b/arch/arm/mach-nuc93x/include/mach/regs-timer.h
new file mode 100644 (file)
index 0000000..394be96
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-timer.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H
+
+/* Timer Registers */
+
+#define TMR_BA                 NUC93X_VA_TIMER
+#define REG_TCSR0              (TMR_BA+0x00)
+#define REG_TICR0              (TMR_BA+0x08)
+#define REG_TDR0               (TMR_BA+0x10)
+#define REG_TISR               (TMR_BA+0x18)
+#define REG_WTCR               (TMR_BA+0x1C)
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/system.h b/arch/arm/mach-nuc93x/include/mach/system.h
new file mode 100644 (file)
index 0000000..d26bd9a
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/machnuc93x/include/mach/system.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/system.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <asm/proc-fns.h>
+
+static void arch_idle(void)
+{
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+       cpu_reset(0);
+}
+
diff --git a/arch/arm/mach-nuc93x/include/mach/timex.h b/arch/arm/mach-nuc93x/include/mach/timex.h
new file mode 100644 (file)
index 0000000..0c719cc
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/timex.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/timex.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE Now, I don't use it. */
+
+#define CLOCK_TICK_RATE 27000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
new file mode 100644 (file)
index 0000000..73082cd
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/uncompress.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+/* Defines for UART registers */
+
+#include <mach/regs-serial.h>
+#include <mach/map.h>
+#include <linux/serial_reg.h>
+
+#define arch_decomp_wdog()
+
+#define TX_DONE        (UART_LSR_TEMT | UART_LSR_THRE)
+static u32 * uart_base = (u32 *)UART0_PA;
+
+static void putc(int ch)
+{
+       /* Check THRE and TEMT bits before we transmit the character.
+        */
+       while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+               barrier();
+
+       *uart_base = ch;
+}
+
+static inline void flush(void)
+{
+}
+
+static void arch_decomp_setup(void)
+{
+}
+
+#endif/* __ASM_NUC93X_UNCOMPRESS_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/vmalloc.h b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
new file mode 100644 (file)
index 0000000..98a21b8
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END      (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
new file mode 100644 (file)
index 0000000..a7a88ea
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * linux/arch/arm/mach-nuc93x/irq.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+
+static void nuc93x_irq_mask(unsigned int irq)
+{
+       __raw_writel(1 << irq, REG_AIC_MDCR);
+}
+
+/*
+ * By the w90p910 spec,any irq,only write 1
+ * to REG_AIC_EOSCR for ACK
+ */
+
+static void nuc93x_irq_ack(unsigned int irq)
+{
+       __raw_writel(0x01, REG_AIC_EOSCR);
+}
+
+static void nuc93x_irq_unmask(unsigned int irq)
+{
+       __raw_writel(1 << irq, REG_AIC_MECR);
+
+}
+
+static struct irq_chip nuc93x_irq_chip = {
+       .ack       = nuc93x_irq_ack,
+       .mask      = nuc93x_irq_mask,
+       .unmask    = nuc93x_irq_unmask,
+};
+
+void __init nuc93x_init_irq(void)
+{
+       int irqno;
+
+       __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
+
+       for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
+               set_irq_chip(irqno, &nuc93x_irq_chip);
+               set_irq_handler(irqno, handle_level_irq);
+               set_irq_flags(irqno, IRQF_VALID);
+       }
+}
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
new file mode 100644 (file)
index 0000000..9f79266
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc910evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+
+#include "nuc932.h"
+
+static void __init nuc932evb_map_io(void)
+{
+       nuc932_map_io();
+       nuc932_init_clocks();
+       nuc932_init_uartclk();
+}
+
+static void __init nuc932evb_init(void)
+{
+       nuc932_board_init();
+}
+
+MACHINE_START(NUC932EVB, "NUC932EVB")
+       /* Maintainer: Wan ZongShun */
+       .phys_io        = NUC93X_PA_UART,
+       .io_pg_offst    = (((u32)NUC93X_VA_UART) >> 18) & 0xfffc,
+       .boot_params    = 0,
+       .map_io         = nuc932evb_map_io,
+       .init_irq       = nuc93x_init_irq,
+       .init_machine   = nuc932evb_init,
+       .timer          = &nuc93x_timer,
+MACHINE_END
diff --git a/arch/arm/mach-nuc93x/nuc932.c b/arch/arm/mach-nuc93x/nuc932.c
new file mode 100644 (file)
index 0000000..3966ead
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * linux/arch/arm/mach-nuc93x/nuc932.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC932 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+
+#include "cpu.h"
+#include "clock.h"
+
+/* define specific CPU platform device */
+
+static struct platform_device *nuc932_dev[] __initdata = {
+};
+
+/* define specific CPU platform io map */
+
+static struct map_desc nuc932evb_iodesc[] __initdata = {
+};
+
+/*Init NUC932 evb io*/
+
+void __init nuc932_map_io(void)
+{
+       nuc93x_map_io(nuc932evb_iodesc, ARRAY_SIZE(nuc932evb_iodesc));
+}
+
+/*Init NUC932 clock*/
+
+void __init nuc932_init_clocks(void)
+{
+       nuc93x_init_clocks();
+}
+
+/*enable NUC932 uart clock*/
+
+void __init nuc932_init_uartclk(void)
+{
+       struct clk *ck_uart = clk_get(NULL, "uart");
+       BUG_ON(IS_ERR(ck_uart));
+
+       clk_enable(ck_uart);
+}
+
+/*Init NUC932 board info*/
+
+void __init nuc932_board_init(void)
+{
+       nuc93x_board_init(nuc932_dev, ARRAY_SIZE(nuc932_dev));
+}
diff --git a/arch/arm/mach-nuc93x/nuc932.h b/arch/arm/mach-nuc93x/nuc932.h
new file mode 100644 (file)
index 0000000..9a66edd
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-nuc93x/nuc932.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC93x CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+struct map_desc;
+struct sys_timer;
+
+/* core initialisation functions */
+
+extern void nuc93x_init_irq(void);
+extern struct sys_timer nuc93x_timer;
+
+/* extern file from nuc932.c */
+
+extern void nuc932_board_init(void);
+extern void nuc932_init_clocks(void);
+extern void nuc932_map_io(void);
+extern void nuc932_init_uartclk(void);
diff --git a/arch/arm/mach-nuc93x/time.c b/arch/arm/mach-nuc93x/time.c
new file mode 100644 (file)
index 0000000..2f90f9d
--- /dev/null
@@ -0,0 +1,100 @@
+/*
+ * linux/arch/arm/mach-nuc93x/time.c
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+#include <mach/system.h>
+#include <mach/map.h>
+#include <mach/regs-timer.h>
+
+#define RESETINT       0x01
+#define PERIOD         (0x01 << 27)
+#define ONESHOT                (0x00 << 27)
+#define COUNTEN                (0x01 << 30)
+#define INTEN          (0x01 << 29)
+
+#define TICKS_PER_SEC  100
+#define PRESCALE       0x63 /* Divider = prescale + 1 */
+
+unsigned int timer0_load;
+
+static unsigned long nuc93x_gettimeoffset(void)
+{
+       return 0;
+}
+
+/*IRQ handler for the timer*/
+
+static irqreturn_t nuc93x_timer_interrupt(int irq, void *dev_id)
+{
+       timer_tick();
+       __raw_writel(0x01, REG_TISR); /* clear TIF0 */
+       return IRQ_HANDLED;
+}
+
+static struct irqaction nuc93x_timer_irq = {
+       .name           = "nuc93x Timer Tick",
+       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+       .handler        = nuc93x_timer_interrupt,
+};
+
+/*Set up timer reg.*/
+
+static void nuc93x_timer_setup(void)
+{
+       struct clk *ck_ext = clk_get(NULL, "ext");
+       struct clk *ck_timer = clk_get(NULL, "timer");
+       unsigned int rate, val = 0;
+
+       BUG_ON(IS_ERR(ck_ext) || IS_ERR(ck_timer));
+
+       clk_enable(ck_timer);
+       rate = clk_get_rate(ck_ext);
+       clk_put(ck_ext);
+       rate = rate / (PRESCALE + 0x01);
+
+        /* set a known state */
+       __raw_writel(0x00, REG_TCSR0);
+       __raw_writel(RESETINT, REG_TISR);
+
+       timer0_load = (rate / TICKS_PER_SEC);
+       __raw_writel(timer0_load, REG_TICR0);
+
+       val |= (PERIOD | COUNTEN | INTEN | PRESCALE);;
+       __raw_writel(val, REG_TCSR0);
+
+}
+
+static void __init nuc93x_timer_init(void)
+{
+       nuc93x_timer_setup();
+       setup_irq(IRQ_TIMER0, &nuc93x_timer_irq);
+}
+
+struct sys_timer nuc93x_timer = {
+       .init           = nuc93x_timer_init,
+       .offset         = nuc93x_gettimeoffset,
+       .resume         = nuc93x_timer_setup
+};
index 111f7ea32b384bd6e492d1cb1c0cf9635632c035..36ffd6a8b34cc8d6a173a7f5f92d5b54862c3141 100644 (file)
@@ -610,34 +610,34 @@ EXPORT_SYMBOL(clk_get_rate);
 
 static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
 {
-       if (rate >= 18900000)
+       if (rate <= 18900000)
                return 18900000;
-       if (rate >= 20800000)
+       if (rate <= 20800000)
                return 20800000;
-       if (rate >= 23100000)
+       if (rate <= 23100000)
                return 23100000;
-       if (rate >= 26000000)
+       if (rate <= 26000000)
                return 26000000;
-       if (rate >= 29700000)
+       if (rate <= 29700000)
                return 29700000;
-       if (rate >= 34700000)
+       if (rate <= 34700000)
                return 34700000;
-       if (rate >= 41600000)
+       if (rate <= 41600000)
                return 41600000;
-       if (rate >= 52000000)
+       if (rate <= 52000000)
                return 52000000;
        return -EINVAL;
 }
 
 static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
 {
-       if (rate >= 13000000)
+       if (rate <= 13000000)
                return 13000000;
-       if (rate >= 52000000)
+       if (rate <= 52000000)
                return 52000000;
-       if (rate >= 104000000)
+       if (rate <= 104000000)
                return 104000000;
-       if (rate >= 208000000)
+       if (rate <= 208000000)
                return 208000000;
        return -EINVAL;
 }
index 653e25be3dd82df532b4b3a508fb45e393b00876..01b50313914cf99fd8738d288495eb18bc2919c9 100644 (file)
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2009 ST-Ericsson AB
+ * Copyright (C) 2007-2010 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -19,6 +19,7 @@
 #include <linux/amba/bus.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <mach/coh901318.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -29,6 +30,7 @@
 
 #include <mach/hardware.h>
 #include <mach/syscon.h>
+#include <mach/dma_channels.h>
 
 #include "clock.h"
 #include "mmc.h"
@@ -372,8 +374,1019 @@ static struct resource ave_resources[] = {
        },
 };
 
+static struct resource dma_resource[] = {
+       {
+               .start = U300_DMAC_BASE,
+               .end = U300_DMAC_BASE + PAGE_SIZE - 1,
+               .flags =  IORESOURCE_MEM,
+       },
+       {
+               .start = IRQ_U300_DMA,
+               .end = IRQ_U300_DMA,
+               .flags =  IORESOURCE_IRQ,
+       }
+};
+
+#ifdef CONFIG_MACH_U300_BS335
+/* points out all dma slave channels.
+ * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
+ * Select all channels from A to B, end of list is marked with -1,-1
+ */
+static int dma_slave_channels[] = {
+       U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
+       U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
+
+/* points out all dma memcpy channels. */
+static int dma_memcpy_channels[] = {
+       U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
+
+#else /* CONFIG_MACH_U300_BS335 */
+
+static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
+static int dma_memcpy_channels[] = {
+       U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
+
+#endif
+
+/** register dma for memory access
+ *
+ * active  1 means dma intends to access memory
+ *         0 means dma wont access memory
+ */
+static void coh901318_access_memory_state(struct device *dev, bool active)
+{
+}
+
+#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
+                       COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
+                       COH901318_CX_CFG_LCR_DISABLE | \
+                       COH901318_CX_CFG_TC_IRQ_ENABLE | \
+                       COH901318_CX_CFG_BE_IRQ_ENABLE)
+#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
+                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                       COH901318_CX_CTRL_TCP_DISABLE | \
+                       COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                       COH901318_CX_CTRL_HSP_DISABLE | \
+                       COH901318_CX_CTRL_HSS_DISABLE | \
+                       COH901318_CX_CTRL_DDMA_LEGACY | \
+                       COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
+                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                       COH901318_CX_CTRL_TCP_DISABLE | \
+                       COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                       COH901318_CX_CTRL_HSP_DISABLE | \
+                       COH901318_CX_CTRL_HSS_DISABLE | \
+                       COH901318_CX_CTRL_DDMA_LEGACY | \
+                       COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
+                       COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                       COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                       COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                       COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                       COH901318_CX_CTRL_TCP_DISABLE | \
+                       COH901318_CX_CTRL_TC_IRQ_ENABLE | \
+                       COH901318_CX_CTRL_HSP_DISABLE | \
+                       COH901318_CX_CTRL_HSS_DISABLE | \
+                       COH901318_CX_CTRL_DDMA_LEGACY | \
+                       COH901318_CX_CTRL_PRDD_SOURCE)
+
+const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
+       {
+               .number = U300_DMA_MSL_TX_0,
+               .name = "MSL TX 0",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
+       },
+       {
+               .number = U300_DMA_MSL_TX_1,
+               .name = "MSL TX 1",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_MSL_TX_2,
+               .name = "MSL TX 2",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .desc_nbr_max = 10,
+       },
+       {
+               .number = U300_DMA_MSL_TX_3,
+               .name = "MSL TX 3",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_MSL_TX_4,
+               .name = "MSL TX 4",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_MSL_TX_5,
+               .name = "MSL TX 5",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
+       },
+       {
+               .number = U300_DMA_MSL_TX_6,
+               .name = "MSL TX 6",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
+       },
+       {
+               .number = U300_DMA_MSL_RX_0,
+               .name = "MSL RX 0",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
+       },
+       {
+               .number = U300_DMA_MSL_RX_1,
+               .name = "MSL RX 1",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_2,
+               .name = "MSL RX 2",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_3,
+               .name = "MSL RX 3",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_4,
+               .name = "MSL RX 4",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_5,
+               .name = "MSL RX 5",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_MSL_RX_6,
+               .name = "MSL RX 6",
+               .priority_high = 0,
+               .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
+       },
+       {
+               .number = U300_DMA_MMCSD_RX_TX,
+               .name = "MMCSD RX TX",
+               .priority_high = 0,
+               .dev_addr =  U300_MMCSD_BASE + 0x080,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY,
+
+       },
+       {
+               .number = U300_DMA_MSPRO_TX,
+               .name = "MSPRO TX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_MSPRO_RX,
+               .name = "MSPRO RX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_UART0_TX,
+               .name = "UART0 TX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_UART0_RX,
+               .name = "UART0 RX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_APEX_TX,
+               .name = "APEX TX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_APEX_RX,
+               .name = "APEX RX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_PCM_I2S0_TX,
+               .name = "PCM I2S0 TX",
+               .priority_high = 1,
+               .dev_addr = U300_PCM_I2S0_BASE + 0x14,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_PCM_I2S0_RX,
+               .name = "PCM I2S0 RX",
+               .priority_high = 1,
+               .dev_addr = U300_PCM_I2S0_BASE + 0x10,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_PCM_I2S1_TX,
+               .name = "PCM I2S1 TX",
+               .priority_high = 1,
+               .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_SOURCE,
+       },
+       {
+               .number = U300_DMA_PCM_I2S1_RX,
+               .name = "PCM I2S1 RX",
+               .priority_high = 1,
+               .dev_addr = U300_PCM_I2S1_BASE + 0x10,
+               .param.config = COH901318_CX_CFG_CH_DISABLE |
+                               COH901318_CX_CFG_LCR_DISABLE |
+                               COH901318_CX_CFG_TC_IRQ_ENABLE |
+                               COH901318_CX_CFG_BE_IRQ_ENABLE,
+               .param.ctrl_lli_chained = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_DISABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+               .param.ctrl_lli_last = 0 |
+                               COH901318_CX_CTRL_TC_ENABLE |
+                               COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                               COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                               COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                               COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                               COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                               COH901318_CX_CTRL_TCP_ENABLE |
+                               COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                               COH901318_CX_CTRL_HSP_ENABLE |
+                               COH901318_CX_CTRL_HSS_DISABLE |
+                               COH901318_CX_CTRL_DDMA_LEGACY |
+                               COH901318_CX_CTRL_PRDD_DEST,
+       },
+       {
+               .number = U300_DMA_XGAM_CDI,
+               .name = "XGAM CDI",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_XGAM_PDI,
+               .name = "XGAM PDI",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_SPI_TX,
+               .name = "SPI TX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_SPI_RX,
+               .name = "SPI RX",
+               .priority_high = 0,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_0,
+               .name = "GENERAL 00",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .param.ctrl_lli_last = flags_memcpy_lli_last,
+       },
+       {
+               .number = U300_DMA_GENERAL_PURPOSE_1,
+               .name = "GENERAL 01",
+               .priority_high = 0,
+
+               .param.config = flags_memcpy_config,
+               .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+               .param.ctrl_lli = flags_memcpy_lli,
+               .par