Merge tag 'drm-ast-2500-for-v4.11' of git://people.freedesktop.org/~airlied/linux
authorLinus Torvalds <torvalds@linux-foundation.org>
Wed, 1 Mar 2017 17:42:42 +0000 (09:42 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Wed, 1 Mar 2017 17:42:42 +0000 (09:42 -0800)
Pull drm AST2500 support from Dave Airlie:
 "This is a set of changes to enable the AST2500 BMC hardware, and also
  fix some bugs interacting with the older AST hardware.

  Some of the bug fixes are cc'ed to stable"

* tag 'drm-ast-2500-for-v4.11' of git://people.freedesktop.org/~airlied/linux:
  drm/ast: Call open_key before enable_mmio in POST code
  drm/ast: Fix test for VGA enabled
  drm/ast: POST code for the new AST2500
  drm/ast: Rename ast_init_dram_2300 to ast_post_chip_2300
  drm/ast: Factor mmc_test code in POST code
  drm/ast: Fixed vram size incorrect issue on POWER
  drm/ast: Base support for AST2500
  drm/ast: Fix calculation of MCLK
  drm/ast: Remove spurious include
  drm/ast: const'ify mode setting tables
  drm/ast: Handle configuration without P2A bridge
  drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS

drivers/gpu/drm/ast/ast_dram_tables.h
drivers/gpu/drm/ast/ast_drv.h
drivers/gpu/drm/ast/ast_main.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/ast/ast_post.c
drivers/gpu/drm/ast/ast_tables.h

index cc04539c0ff3dbc98aaa1d4db00e929897d8b188..1d9c4e75d3030a7ce67cdc4c16b15545da049538 100644 (file)
@@ -141,4 +141,66 @@ static const struct ast_dramstruct ast2100_dram_table_data[] = {
        { 0xffff, 0xffffffff },
 };
 
+/*
+ * AST2500 DRAM settings modules
+ */
+#define REGTBL_NUM           17
+#define REGIDX_010           0
+#define REGIDX_014           1
+#define REGIDX_018           2
+#define REGIDX_020           3
+#define REGIDX_024           4
+#define REGIDX_02C           5
+#define REGIDX_030           6
+#define REGIDX_214           7
+#define REGIDX_2E0           8
+#define REGIDX_2E4           9
+#define REGIDX_2E8           10
+#define REGIDX_2EC           11
+#define REGIDX_2F0           12
+#define REGIDX_2F4           13
+#define REGIDX_2F8           14
+#define REGIDX_RFC           15
+#define REGIDX_PLL           16
+
+static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
+       0x64604D38,                  /* 0x010 */
+       0x29690599,                  /* 0x014 */
+       0x00000300,                  /* 0x018 */
+       0x00000000,                  /* 0x020 */
+       0x00000000,                  /* 0x024 */
+       0x02181E70,                  /* 0x02C */
+       0x00000040,                  /* 0x030 */
+       0x00000024,                  /* 0x214 */
+       0x02001300,                  /* 0x2E0 */
+       0x0E0000A0,                  /* 0x2E4 */
+       0x000E001B,                  /* 0x2E8 */
+       0x35B8C105,                  /* 0x2EC */
+       0x08090408,                  /* 0x2F0 */
+       0x9B000800,                  /* 0x2F4 */
+       0x0E400A00,                  /* 0x2F8 */
+       0x9971452F,                  /* tRFC  */
+       0x000071C1                   /* PLL   */
+};
+
+static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
+       0x63604E37,                  /* 0x010 */
+       0xE97AFA99,                  /* 0x014 */
+       0x00019000,                  /* 0x018 */
+       0x08000000,                  /* 0x020 */
+       0x00000400,                  /* 0x024 */
+       0x00000410,                  /* 0x02C */
+       0x00000101,                  /* 0x030 */
+       0x00000024,                  /* 0x214 */
+       0x03002900,                  /* 0x2E0 */
+       0x0E0000A0,                  /* 0x2E4 */
+       0x000E001C,                  /* 0x2E8 */
+       0x35B8C106,                  /* 0x2EC */
+       0x08080607,                  /* 0x2F0 */
+       0x9B000900,                  /* 0x2F4 */
+       0x0E400A00,                  /* 0x2F8 */
+       0x99714545,                  /* tRFC  */
+       0x000071C1                   /* PLL   */
+};
+
 #endif
index 5a8fa1c8522987517a9f98589eb658f72bc21901..8880f0b62e9c2832845d7df2f40e0e77817a9f91 100644 (file)
@@ -65,6 +65,7 @@ enum ast_chip {
        AST2150,
        AST2300,
        AST2400,
+       AST2500,
        AST1180,
 };
 
@@ -81,6 +82,7 @@ enum ast_tx_chip {
 #define AST_DRAM_1Gx32   3
 #define AST_DRAM_2Gx16   6
 #define AST_DRAM_4Gx16   7
+#define AST_DRAM_8Gx16   8
 
 struct ast_fbdev;
 
@@ -114,7 +116,11 @@ struct ast_private {
        struct ttm_bo_kmap_obj cache_kmap;
        int next_cursor;
        bool support_wide_screen;
-       bool DisableP2A;
+       enum {
+               ast_use_p2a,
+               ast_use_dt,
+               ast_use_defaults
+       } config_mode;
 
        enum ast_tx_chip tx_chip_type;
        u8 dp501_maxclk;
@@ -301,8 +307,8 @@ struct ast_vbios_dclk_info {
 };
 
 struct ast_vbios_mode_info {
-       struct ast_vbios_stdtable *std_table;
-       struct ast_vbios_enhtable *enh_table;
+       const struct ast_vbios_stdtable *std_table;
+       const struct ast_vbios_enhtable *enh_table;
 };
 
 extern int ast_mode_init(struct drm_device *dev);
index 993909430736f04dd9d420db5aed015b52098ccc..262c2c0e43b4b162fae7530f88b143814abe8949 100644 (file)
@@ -32,8 +32,6 @@
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_crtc_helper.h>
 
-#include "ast_dram_tables.h"
-
 void ast_set_index_reg_mask(struct ast_private *ast,
                            uint32_t base, uint8_t index,
                            uint8_t mask, uint8_t val)
@@ -62,30 +60,99 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast,
        return ret;
 }
 
+static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
+{
+       struct device_node *np = dev->pdev->dev.of_node;
+       struct ast_private *ast = dev->dev_private;
+       uint32_t data, jregd0, jregd1;
+
+       /* Defaults */
+       ast->config_mode = ast_use_defaults;
+       *scu_rev = 0xffffffff;
+
+       /* Check if we have device-tree properties */
+       if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
+                                       scu_rev)) {
+               /* We do, disable P2A access */
+               ast->config_mode = ast_use_dt;
+               DRM_INFO("Using device-tree for configuration\n");
+               return;
+       }
+
+       /* Not all families have a P2A bridge */
+       if (dev->pdev->device != PCI_CHIP_AST2000)
+               return;
+
+       /*
+        * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
+        * is disabled. We force using P2A if VGA only mode bit
+        * is set D[7]
+        */
+       jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
+       jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
+       if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
+               /* Double check it's actually working */
+               data = ast_read32(ast, 0xf004);
+               if (data != 0xFFFFFFFF) {
+                       /* P2A works, grab silicon revision */
+                       ast->config_mode = ast_use_p2a;
+
+                       DRM_INFO("Using P2A bridge for configuration\n");
+
+                       /* Read SCU7c (silicon revision register) */
+                       ast_write32(ast, 0xf004, 0x1e6e0000);
+                       ast_write32(ast, 0xf000, 0x1);
+                       *scu_rev = ast_read32(ast, 0x1207c);
+                       return;
+               }
+       }
+
+       /* We have a P2A bridge but it's disabled */
+       DRM_INFO("P2A bridge disabled, using default configuration\n");
+}
 
 static int ast_detect_chip(struct drm_device *dev, bool *need_post)
 {
        struct ast_private *ast = dev->dev_private;
-       uint32_t data, jreg;
+       uint32_t jreg, scu_rev;
+
+       /*
+        * If VGA isn't enabled, we need to enable now or subsequent
+        * access to the scratch registers will fail. We also inform
+        * our caller that it needs to POST the chip
+        * (Assumption: VGA not enabled -> need to POST)
+        */
+       if (!ast_is_vga_enabled(dev)) {
+               ast_enable_vga(dev);
+               DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
+               *need_post = true;
+       } else
+               *need_post = false;
+
+
+       /* Enable extended register access */
+       ast_enable_mmio(dev);
        ast_open_key(ast);
 
+       /* Find out whether P2A works or whether to use device-tree */
+       ast_detect_config_mode(dev, &scu_rev);
+
+       /* Identify chipset */
        if (dev->pdev->device == PCI_CHIP_AST1180) {
                ast->chip = AST1100;
                DRM_INFO("AST 1180 detected\n");
        } else {
-               if (dev->pdev->revision >= 0x30) {
+               if (dev->pdev->revision >= 0x40) {
+                       ast->chip = AST2500;
+                       DRM_INFO("AST 2500 detected\n");
+               } else if (dev->pdev->revision >= 0x30) {
                        ast->chip = AST2400;
                        DRM_INFO("AST 2400 detected\n");
                } else if (dev->pdev->revision >= 0x20) {
                        ast->chip = AST2300;
                        DRM_INFO("AST 2300 detected\n");
                } else if (dev->pdev->revision >= 0x10) {
-                       uint32_t data;
-                       ast_write32(ast, 0xf004, 0x1e6e0000);
-                       ast_write32(ast, 0xf000, 0x1);
-
-                       data = ast_read32(ast, 0x1207c);
-                       switch (data & 0x0300) {
+                       switch (scu_rev & 0x0300) {
                        case 0x0200:
                                ast->chip = AST1100;
                                DRM_INFO("AST 1100 detected\n");
@@ -110,26 +177,6 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
                }
        }
 
-       /*
-        * If VGA isn't enabled, we need to enable now or subsequent
-        * access to the scratch registers will fail. We also inform
-        * our caller that it needs to POST the chip
-        * (Assumption: VGA not enabled -> need to POST)
-        */
-       if (!ast_is_vga_enabled(dev)) {
-               ast_enable_vga(dev);
-               ast_enable_mmio(dev);
-               DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
-               *need_post = true;
-       } else
-               *need_post = false;
-
-       /* Check P2A Access */
-       ast->DisableP2A = true;
-       data = ast_read32(ast, 0xf004);
-       if (data != 0xFFFFFFFF)
-               ast->DisableP2A = false;
-
        /* Check if we support wide screen */
        switch (ast->chip) {
        case AST1180:
@@ -146,17 +193,15 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
                        ast->support_wide_screen = true;
                else {
                        ast->support_wide_screen = false;
-                       if (ast->DisableP2A == false) {
-                               /* Read SCU7c (silicon revision register) */
-                               ast_write32(ast, 0xf004, 0x1e6e0000);
-                               ast_write32(ast, 0xf000, 0x1);
-                               data = ast_read32(ast, 0x1207c);
-                               data &= 0x300;
-                               if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
-                                       ast->support_wide_screen = true;
-                               if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
-                                       ast->support_wide_screen = true;
-                       }
+                       if (ast->chip == AST2300 &&
+                           (scu_rev & 0x300) == 0x0) /* ast1300 */
+                               ast->support_wide_screen = true;
+                       if (ast->chip == AST2400 &&
+                           (scu_rev & 0x300) == 0x100) /* ast1400 */
+                               ast->support_wide_screen = true;
+                       if (ast->chip == AST2500 &&
+                           scu_rev == 0x100)           /* ast2510 */
+                               ast->support_wide_screen = true;
                }
                break;
        }
@@ -220,85 +265,121 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
 
 static int ast_get_dram_info(struct drm_device *dev)
 {
+       struct device_node *np = dev->pdev->dev.of_node;
        struct ast_private *ast = dev->dev_private;
-       uint32_t data, data2;
-       uint32_t denum, num, div, ref_pll;
+       uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
+       uint32_t denum, num, div, ref_pll, dsel;
 
-       if (ast->DisableP2A)
-       {
-               ast->dram_bus_width = 16;
-               ast->dram_type = AST_DRAM_1Gx16;
-               ast->mclk = 396;
-       }
-       else
-       {
+       switch (ast->config_mode) {
+       case ast_use_dt:
+               /*
+                * If some properties are missing, use reasonable
+                * defaults for AST2400
+                */
+               if (of_property_read_u32(np, "aspeed,mcr-configuration",
+                                        &mcr_cfg))
+                       mcr_cfg = 0x00000577;
+               if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
+                                        &mcr_scu_mpll))
+                       mcr_scu_mpll = 0x000050C0;
+               if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
+                                        &mcr_scu_strap))
+                       mcr_scu_strap = 0;
+               break;
+       case ast_use_p2a:
                ast_write32(ast, 0xf004, 0x1e6e0000);
                ast_write32(ast, 0xf000, 0x1);
-               data = ast_read32(ast, 0x10004);
-
-               if (data & 0x40)
-                       ast->dram_bus_width = 16;
+               mcr_cfg = ast_read32(ast, 0x10004);
+               mcr_scu_mpll = ast_read32(ast, 0x10120);
+               mcr_scu_strap = ast_read32(ast, 0x10170);
+               break;
+       case ast_use_defaults:
+       default:
+               ast->dram_bus_width = 16;
+               ast->dram_type = AST_DRAM_1Gx16;
+               if (ast->chip == AST2500)
+                       ast->mclk = 800;
                else
-                       ast->dram_bus_width = 32;
-
-               if (ast->chip == AST2300 || ast->chip == AST2400) {
-                       switch (data & 0x03) {
-                       case 0:
-                               ast->dram_type = AST_DRAM_512Mx16;
-                               break;
-                       default:
-                       case 1:
-                               ast->dram_type = AST_DRAM_1Gx16;
-                               break;
-                       case 2:
-                               ast->dram_type = AST_DRAM_2Gx16;
-                               break;
-                       case 3:
-                               ast->dram_type = AST_DRAM_4Gx16;
-                               break;
-                       }
-               } else {
-                       switch (data & 0x0c) {
-                       case 0:
-                       case 4:
-                               ast->dram_type = AST_DRAM_512Mx16;
-                               break;
-                       case 8:
-                               if (data & 0x40)
-                                       ast->dram_type = AST_DRAM_1Gx16;
-                               else
-                                       ast->dram_type = AST_DRAM_512Mx32;
-                               break;
-                       case 0xc:
-                               ast->dram_type = AST_DRAM_1Gx32;
-                               break;
-                       }
-               }
+                       ast->mclk = 396;
+               return 0;
+       }
 
-               data = ast_read32(ast, 0x10120);
-               data2 = ast_read32(ast, 0x10170);
-               if (data2 & 0x2000)
-                       ref_pll = 14318;
-               else
-                       ref_pll = 12000;
+       if (mcr_cfg & 0x40)
+               ast->dram_bus_width = 16;
+       else
+               ast->dram_bus_width = 32;
 
-               denum = data & 0x1f;
-               num = (data & 0x3fe0) >> 5;
-               data = (data & 0xc000) >> 14;
-               switch (data) {
-               case 3:
-                       div = 0x4;
+       if (ast->chip == AST2500) {
+               switch (mcr_cfg & 0x03) {
+               case 0:
+                       ast->dram_type = AST_DRAM_1Gx16;
                        break;
-               case 2:
+               default:
                case 1:
-                       div = 0x2;
+                       ast->dram_type = AST_DRAM_2Gx16;
+                       break;
+               case 2:
+                       ast->dram_type = AST_DRAM_4Gx16;
+                       break;
+               case 3:
+                       ast->dram_type = AST_DRAM_8Gx16;
+                       break;
+               }
+       } else if (ast->chip == AST2300 || ast->chip == AST2400) {
+               switch (mcr_cfg & 0x03) {
+               case 0:
+                       ast->dram_type = AST_DRAM_512Mx16;
                        break;
                default:
-                       div = 0x1;
+               case 1:
+                       ast->dram_type = AST_DRAM_1Gx16;
+                       break;
+               case 2:
+                       ast->dram_type = AST_DRAM_2Gx16;
+                       break;
+               case 3:
+                       ast->dram_type = AST_DRAM_4Gx16;
+                       break;
+               }
+       } else {
+               switch (mcr_cfg & 0x0c) {
+               case 0:
+               case 4:
+                       ast->dram_type = AST_DRAM_512Mx16;
+                       break;
+               case 8:
+                       if (mcr_cfg & 0x40)
+                               ast->dram_type = AST_DRAM_1Gx16;
+                       else
+                               ast->dram_type = AST_DRAM_512Mx32;
+                       break;
+               case 0xc:
+                       ast->dram_type = AST_DRAM_1Gx32;
                        break;
                }
-               ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
        }
+
+       if (mcr_scu_strap & 0x2000)
+               ref_pll = 14318;
+       else
+               ref_pll = 12000;
+
+       denum = mcr_scu_mpll & 0x1f;
+       num = (mcr_scu_mpll & 0x3fe0) >> 5;
+       dsel = (mcr_scu_mpll & 0xc000) >> 14;
+       switch (dsel) {
+       case 3:
+               div = 0x4;
+               break;
+       case 2:
+       case 1:
+               div = 0x2;
+               break;
+       default:
+               div = 0x1;
+               break;
+       }
+       ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
        return 0;
 }
 
@@ -437,17 +518,19 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
 
        ast_detect_chip(dev, &need_post);
 
+       if (need_post)
+               ast_post_gpu(dev);
+
        if (ast->chip != AST1180) {
                ret = ast_get_dram_info(dev);
                if (ret)
                        goto out_free;
                ast->vram_size = ast_get_vram_info(dev);
-               DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
+               DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
+                        ast->mclk, ast->dram_type,
+                        ast->dram_bus_width, ast->vram_size);
        }
 
-       if (need_post)
-               ast_post_gpu(dev);
-
        ret = ast_mm_init(ast);
        if (ret)
                goto out_free;
@@ -465,6 +548,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
            ast->chip == AST2200 ||
            ast->chip == AST2300 ||
            ast->chip == AST2400 ||
+           ast->chip == AST2500 ||
            ast->chip == AST1180) {
                dev->mode_config.max_width = 1920;
                dev->mode_config.max_height = 2048;
index 606cb40f6c7cd6ccdaee2d5d1c61e7c105049689..47b78e52691cb33bb7cc3b189d92f35b11510340 100644 (file)
@@ -81,9 +81,9 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
        struct ast_private *ast = crtc->dev->dev_private;
        const struct drm_framebuffer *fb = crtc->primary->fb;
        u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
+       const struct ast_vbios_enhtable *best = NULL;
        u32 hborder, vborder;
        bool check_sync;
-       struct ast_vbios_enhtable *best = NULL;
 
        switch (fb->format->cpp[0] * 8) {
        case 8:
@@ -147,7 +147,7 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
        refresh_rate = drm_mode_vrefresh(mode);
        check_sync = vbios_mode->enh_table->flags & WideScreenMode;
        do {
-               struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
+               const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
 
                while (loop->refresh_rate != 0xff) {
                        if ((check_sync) &&
@@ -227,7 +227,7 @@ static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
                            struct ast_vbios_mode_info *vbios_mode)
 {
        struct ast_private *ast = crtc->dev->dev_private;
-       struct ast_vbios_stdtable *stdtable;
+       const struct ast_vbios_stdtable *stdtable;
        u32 i;
        u8 jreg;
 
@@ -273,7 +273,11 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
 {
        struct ast_private *ast = crtc->dev->dev_private;
        u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
-       u16 temp;
+       u16 temp, precache = 0;
+
+       if ((ast->chip == AST2500) &&
+           (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
+               precache = 40;
 
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
 
@@ -299,12 +303,12 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
                jregAD |= 0x01;  /* HBE D[5] */
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
 
-       temp = (mode->crtc_hsync_start >> 3) - 1;
+       temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
        if (temp & 0x100)
                jregAC |= 0x40; /* HRS D[5] */
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
 
-       temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
+       temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
        if (temp & 0x20)
                jregAD |= 0x04; /* HRE D[5] */
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
@@ -365,6 +369,11 @@ static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mod
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
 
+       if (precache)
+               ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
+       else
+               ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
+
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
 }
 
@@ -384,14 +393,18 @@ static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mo
                             struct ast_vbios_mode_info *vbios_mode)
 {
        struct ast_private *ast = dev->dev_private;
-       struct ast_vbios_dclk_info *clk_info;
+       const struct ast_vbios_dclk_info *clk_info;
 
-       clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
+       if (ast->chip == AST2500)
+               clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
+       else
+               clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
 
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
-                              (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
+                              (clk_info->param3 & 0xc0) |
+                              ((clk_info->param3 & 0x3) << 4));
 }
 
 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
@@ -425,7 +438,8 @@ static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
 
        /* Set Threshold */
-       if (ast->chip == AST2300 || ast->chip == AST2400) {
+       if (ast->chip == AST2300 || ast->chip == AST2400 ||
+           ast->chip == AST2500) {
                ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
                ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
        } else if (ast->chip == AST2100 ||
@@ -800,7 +814,9 @@ static int ast_mode_valid(struct drm_connector *connector,
                if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
                        return MODE_OK;
 
-               if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
+               if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
+                   (ast->chip == AST2300) || (ast->chip == AST2400) ||
+                   (ast->chip == AST2500) || (ast->chip == AST1180)) {
                        if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
                                return MODE_OK;
 
index 5331ee1df086e7ae3950e33efc38975b544abdd4..f7d421359d564756ff86d78c64293e37eea74c7e 100644 (file)
@@ -31,7 +31,8 @@
 
 #include "ast_dram_tables.h"
 
-static void ast_init_dram_2300(struct drm_device *dev);
+static void ast_post_chip_2300(struct drm_device *dev);
+static void ast_post_chip_2500(struct drm_device *dev);
 
 void ast_enable_vga(struct drm_device *dev)
 {
@@ -58,13 +59,9 @@ bool ast_is_vga_enabled(struct drm_device *dev)
                /* TODO 1180 */
        } else {
                ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
-               if (ch) {
-                       ast_open_key(ast);
-                       ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
-                       return ch & 0x04;
-               }
+               return !!(ch & 0x01);
        }
-       return 0;
+       return false;
 }
 
 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
@@ -79,10 +76,11 @@ ast_set_def_ext_reg(struct drm_device *dev)
        const u8 *ext_reg_info;
 
        /* reset scratch */
-       for (i = 0x81; i <= 0x8f; i++)
+       for (i = 0x81; i <= 0x9f; i++)
                ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
 
-       if (ast->chip == AST2300 || ast->chip == AST2400) {
+       if (ast->chip == AST2300 || ast->chip == AST2400 ||
+           ast->chip == AST2500) {
                if (dev->pdev->revision >= 0x20)
                        ext_reg_info = extreginfo_ast2300;
                else
@@ -106,7 +104,8 @@ ast_set_def_ext_reg(struct drm_device *dev)
 
        /* Enable RAMDAC for A1 */
        reg = 0x04;
-       if (ast->chip == AST2300 || ast->chip == AST2400)
+       if (ast->chip == AST2300 || ast->chip == AST2400 ||
+           ast->chip == AST2500)
                reg |= 0x20;
        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
 }
@@ -375,21 +374,20 @@ void ast_post_gpu(struct drm_device *dev)
        pci_write_config_dword(ast->dev->pdev, 0x04, reg);
 
        ast_enable_vga(dev);
-       ast_enable_mmio(dev);
        ast_open_key(ast);
+       ast_enable_mmio(dev);
        ast_set_def_ext_reg(dev);
 
-       if (ast->DisableP2A == false)
-       {
-               if (ast->chip == AST2300 || ast->chip == AST2400)
-                       ast_init_dram_2300(dev);
+       if (ast->config_mode == ast_use_p2a) {
+               if (ast->chip == AST2500)
+                       ast_post_chip_2500(dev);
+               else if (ast->chip == AST2300 || ast->chip == AST2400)
+                       ast_post_chip_2300(dev);
                else
                        ast_init_dram_reg(dev);
 
                ast_init_3rdtx(dev);
-       }
-       else
-       {
+       } else {
                if (ast->tx_chip_type != AST_TX_NONE)
                        ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);        /* Enable DVO */
        }
@@ -448,85 +446,70 @@ static const u32 pattern[8] = {
        0x7C61D253
 };
 
-static int mmc_test_burst(struct ast_private *ast, u32 datagen)
+static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
 {
        u32 data, timeout;
 
        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-       ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
+       ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
        timeout = 0;
        do {
                data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
-               if (data & 0x2000) {
-                       return 0;
-               }
+               if (data & 0x2000)
+                       return false;
                if (++timeout > TIMEOUT) {
                        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-                       return 0;
+                       return false;
                }
        } while (!data);
-       ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-       return 1;
+       ast_moutdwm(ast, 0x1e6e0070, 0x0);
+       return true;
 }
 
-static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
+static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
 {
        u32 data, timeout;
 
        ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-       ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
+       ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
        timeout = 0;
        do {
                data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
                if (++timeout > TIMEOUT) {
                        ast_moutdwm(ast, 0x1e6e0070, 0x0);
-                       return -1;
+                       return 0xffffffff;
                }
        } while (!data);
        data = ast_mindwm(ast, 0x1e6e0078);
        data = (data | (data >> 16)) & 0xffff;
-       ast_moutdwm(ast, 0x1e6e0070, 0x0);
+       ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
        return data;
 }
 
-static int mmc_test_single(struct ast_private *ast, u32 datagen)
+
+static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
 {
-       u32 data, timeout;
+       return mmc_test(ast, datagen, 0xc1);
+}
 
-       ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-       ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
-       timeout = 0;
-       do {
-               data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
-               if (data & 0x2000)
-                       return 0;
-               if (++timeout > TIMEOUT) {
-                       ast_moutdwm(ast, 0x1e6e0070, 0x0);
-                       return 0;
-               }
-       } while (!data);
-       ast_moutdwm(ast, 0x1e6e0070, 0x0);
-       return 1;
+static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
+{
+       return mmc_test2(ast, datagen, 0x41);
 }
 
-static int mmc_test_single2(struct ast_private *ast, u32 datagen)
+static bool mmc_test_single(struct ast_private *ast, u32 datagen)
 {
-       u32 data, timeout;
+       return mmc_test(ast, datagen, 0xc5);
+}
 
-       ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
-       ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
-       timeout = 0;
-       do {
-               data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
-               if (++timeout > TIMEOUT) {
-                       ast_moutdwm(ast, 0x1e6e0070, 0x0);
-                       return -1;
-               }
-       } while (!data);
-       data = ast_mindwm(ast, 0x1e6e0078);
-       data = (data | (data >> 16)) & 0xffff;
-       ast_moutdwm(ast, 0x1e6e0070, 0x0);
-       return data;
+static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
+{
+       return mmc_test2(ast, datagen, 0x05);
+}
+
+static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
+{
+       return mmc_test(ast, datagen, 0x85);
 }
 
 static int cbr_test(struct ast_private *ast)
@@ -604,16 +587,16 @@ static u32 cbr_scan2(struct ast_private *ast)
        return data2;
 }
 
-static u32 cbr_test3(struct ast_private *ast)
+static bool cbr_test3(struct ast_private *ast)
 {
        if (!mmc_test_burst(ast, 0))
-               return 0;
+               return false;
        if (!mmc_test_single(ast, 0))
-               return 0;
-       return 1;
+               return false;
+       return true;
 }
 
-static u32 cbr_scan3(struct ast_private *ast)
+static bool cbr_scan3(struct ast_private *ast)
 {
        u32 patcnt, loop;
 
@@ -624,9 +607,9 @@ static u32 cbr_scan3(struct ast_private *ast)
                                break;
                }
                if (loop == 2)
-                       return 0;
+                       return false;
        }
-       return 1;
+       return true;
 }
 
 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -1612,7 +1595,7 @@ ddr2_init_start:
 
 }
 
-static void ast_init_dram_2300(struct drm_device *dev)
+static void ast_post_chip_2300(struct drm_device *dev)
 {
        struct ast_private *ast = dev->dev_private;
        struct ast2300_dram_param param;
@@ -1638,12 +1621,44 @@ static void ast_init_dram_2300(struct drm_device *dev)
                temp |= 0x73;
                ast_write32(ast, 0x12008, temp);
 
+               param.dram_freq = 396;
                param.dram_type = AST_DDR3;
+               temp = ast_mindwm(ast, 0x1e6e2070);
                if (temp & 0x01000000)
                        param.dram_type = AST_DDR2;
-               param.dram_chipid = ast->dram_type;
-               param.dram_freq = ast->mclk;
-               param.vram_size = ast->vram_size;
+                switch (temp & 0x18000000) {
+               case 0:
+                       param.dram_chipid = AST_DRAM_512Mx16;
+                       break;
+               default:
+               case 0x08000000:
+                       param.dram_chipid = AST_DRAM_1Gx16;
+                       break;
+               case 0x10000000:
+                       param.dram_chipid = AST_DRAM_2Gx16;
+                       break;
+               case 0x18000000:
+                       param.dram_chipid = AST_DRAM_4Gx16;
+                       break;
+               }
+                switch (temp & 0x0c) {
+                default:
+               case 0x00:
+                       param.vram_size = AST_VIDMEM_SIZE_8M;
+                       break;
+
+               case 0x04:
+                       param.vram_size = AST_VIDMEM_SIZE_16M;
+                       break;
+
+               case 0x08:
+                       param.vram_size = AST_VIDMEM_SIZE_32M;
+                       break;
+
+               case 0x0c:
+                       param.vram_size = AST_VIDMEM_SIZE_64M;
+                       break;
+               }
 
                if (param.dram_type == AST_DDR3) {
                        get_ddr3_info(ast, &param);
@@ -1663,3 +1678,404 @@ static void ast_init_dram_2300(struct drm_device *dev)
        } while ((reg & 0x40) == 0);
 }
 
+static bool cbr_test_2500(struct ast_private *ast)
+{
+       ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
+       ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
+       if (!mmc_test_burst(ast, 0))
+               return false;
+       if (!mmc_test_single_2500(ast, 0))
+               return false;
+       return true;
+}
+
+static bool ddr_test_2500(struct ast_private *ast)
+{
+       ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
+       ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
+       if (!mmc_test_burst(ast, 0))
+               return false;
+       if (!mmc_test_burst(ast, 1))
+               return false;
+       if (!mmc_test_burst(ast, 2))
+               return false;
+       if (!mmc_test_burst(ast, 3))
+               return false;
+       if (!mmc_test_single_2500(ast, 0))
+               return false;
+       return true;
+}
+
+static void ddr_init_common_2500(struct ast_private *ast)
+{
+       ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
+       ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
+       ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
+       ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
+       ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
+       ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
+       ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
+       ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
+       ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
+       ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
+       ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
+       ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
+}
+
+static void ddr_phy_init_2500(struct ast_private *ast)
+{
+       u32 data, pass, timecnt;
+
+       pass = 0;
+       ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
+       while (!pass) {
+               for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
+                       data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
+                       if (!data)
+                               break;
+               }
+               if (timecnt != TIMEOUT) {
+                       data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
+                       if (!data)
+                               pass = 1;
+               }
+               if (!pass) {
+                       ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+                       udelay(10); /* delay 10 us */
+                       ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
+               }
+       }
+
+       ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
+}
+
+/*
+ * Check DRAM Size
+ * 1Gb : 0x80000000 ~ 0x87FFFFFF
+ * 2Gb : 0x80000000 ~ 0x8FFFFFFF
+ * 4Gb : 0x80000000 ~ 0x9FFFFFFF
+ * 8Gb : 0x80000000 ~ 0xBFFFFFFF
+ */
+static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
+{
+       u32 reg_04, reg_14;
+
+       reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
+       reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
+
+       ast_moutdwm(ast, 0xA0100000, 0x41424344);
+       ast_moutdwm(ast, 0x90100000, 0x35363738);
+       ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
+       ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
+
+       /* Check 8Gbit */
+       if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
+               reg_04 |= 0x03;
+               reg_14 |= (tRFC >> 24) & 0xFF;
+               /* Check 4Gbit */
+       } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
+               reg_04 |= 0x02;
+               reg_14 |= (tRFC >> 16) & 0xFF;
+               /* Check 2Gbit */
+       } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
+               reg_04 |= 0x01;
+               reg_14 |= (tRFC >> 8) & 0xFF;
+       } else {
+               reg_14 |= tRFC & 0xFF;
+       }
+       ast_moutdwm(ast, 0x1E6E0004, reg_04);
+       ast_moutdwm(ast, 0x1E6E0014, reg_14);
+}
+
+static void enable_cache_2500(struct ast_private *ast)
+{
+       u32 reg_04, data;
+
+       reg_04 = ast_mindwm(ast, 0x1E6E0004);
+       ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
+
+       do
+               data = ast_mindwm(ast, 0x1E6E0004);
+       while (!(data & 0x80000));
+       ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
+}
+
+static void set_mpll_2500(struct ast_private *ast)
+{
+       u32 addr, data, param;
+
+       /* Reset MMC */
+       ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
+       ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
+       for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
+               ast_moutdwm(ast, addr, 0x0);
+               addr += 4;
+       }
+       ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
+
+       ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
+       data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
+       if (data) {
+               /* CLKIN = 25MHz */
+               param = 0x930023E0;
+               ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
+       } else {
+               /* CLKIN = 24MHz */
+               param = 0x93002400;
+       }
+       ast_moutdwm(ast, 0x1E6E2020, param);
+       udelay(100);
+}
+
+static void reset_mmc_2500(struct ast_private *ast)
+{
+       ast_moutdwm(ast, 0x1E78505C, 0x00000004);
+       ast_moutdwm(ast, 0x1E785044, 0x00000001);
+       ast_moutdwm(ast, 0x1E785048, 0x00004755);
+       ast_moutdwm(ast, 0x1E78504C, 0x00000013);
+       mdelay(100);
+       ast_moutdwm(ast, 0x1E785054, 0x00000077);
+       ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
+}
+
+static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
+{
+
+       ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
+       ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
+       ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
+       ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
+       ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
+       ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
+       ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
+       ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
+
+       /* DDR PHY Setting */
+       ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
+       ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
+       ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
+       ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
+       ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
+       ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
+       ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
+       ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
+       ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
+       ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
+       ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
+       ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
+       ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
+       ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
+
+       /* Controller Setting */
+       ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
+
+       /* Wait DDR PHY init done */
+       ddr_phy_init_2500(ast);
+
+       ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
+       ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
+       ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
+
+       check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
+       enable_cache_2500(ast);
+       ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
+       ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
+}
+
+static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
+{
+       u32 data, data2, pass, retrycnt;
+       u32 ddr_vref, phy_vref;
+       u32 min_ddr_vref = 0, min_phy_vref = 0;
+       u32 max_ddr_vref = 0, max_phy_vref = 0;
+
+       ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
+       ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
+       ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
+       ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
+       ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
+       ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
+       ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
+       ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
+
+       /* DDR PHY Setting */
+       ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
+       ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
+       ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
+       ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
+       ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
+       ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
+       ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
+       ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
+       ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
+       ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
+       ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
+       ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
+       ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
+       ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
+       ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
+
+       /* Controller Setting */
+       ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
+
+       /* Train PHY Vref first */
+       pass = 0;
+
+       for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
+               max_phy_vref = 0x0;
+               pass = 0;
+               ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
+               for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
+                       ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+                       ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+                       ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
+                       /* Fire DFI Init */
+                       ddr_phy_init_2500(ast);
+                       ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
+                       if (cbr_test_2500(ast)) {
+                               pass++;
+                               data = ast_mindwm(ast, 0x1E6E03D0);
+                               data2 = data >> 8;
+                               data  = data & 0xff;
+                               if (data > data2)
+                                       data = data2;
+                               if (max_phy_vref < data) {
+                                       max_phy_vref = data;
+                                       min_phy_vref = phy_vref;
+                               }
+                       } else if (pass > 0)
+                               break;
+               }
+       }
+       ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
+
+       /* Train DDR Vref next */
+       pass = 0;
+
+       for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
+               min_ddr_vref = 0xFF;
+               max_ddr_vref = 0x0;
+               pass = 0;
+               for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
+                       ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+                       ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+                       ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
+                       /* Fire DFI Init */
+                       ddr_phy_init_2500(ast);
+                       ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
+                       if (cbr_test_2500(ast)) {
+                               pass++;
+                               if (min_ddr_vref > ddr_vref)
+                                       min_ddr_vref = ddr_vref;
+                               if (max_ddr_vref < ddr_vref)
+                                       max_ddr_vref = ddr_vref;
+                       } else if (pass != 0)
+                               break;
+               }
+       }
+
+       ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
+       ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
+       ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
+       ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
+
+       /* Wait DDR PHY init done */
+       ddr_phy_init_2500(ast);
+
+       ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
+       ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
+       ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
+
+       check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
+       enable_cache_2500(ast);
+       ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
+       ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
+}
+
+static bool ast_dram_init_2500(struct ast_private *ast)
+{
+       u32 data;
+       u32 max_tries = 5;
+
+       do {
+               if (max_tries-- == 0)
+                       return false;
+               set_mpll_2500(ast);
+               reset_mmc_2500(ast);
+               ddr_init_common_2500(ast);
+
+               data = ast_mindwm(ast, 0x1E6E2070);
+               if (data & 0x01000000)
+                       ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
+               else
+                       ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
+       } while (!ddr_test_2500(ast));
+
+       ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
+
+       /* Patch code */
+       data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
+       ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
+
+       return true;
+}
+
+void ast_post_chip_2500(struct drm_device *dev)
+{
+       struct ast_private *ast = dev->dev_private;
+       u32 temp;
+       u8 reg;
+
+       reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
+       if ((reg & 0x80) == 0) {/* vga only */
+               /* Clear bus lock condition */
+               ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
+               ast_moutdwm(ast, 0x1e600084, 0x00010000);
+               ast_moutdwm(ast, 0x1e600088, 0x00000000);
+               ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
+               ast_write32(ast, 0xf004, 0x1e6e0000);
+               ast_write32(ast, 0xf000, 0x1);
+               ast_write32(ast, 0x12000, 0x1688a8a8);
+               while (ast_read32(ast, 0x12000) != 0x1)
+                       ;
+
+               ast_write32(ast, 0x10000, 0xfc600309);
+               while (ast_read32(ast, 0x10000) != 0x1)
+                       ;
+
+               /* Slow down CPU/AHB CLK in VGA only mode */
+               temp = ast_read32(ast, 0x12008);
+               temp |= 0x73;
+               ast_write32(ast, 0x12008, temp);
+
+               /* Reset USB port to patch USB unknown device issue */
+               ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
+               temp  = ast_mindwm(ast, 0x1e6e2094);
+               temp |= 0x00004000;
+               ast_moutdwm(ast, 0x1e6e2094, temp);
+               temp  = ast_mindwm(ast, 0x1e6e2070);
+               if (temp & 0x00800000) {
+                       ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
+                       mdelay(100);
+                       ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
+               }
+
+               if (!ast_dram_init_2500(ast))
+                       DRM_ERROR("DRAM init failed !\n");
+
+               temp = ast_mindwm(ast, 0x1e6e2040);
+               ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
+       }
+
+       /* wait ready */
+       do {
+               reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
+       } while ((reg & 0x40) == 0);
+}
index 3608d5aa7451a458a07fcfe3199ce3984108992b..5f4c2e833a650dd6be2e6afb5e9835cf7e434e17 100644 (file)
@@ -47,6 +47,7 @@
 #define SyncPN                 (PVSync | NHSync)
 #define SyncNP                 (NVSync | PHSync)
 #define SyncNN                 (NVSync | NHSync)
+#define AST2500PreCatchCRT             0x00004000
 
 /* DCLK Index */
 #define VCLK25_175                     0x00
 #define VCLK97_75              0x19
 #define VCLK118_25                     0x1A
 
-static struct ast_vbios_dclk_info dclk_table[] = {
-       {0x2C, 0xE7, 0x03},                                     /* 00: VCLK25_175       */
-       {0x95, 0x62, 0x03},                                     /* 01: VCLK28_322       */
-       {0x67, 0x63, 0x01},                                     /* 02: VCLK31_5         */
-       {0x76, 0x63, 0x01},                                     /* 03: VCLK36           */
-       {0xEE, 0x67, 0x01},                                     /* 04: VCLK40           */
-       {0x82, 0x62, 0x01},                             /* 05: VCLK49_5         */
-       {0xC6, 0x64, 0x01},                                     /* 06: VCLK50           */
-       {0x94, 0x62, 0x01},                                     /* 07: VCLK56_25        */
-       {0x80, 0x64, 0x00},                                     /* 08: VCLK65           */
-       {0x7B, 0x63, 0x00},                                     /* 09: VCLK75           */
-       {0x67, 0x62, 0x00},                                     /* 0A: VCLK78_75        */
-       {0x7C, 0x62, 0x00},                                     /* 0B: VCLK94_5         */
-       {0x8E, 0x62, 0x00},                                     /* 0C: VCLK108          */
-       {0x85, 0x24, 0x00},                                     /* 0D: VCLK135          */
-       {0x67, 0x22, 0x00},                                     /* 0E: VCLK157_5        */
-       {0x6A, 0x22, 0x00},                                     /* 0F: VCLK162          */
-       {0x4d, 0x4c, 0x80},                                     /* 10: VCLK154          */
-       {0xa7, 0x78, 0x80},                                     /* 11: VCLK83.5         */
-       {0x28, 0x49, 0x80},                                     /* 12: VCLK106.5        */
-       {0x37, 0x49, 0x80},                                     /* 13: VCLK146.25       */
-       {0x1f, 0x45, 0x80},                                     /* 14: VCLK148.5        */
-       {0x47, 0x6c, 0x80},                                     /* 15: VCLK71       */
-       {0x25, 0x65, 0x80},                                     /* 16: VCLK88.75    */
-       {0x77, 0x58, 0x80},                                     /* 17: VCLK119      */
-       {0x32, 0x67, 0x80},                                 /* 18: VCLK85_5     */
-       {0x6a, 0x6d, 0x80},                                     /* 19: VCLK97_75        */
-       {0x3b, 0x2c, 0x81},                                     /* 1A: VCLK118_25       */
+static const struct ast_vbios_dclk_info dclk_table[] = {
+       {0x2C, 0xE7, 0x03},                     /* 00: VCLK25_175       */
+       {0x95, 0x62, 0x03},                     /* 01: VCLK28_322       */
+       {0x67, 0x63, 0x01},                     /* 02: VCLK31_5         */
+       {0x76, 0x63, 0x01},                     /* 03: VCLK36           */
+       {0xEE, 0x67, 0x01},                     /* 04: VCLK40           */
+       {0x82, 0x62, 0x01},                     /* 05: VCLK49_5         */
+       {0xC6, 0x64, 0x01},                     /* 06: VCLK50           */
+       {0x94, 0x62, 0x01},                     /* 07: VCLK56_25        */
+       {0x80, 0x64, 0x00},                     /* 08: VCLK65           */
+       {0x7B, 0x63, 0x00},                     /* 09: VCLK75           */
+       {0x67, 0x62, 0x00},                     /* 0A: VCLK78_75        */
+       {0x7C, 0x62, 0x00},                     /* 0B: VCLK94_5         */
+       {0x8E, 0x62, 0x00},                     /* 0C: VCLK108          */
+       {0x85, 0x24, 0x00},                     /* 0D: VCLK135          */
+       {0x67, 0x22, 0x00},                     /* 0E: VCLK157_5        */
+       {0x6A, 0x22, 0x00},                     /* 0F: VCLK162          */
+       {0x4d, 0x4c, 0x80},                     /* 10: VCLK154          */
+       {0xa7, 0x78, 0x80},                     /* 11: VCLK83.5         */
+       {0x28, 0x49, 0x80},                     /* 12: VCLK106.5        */
+       {0x37, 0x49, 0x80},                     /* 13: VCLK146.25       */
+       {0x1f, 0x45, 0x80},                     /* 14: VCLK148.5        */
+       {0x47, 0x6c, 0x80},                     /* 15: VCLK71           */
+       {0x25, 0x65, 0x80},                     /* 16: VCLK88.75        */
+       {0x77, 0x58, 0x80},                     /* 17: VCLK119          */
+       {0x32, 0x67, 0x80},                     /* 18: VCLK85_5         */
+       {0x6a, 0x6d, 0x80},                     /* 19: VCLK97_75        */
+       {0x3b, 0x2c, 0x81},                     /* 1A: VCLK118_25       */
 };
 
-static struct ast_vbios_stdtable vbios_stdtable[] = {
+static const struct ast_vbios_dclk_info dclk_table_ast2500[] = {
+       {0x2C, 0xE7, 0x03},                     /* 00: VCLK25_175       */
+       {0x95, 0x62, 0x03},                     /* 01: VCLK28_322       */
+       {0x67, 0x63, 0x01},                     /* 02: VCLK31_5         */
+       {0x76, 0x63, 0x01},                     /* 03: VCLK36           */
+       {0xEE, 0x67, 0x01},                     /* 04: VCLK40           */
+       {0x82, 0x62, 0x01},                     /* 05: VCLK49_5         */
+       {0xC6, 0x64, 0x01},                     /* 06: VCLK50           */
+       {0x94, 0x62, 0x01},                     /* 07: VCLK56_25        */
+       {0x80, 0x64, 0x00},                     /* 08: VCLK65           */
+       {0x7B, 0x63, 0x00},                     /* 09: VCLK75           */
+       {0x67, 0x62, 0x00},                     /* 0A: VCLK78_75        */
+       {0x7C, 0x62, 0x00},                     /* 0B: VCLK94_5         */
+       {0x8E, 0x62, 0x00},                     /* 0C: VCLK108          */
+       {0x85, 0x24, 0x00},                     /* 0D: VCLK135          */
+       {0x67, 0x22, 0x00},                     /* 0E: VCLK157_5        */
+       {0x6A, 0x22, 0x00},                     /* 0F: VCLK162          */
+       {0x4d, 0x4c, 0x80},                     /* 10: VCLK154          */
+       {0xa7, 0x78, 0x80},                     /* 11: VCLK83.5         */
+       {0x28, 0x49, 0x80},                     /* 12: VCLK106.5        */
+       {0x37, 0x49, 0x80},                     /* 13: VCLK146.25       */
+       {0x1f, 0x45, 0x80},                     /* 14: VCLK148.5        */
+       {0x47, 0x6c, 0x80},                     /* 15: VCLK71           */
+       {0x25, 0x65, 0x80},                     /* 16: VCLK88.75        */
+       {0x58, 0x01, 0x42},                     /* 17: VCLK119          */
+       {0x32, 0x67, 0x80},                     /* 18: VCLK85_5         */
+       {0x6a, 0x6d, 0x80},                     /* 19: VCLK97_75        */
+       {0x44, 0x20, 0x43},                     /* 1A: VCLK118_25       */
+};
+
+static const struct ast_vbios_stdtable vbios_stdtable[] = {
        /* MD_2_3_400 */
        {
                0x67,
@@ -181,21 +212,21 @@ static struct ast_vbios_stdtable vbios_stdtable[] = {
        },
 };
 
-static struct ast_vbios_enhtable res_640x480[] = {
+static const struct ast_vbios_enhtable res_640x480[] = {
        { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175,  /* 60Hz */
          (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E },
        { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5,   /* 72Hz */
          (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E  },
        { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5,   /* 75Hz */
          (SyncNN | Charx8Dot) , 75, 3, 0x2E },
-       { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,             /* 85Hz */
+       { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,     /* 85Hz */
          (SyncNN | Charx8Dot) , 85, 4, 0x2E },
-       { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,             /* end */
+       { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36,     /* end */
          (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E },
 };
 
-static struct ast_vbios_enhtable res_800x600[] = {
-       {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36,             /* 56Hz */
+static const struct ast_vbios_enhtable res_800x600[] = {
+       {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36,     /* 56Hz */
         (SyncPP | Charx8Dot), 56, 1, 0x30 },
        {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40,    /* 60Hz */
         (SyncPP | Charx8Dot), 60, 2, 0x30 },
@@ -210,7 +241,7 @@ static struct ast_vbios_enhtable res_800x600[] = {
 };
 
 
-static struct ast_vbios_enhtable res_1024x768[] = {
+static const struct ast_vbios_enhtable res_1024x768[] = {
        {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65,   /* 60Hz */
         (SyncNN | Charx8Dot), 60, 1, 0x31 },
        {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75,   /* 70Hz */
@@ -223,7 +254,7 @@ static struct ast_vbios_enhtable res_1024x768[] = {
         (SyncPP | Charx8Dot), 0xFF, 4, 0x31 },
 };
 
-static struct ast_vbios_enhtable res_1280x1024[] = {
+static const struct ast_vbios_enhtable res_1280x1024[] = {
        {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108,        /* 60Hz */
         (SyncPP | Charx8Dot), 60, 1, 0x32 },
        {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135,        /* 75Hz */
@@ -234,7 +265,7 @@ static struct ast_vbios_enhtable res_1280x1024[] = {
         (SyncPP | Charx8Dot), 0xFF, 3, 0x32 },
 };
 
-static struct ast_vbios_enhtable res_1600x1200[] = {
+static const struct ast_vbios_enhtable res_1600x1200[] = {
        {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162,        /* 60Hz */
         (SyncPP | Charx8Dot), 60, 1, 0x33 },
        {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162,        /* end */
@@ -242,34 +273,39 @@ static struct ast_vbios_enhtable res_1600x1200[] = {
 };
 
 /* 16:9 */
-static struct ast_vbios_enhtable res_1360x768[] = {
-       {1792, 1360, 64,112, 795,  768, 3, 6, VCLK85_5,          /* 60Hz */
+static const struct ast_vbios_enhtable res_1360x768[] = {
+       {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,         /* 60Hz */
         (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 },
-       {1792, 1360, 64,112, 795,  768, 3, 6, VCLK85_5,          /* end */
-        (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 },
+       {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5,          /* end */
+        (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 0xFF, 1, 0x39 },
 };
 
-static struct ast_vbios_enhtable res_1600x900[] = {
-       {1760, 1600, 48, 32, 926,  900, 3, 5, VCLK97_75,        /* 60Hz CVT RB */
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A },
-       {2112, 1600, 88,168, 934,  900, 3, 5, VCLK118_25,       /* 60Hz CVT */
+static const struct ast_vbios_enhtable res_1600x900[] = {
+       {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75,         /* 60Hz CVT RB */
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 60, 1, 0x3A },
+       {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,       /* 60Hz CVT */
         (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A },
-       {2112, 1600, 88,168, 934,  900, 3, 5, VCLK118_25,       /* 60Hz CVT */
+       {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25,       /* 60Hz CVT */
         (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A },
 };
 
-static struct ast_vbios_enhtable res_1920x1080[] = {
+static const struct ast_vbios_enhtable res_1920x1080[] = {
        {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,       /* 60Hz */
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 },
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 60, 1, 0x38 },
        {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5,       /* 60Hz */
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 },
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 0xFF, 1, 0x38 },
 };
 
 
 /* 16:10 */
-static struct ast_vbios_enhtable res_1280x800[] = {
-       {1440, 1280, 48, 32,  823,  800, 3, 6, VCLK71,  /* 60Hz RB */
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 },
+static const struct ast_vbios_enhtable res_1280x800[] = {
+       {1440, 1280, 48, 32,  823,  800, 3, 6, VCLK71,          /* 60Hz RB */
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 60, 1, 0x35 },
        {1680, 1280, 72,128,  831,  800, 3, 6, VCLK83_5,        /* 60Hz */
         (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 },
        {1680, 1280, 72,128,  831,  800, 3, 6, VCLK83_5,        /* 60Hz */
@@ -277,29 +313,33 @@ static struct ast_vbios_enhtable res_1280x800[] = {
 
 };
 
-static struct ast_vbios_enhtable res_1440x900[] = {
+static const struct ast_vbios_enhtable res_1440x900[] = {
        {1600, 1440, 48, 32,  926,  900, 3, 6, VCLK88_75,       /* 60Hz RB */
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 60, 1, 0x36 },
        {1904, 1440, 80,152,  934,  900, 3, 6, VCLK106_5,       /* 60Hz */
         (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 },
        {1904, 1440, 80,152,  934,  900, 3, 6, VCLK106_5,       /* 60Hz */
         (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 },
 };
 
-static struct ast_vbios_enhtable res_1680x1050[] = {
-       {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
+static const struct ast_vbios_enhtable res_1680x1050[] = {
+       {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119,         /* 60Hz RB */
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 60, 1, 0x37 },
        {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25,      /* 60Hz */
         (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 },
        {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25,      /* 60Hz */
         (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 },
 };
 
-static struct ast_vbios_enhtable res_1920x1200[] = {
-       {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB*/
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 },
-       {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz RB */
-        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 },
+static const struct ast_vbios_enhtable res_1920x1200[] = {
+       {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,         /* 60Hz RB*/
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 60, 1, 0x34 },
+       {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154,         /* 60Hz RB */
+        (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo |
+         AST2500PreCatchCRT), 0xFF, 1, 0x34 },
 };
 
 #endif