arm64: dts: renesas: r8a7796: Enable IPMMU devices

Remove 'status = "disabled"' to make sure all IPMMU devices are enabled
in DT on the r8a7796 SoC.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index e6254711556cb196f52c586da6d3ca42ec10a165..f33063dd7cd76a51b67735ed42fcfbd3a1c4e7ff 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -881,7 +881,6 @@
                        renesas,ipmmu-main = <&ipmmu_mm 2>;
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
-                       status = "disabled";
                };
 
                ipmmu_ir: mmu@ff8b0000 {
@@ -890,7 +889,6 @@
                        renesas,ipmmu-main = <&ipmmu_mm 3>;
                        power-domains = <&sysc R8A7796_PD_A3IR>;
                        #iommu-cells = <1>;
-                       status = "disabled";
                };
 
                ipmmu_mm: mmu@e67b0000 {
@@ -924,7 +922,6 @@
                        renesas,ipmmu-main = <&ipmmu_mm 6>;
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
-                       status = "disabled";
                };
 
                ipmmu_rt: mmu@ffc80000 {
@@ -933,7 +930,6 @@
                        renesas,ipmmu-main = <&ipmmu_mm 7>;
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                        #iommu-cells = <1>;
-                       status = "disabled";
                };
 
                ipmmu_vc0: mmu@fe6b0000 {
@@ -942,7 +938,6 @@
                        renesas,ipmmu-main = <&ipmmu_mm 8>;
                        power-domains = <&sysc R8A7796_PD_A3VC>;
                        #iommu-cells = <1>;
-                       status = "disabled";
                };
 
                ipmmu_vi0: mmu@febd0000 {