Merge tag 'drm-next-2019-07-19' of git://anongit.freedesktop.org/drm/drm
authorLinus Torvalds <torvalds@linux-foundation.org>
Fri, 19 Jul 2019 19:29:43 +0000 (12:29 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Fri, 19 Jul 2019 19:29:43 +0000 (12:29 -0700)
Pull drm fixes from Daniel Vetter:
 "Dave is back in shape, but now family got it so I'm doing the pull.
  Two things worthy of note:

   - nouveau feature pull was way too late, Dave&me decided to not take
     that, so Ben spun up a pull with just the fixes.

   - after some chatting with the arm display maintainers we decided to
     change a bit how that's maintained, for more oversight/review and
     cross vendor collab.

  More details below:

  nouveau:
   - bugfixes
   - TU116 enabling (minor iteration) :w

  amdgpu:
   - large pile of fixes for new hw support this release (navi, vega20)
   - audio hotplug fix
   - bunch of corner cases and small fixes all over for amdgpu/kfd

  komeda:
   - back out some new properties (from this merge window) that needs
     more pondering.

  bochs:
   - fb pitch setup

  core:
   - a new panel quirk
   - misc fixes"

* tag 'drm-next-2019-07-19' of git://anongit.freedesktop.org/drm/drm: (73 commits)
  drm/nouveau/secboot/gp102-: remove WAR for SEC2 RTOS start bug
  drm/nouveau/flcn/gp102-: improve implementation of bind_context() on SEC2/GSP
  drm/nouveau: fix memory leak in nouveau_conn_reset()
  drm/nouveau/dmem: missing mutex_lock in error path
  drm/nouveau/hwmon: return EINVAL if the GPU is powered down for sensors reads
  drm/nouveau: fix bogus GPL-2 license header
  drm/nouveau: fix bogus GPL-2 license header
  drm/nouveau/i2c: Enable i2c pads & busses during preinit
  drm/nouveau/disp/tu102-: wire up scdc parameter setter
  drm/nouveau/core: recognise TU116 chipset
  drm/nouveau/kms: disallow dual-link harder if hdmi connection detected
  drm/nouveau/disp/nv50-: fix center/aspect-corrected scaling
  drm/nouveau/disp/nv50-: force scaler for any non-default LVDS/eDP modes
  drm/nouveau/mcp89/mmu: Use mcp77_mmu_new instead of g84_mmu_new on MCP89.
  drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq
  drm/amdgpu/pm: remove check for pp funcs in freq sysfs handlers
  drm/amd/display: Force uclk to max for every state
  drm/amdkfd: Remove GWS from process during uninit
  drm/amd/amdgpu: Fix offset for vmid selection in debugfs interface
  drm/amd/powerplay: update vega20 driver if to fit latest SMU firmware
  ...

412 files changed:
MAINTAINERS
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/amdgpu/vi.c
drivers/gpu/drm/amd/amdgpu/vi_dpm.h [deleted file]
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
drivers/gpu/drm/amd/display/Kconfig
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drivers/gpu/drm/amd/display/dc/dc_stream.h
drivers/gpu/drm/amd/display/dc/dcn20/Makefile
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
drivers/gpu/drm/amd/display/dc/dsc/Makefile
drivers/gpu/drm/amd/include/amd_shared.h
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
drivers/gpu/drm/arm/display/komeda/komeda_kms.h
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
drivers/gpu/drm/arm/display/komeda/komeda_plane.c
drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
drivers/gpu/drm/bochs/bochs.h
drivers/gpu/drm/bochs/bochs_hw.c
drivers/gpu/drm/bochs/bochs_kms.c
drivers/gpu/drm/drm_client_modeset.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/drm_modes.c
drivers/gpu/drm/drm_panel_orientation_quirks.c
drivers/gpu/drm/nouveau/Kbuild
drivers/gpu/drm/nouveau/dispnv04/Kbuild
drivers/gpu/drm/nouveau/dispnv04/cursor.c
drivers/gpu/drm/nouveau/dispnv04/disp.h
drivers/gpu/drm/nouveau/dispnv50/Kbuild
drivers/gpu/drm/nouveau/dispnv50/disp.c
drivers/gpu/drm/nouveau/dispnv50/head.c
drivers/gpu/drm/nouveau/include/nvif/cl0002.h
drivers/gpu/drm/nouveau/include/nvif/cl0046.h
drivers/gpu/drm/nouveau/include/nvif/cl006b.h
drivers/gpu/drm/nouveau/include/nvif/cl0080.h
drivers/gpu/drm/nouveau/include/nvif/cl506e.h
drivers/gpu/drm/nouveau/include/nvif/cl506f.h
drivers/gpu/drm/nouveau/include/nvif/cl5070.h
drivers/gpu/drm/nouveau/include/nvif/cl507a.h
drivers/gpu/drm/nouveau/include/nvif/cl507b.h
drivers/gpu/drm/nouveau/include/nvif/cl507c.h
drivers/gpu/drm/nouveau/include/nvif/cl507d.h
drivers/gpu/drm/nouveau/include/nvif/cl507e.h
drivers/gpu/drm/nouveau/include/nvif/cl826e.h
drivers/gpu/drm/nouveau/include/nvif/cl826f.h
drivers/gpu/drm/nouveau/include/nvif/cl906f.h
drivers/gpu/drm/nouveau/include/nvif/cl9097.h
drivers/gpu/drm/nouveau/include/nvif/cla06f.h
drivers/gpu/drm/nouveau/include/nvif/class.h
drivers/gpu/drm/nouveau/include/nvif/clc36f.h
drivers/gpu/drm/nouveau/include/nvif/clc37b.h
drivers/gpu/drm/nouveau/include/nvif/clc37e.h
drivers/gpu/drm/nouveau/include/nvif/client.h
drivers/gpu/drm/nouveau/include/nvif/device.h
drivers/gpu/drm/nouveau/include/nvif/driver.h
drivers/gpu/drm/nouveau/include/nvif/event.h
drivers/gpu/drm/nouveau/include/nvif/if0000.h
drivers/gpu/drm/nouveau/include/nvif/if0001.h
drivers/gpu/drm/nouveau/include/nvif/if0002.h
drivers/gpu/drm/nouveau/include/nvif/if0003.h
drivers/gpu/drm/nouveau/include/nvif/if0004.h
drivers/gpu/drm/nouveau/include/nvif/if0005.h
drivers/gpu/drm/nouveau/include/nvif/ioctl.h
drivers/gpu/drm/nouveau/include/nvif/notify.h
drivers/gpu/drm/nouveau/include/nvif/object.h
drivers/gpu/drm/nouveau/include/nvif/os.h
drivers/gpu/drm/nouveau/include/nvif/unpack.h
drivers/gpu/drm/nouveau/include/nvkm/core/client.h
drivers/gpu/drm/nouveau/include/nvkm/core/debug.h
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
drivers/gpu/drm/nouveau/include/nvkm/core/engine.h
drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
drivers/gpu/drm/nouveau/include/nvkm/core/event.h
drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h
drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h
drivers/gpu/drm/nouveau/include/nvkm/core/ioctl.h
drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
drivers/gpu/drm/nouveau/include/nvkm/core/mm.h
drivers/gpu/drm/nouveau/include/nvkm/core/notify.h
drivers/gpu/drm/nouveau/include/nvkm/core/object.h
drivers/gpu/drm/nouveau/include/nvkm/core/oproxy.h
drivers/gpu/drm/nouveau/include/nvkm/core/option.h
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
drivers/gpu/drm/nouveau/include/nvkm/core/pci.h
drivers/gpu/drm/nouveau/include/nvkm/core/ramht.h
drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h
drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h
drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h
drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
drivers/gpu/drm/nouveau/include/nvkm/engine/mpeg.h
drivers/gpu/drm/nouveau/include/nvkm/engine/msenc.h
drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h
drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h
drivers/gpu/drm/nouveau/include/nvkm/engine/pm.h
drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
drivers/gpu/drm/nouveau/include/nvkm/engine/sw.h
drivers/gpu/drm/nouveau/include/nvkm/engine/vic.h
drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0203.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0205.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/M0209.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/P0260.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bit.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/bmp.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/fan.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/i2c.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/iccsense.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/image.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/mxm.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/npde.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pcir.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/rammap.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/therm.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/timing.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vmap.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/xpio.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/fuse.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/mxm.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h
drivers/gpu/drm/nouveau/nouveau_abi16.h
drivers/gpu/drm/nouveau/nouveau_acpi.c
drivers/gpu/drm/nouveau/nouveau_acpi.h
drivers/gpu/drm/nouveau/nouveau_bo.h
drivers/gpu/drm/nouveau/nouveau_chan.h
drivers/gpu/drm/nouveau/nouveau_connector.c
drivers/gpu/drm/nouveau/nouveau_debugfs.h
drivers/gpu/drm/nouveau/nouveau_display.h
drivers/gpu/drm/nouveau/nouveau_dmem.c
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_fence.h
drivers/gpu/drm/nouveau/nouveau_gem.h
drivers/gpu/drm/nouveau/nouveau_hwmon.c
drivers/gpu/drm/nouveau/nouveau_ioctl.h
drivers/gpu/drm/nouveau/nouveau_reg.h
drivers/gpu/drm/nouveau/nouveau_sgdma.c
drivers/gpu/drm/nouveau/nouveau_ttm.h
drivers/gpu/drm/nouveau/nouveau_usif.h
drivers/gpu/drm/nouveau/nouveau_vga.c
drivers/gpu/drm/nouveau/nouveau_vga.h
drivers/gpu/drm/nouveau/nv10_fence.h
drivers/gpu/drm/nouveau/nvif/Kbuild
drivers/gpu/drm/nouveau/nvkm/Kbuild
drivers/gpu/drm/nouveau/nvkm/core/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gf100.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/gt215.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.h
drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/head.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c
drivers/gpu/drm/nouveau/nvkm/engine/dma/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/dma/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/dma/user.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/os.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.h
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/msenc/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/pm/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.h
drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/g98.fuc0s.h
drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/sw/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.h
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.h
drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.h
drivers/gpu/drm/nouveau/nvkm/engine/sw/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/vic/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/vp/Kbuild
drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild
drivers/gpu/drm/nouveau/nvkm/falcon/priv.h
drivers/gpu/drm/nouveau/nvkm/falcon/v1.c
drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h
drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/bus/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
drivers/gpu/drm/nouveau/nvkm/subdev/bus/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.h
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/fault/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/gpio/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.h
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.h
drivers/gpu/drm/nouveau/nvkm/subdev/mxm/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.h
drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gt215.fuc3.h
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/os.h
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c
drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h
drivers/gpu/drm/nouveau/nvkm/subdev/top/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/top/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h
drivers/gpu/drm/selftests/test-drm_cmdline_parser.c
include/drm/drm_modes.h
include/uapi/drm/amdgpu_drm.h

index a99adee5471a1a7a1e2041740c3f0b0165a55796..a63d465d3e2db16cd872bda73387a2a59d436f2e 100644 (file)
@@ -1236,7 +1236,7 @@ M:        James (Qian) Wang <james.qian.wang@arm.com>
 M:     Liviu Dudau <liviu.dudau@arm.com>
 L:     Mali DP Maintainers <malidp@foss.arm.com>
 S:     Supported
-T:     git git://linux-arm.org/linux-ld.git for-upstream/mali-dp
+T:     git git://anongit.freedesktop.org/drm/drm-misc
 F:     drivers/gpu/drm/arm/display/include/
 F:     drivers/gpu/drm/arm/display/komeda/
 F:     Documentation/devicetree/bindings/display/arm,komeda.txt
@@ -1247,7 +1247,7 @@ M:        Liviu Dudau <liviu.dudau@arm.com>
 M:     Brian Starkey <brian.starkey@arm.com>
 L:     Mali DP Maintainers <malidp@foss.arm.com>
 S:     Supported
-T:     git git://linux-arm.org/linux-ld.git for-upstream/mali-dp
+T:     git git://anongit.freedesktop.org/drm/drm-misc
 F:     drivers/gpu/drm/arm/
 F:     Documentation/devicetree/bindings/display/arm,malidp.txt
 F:     Documentation/gpu/afbc.rst
index f88d8141447c81e1f69f4a536ba04a47e25931b3..8199d201b43a477a8460f63452a5494ca403b554 100644 (file)
@@ -164,6 +164,7 @@ extern int amdgpu_async_gfx_ring;
 extern int amdgpu_mcbp;
 extern int amdgpu_discovery;
 extern int amdgpu_mes;
+extern int amdgpu_noretry;
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
index 20ce158490db258a487d37e616bdc1046c51bbf3..6d54decef7f8156d0a20883151dab0af1c90d6de 100644 (file)
@@ -106,10 +106,10 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
        ssize_t result = 0;
        int r;
        bool pm_pg_lock, use_bank, use_ring;
-       unsigned instance_bank, sh_bank, se_bank, me, pipe, queue;
+       unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
 
        pm_pg_lock = use_bank = use_ring = false;
-       instance_bank = sh_bank = se_bank = me = pipe = queue = 0;
+       instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
 
        if (size & 0x3 || *pos & 0x3 ||
                        ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
@@ -135,6 +135,7 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
                me = (*pos & GENMASK_ULL(33, 24)) >> 24;
                pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
                queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
+               vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
 
                use_ring = 1;
        } else {
@@ -152,7 +153,7 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
                                        sh_bank, instance_bank);
        } else if (use_ring) {
                mutex_lock(&adev->srbm_mutex);
-               amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue);
+               amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
        }
 
        if (pm_pg_lock)
@@ -185,7 +186,7 @@ end:
                amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
                mutex_unlock(&adev->grbm_idx_mutex);
        } else if (use_ring) {
-               amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0);
+               amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
        }
 
index 7401bc95c15be39b0e797394114d282371e9d68b..5a7f893cf72448d9a4d6e9c12b0d3827d3e7bdcb 100644 (file)
@@ -2537,6 +2537,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
        hash_init(adev->mn_hash);
        mutex_init(&adev->lock_reset);
        mutex_init(&adev->virt.dpm_mutex);
+       mutex_init(&adev->psp.mutex);
 
        r = amdgpu_device_check_arguments(adev);
        if (r)
index e049ae6a76fbdb8ad46eda79977e6eb29df95169..1481899f86c166ed25c0639c80031ec2b9fdea90 100644 (file)
@@ -123,7 +123,7 @@ static int hw_id_map[MAX_HWIP] = {
        [UVD_HWIP]      = UVD_HWID,
        [VCE_HWIP]      = VCE_HWID,
        [DF_HWIP]       = DF_HWID,
-       [DCE_HWIP]      = DCEAZ_HWID,
+       [DCE_HWIP]      = DMU_HWID,
        [OSSSYS_HWIP]   = OSSSYS_HWID,
        [SMUIO_HWIP]    = SMUIO_HWID,
        [PWR_HWIP]      = PWR_HWID,
index 1b0613c7cf9564d3694a88f5e7e0d830a3bc4188..f2e8b4238efd49d6efac87b9e2d06801a94aca06 100644 (file)
@@ -140,8 +140,9 @@ uint amdgpu_smu_memory_pool_size = 0;
 uint amdgpu_dc_feature_mask = 0;
 int amdgpu_async_gfx_ring = 1;
 int amdgpu_mcbp = 0;
-int amdgpu_discovery = 0;
+int amdgpu_discovery = -1;
 int amdgpu_mes = 0;
+int amdgpu_noretry;
 
 struct amdgpu_mgpu_info mgpu_info = {
        .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -593,6 +594,7 @@ module_param_named(mcbp, amdgpu_mcbp, int, 0444);
 /**
  * DOC: discovery (int)
  * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
+ * (-1 = auto (default), 0 = disabled, 1 = enabled)
  */
 MODULE_PARM_DESC(discovery,
        "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
@@ -607,6 +609,10 @@ MODULE_PARM_DESC(mes,
        "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
 module_param_named(mes, amdgpu_mes, int, 0444);
 
+MODULE_PARM_DESC(noretry,
+       "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");
+module_param_named(noretry, amdgpu_noretry, int, 0644);
+
 #ifdef CONFIG_HSA_AMD
 /**
  * DOC: sched_policy (int)
@@ -682,17 +688,6 @@ module_param(ignore_crat, int, 0444);
 MODULE_PARM_DESC(ignore_crat,
        "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
 
-/**
- * DOC: noretry (int)
- * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry.
- * Setting 1 disables retry.
- * Retry is needed for recoverable page faults.
- */
-int noretry;
-module_param(noretry, int, 0644);
-MODULE_PARM_DESC(noretry,
-       "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)");
-
 /**
  * DOC: halt_if_hws_hang (int)
  * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
index f96407ba977066ae4626bfe82f2c420e0d52955e..1199b5828b90964f69059ebedef7e5b7e7de4f91 100644 (file)
@@ -195,7 +195,7 @@ struct amdgpu_gfx_funcs {
                                uint32_t wave, uint32_t start, uint32_t size,
                                uint32_t *dst);
        void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
-                                u32 queue);
+                                u32 queue, u32 vmid);
 };
 
 struct amdgpu_ngg_buf {
@@ -327,7 +327,7 @@ struct amdgpu_gfx {
 
 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
-#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
+#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
 
 /**
  * amdgpu_gfx_create_bitmask - create a bitmask
index 193d53720d9baeca7800e376bed88d9cc2273542..8b7efd0a70280a486160ccce13ec736adaccc33c 100644 (file)
@@ -2077,11 +2077,6 @@ static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
                return -EINVAL;
 
-       /* sanity check PP is enabled */
-       if (!(adev->powerplay.pp_funcs &&
-             adev->powerplay.pp_funcs->read_sensor))
-             return -EINVAL;
-
        /* get the sclk */
        r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
                                   (void *)&sclk, &size);
@@ -2112,11 +2107,6 @@ static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
                return -EINVAL;
 
-       /* sanity check PP is enabled */
-       if (!(adev->powerplay.pp_funcs &&
-             adev->powerplay.pp_funcs->read_sensor))
-             return -EINVAL;
-
        /* get the sclk */
        r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
                                   (void *)&mclk, &size);
@@ -2996,13 +2986,10 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
        }
 
        if (is_support_sw_smu(adev)) {
-               struct smu_context *smu = &adev->smu;
                struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
-               mutex_lock(&(smu->mutex));
                smu_handle_task(&adev->smu,
                                smu_dpm->dpm_level,
                                AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
-               mutex_unlock(&(smu->mutex));
        } else {
                if (adev->powerplay.pp_funcs->dispatch_tasks) {
                        if (!amdgpu_device_has_dc_support(adev)) {
index e69ad6e089c5b7b6dc0878a7ff8d0a504418a934..c027e5e7713ef821297d78127e035fff8e3732d8 100644 (file)
@@ -130,6 +130,8 @@ psp_cmd_submit_buf(struct psp_context *psp,
        int index;
        int timeout = 2000;
 
+       mutex_lock(&psp->mutex);
+
        memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 
        memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
@@ -139,6 +141,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
                             fence_mc_addr, index);
        if (ret) {
                atomic_dec(&psp->fence_value);
+               mutex_unlock(&psp->mutex);
                return ret;
        }
 
@@ -161,8 +164,10 @@ psp_cmd_submit_buf(struct psp_context *psp,
                                  ucode->ucode_id);
                DRM_WARN("psp command failed and response status is (%d)\n",
                          psp->cmd_buf_mem->resp.status);
-               if (!timeout)
+               if (!timeout) {
+                       mutex_unlock(&psp->mutex);
                        return -EINVAL;
+               }
        }
 
        /* get xGMI session id from response buffer */
@@ -172,6 +177,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
                ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
                ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
        }
+       mutex_unlock(&psp->mutex);
 
        return ret;
 }
@@ -763,6 +769,15 @@ static int psp_hw_start(struct psp_context *psp)
        int ret;
 
        if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
+               if (psp->kdb_bin_size &&
+                   (psp->funcs->bootloader_load_kdb != NULL)) {
+                       ret = psp_bootloader_load_kdb(psp);
+                       if (ret) {
+                               DRM_ERROR("PSP load kdb failed!\n");
+                               return ret;
+                       }
+               }
+
                ret = psp_bootloader_load_sysdrv(psp);
                if (ret) {
                        DRM_ERROR("PSP load sysdrv failed!\n");
@@ -1188,10 +1203,16 @@ failed:
 
 int psp_gpu_reset(struct amdgpu_device *adev)
 {
+       int ret;
+
        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
                return 0;
 
-       return psp_mode1_reset(&adev->psp);
+       mutex_lock(&adev->psp.mutex);
+       ret = psp_mode1_reset(&adev->psp);
+       mutex_unlock(&adev->psp.mutex);
+
+       return ret;
 }
 
 int psp_rlc_autoload_start(struct psp_context *psp)
index 6039acc84346956553d54d14b901c862260306ed..e0fc2a790e5309489c7abac52729be13b359b66c 100644 (file)
@@ -42,6 +42,12 @@ struct psp_context;
 struct psp_xgmi_node_info;
 struct psp_xgmi_topology_info;
 
+enum psp_bootloader_cmd {
+       PSP_BL__LOAD_SYSDRV             = 0x10000,
+       PSP_BL__LOAD_SOSDRV             = 0x20000,
+       PSP_BL__LOAD_KEY_DATABASE       = 0x80000,
+};
+
 enum psp_ring_type
 {
        PSP_RING_TYPE__INVALID = 0,
@@ -73,6 +79,7 @@ enum psp_reg_prog_id {
 struct psp_funcs
 {
        int (*init_microcode)(struct psp_context *psp);
+       int (*bootloader_load_kdb)(struct psp_context *psp);
        int (*bootloader_load_sysdrv)(struct psp_context *psp);
        int (*bootloader_load_sos)(struct psp_context *psp);
        int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
@@ -156,9 +163,11 @@ struct psp_context
        uint32_t                        sys_bin_size;
        uint32_t                        sos_bin_size;
        uint32_t                        toc_bin_size;
+       uint32_t                        kdb_bin_size;
        uint8_t                         *sys_start_addr;
        uint8_t                         *sos_start_addr;
        uint8_t                         *toc_start_addr;
+       uint8_t                         *kdb_start_addr;
 
        /* tmr buffer */
        struct amdgpu_bo                *tmr_bo;
@@ -201,6 +210,7 @@ struct psp_context
        uint8_t                         *ta_ras_start_addr;
        struct psp_xgmi_context         xgmi_context;
        struct psp_ras_context          ras;
+       struct mutex                    mutex;
 };
 
 struct amdgpu_psp_funcs {
@@ -219,6 +229,8 @@ struct amdgpu_psp_funcs {
                (psp)->funcs->compare_sram_data((psp), (ucode), (type))
 #define psp_init_microcode(psp) \
                ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
+#define psp_bootloader_load_kdb(psp) \
+               ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
 #define psp_bootloader_load_sysdrv(psp) \
                ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
 #define psp_bootloader_load_sos(psp) \
index 5c05644b9b96a802d6c2699b4af631e85ea0e7a2..e51b48ac48eb151fcf72d11a4bdf15b9a06dda0e 100644 (file)
@@ -391,6 +391,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
                        src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
                                                             src->mem);
                        src_node_size = (src_mm->size << PAGE_SHIFT);
+                       src_page_offset = 0;
                } else {
                        src_node_start += cur_size;
                        src_page_offset = src_node_start & (PAGE_SIZE - 1);
@@ -400,6 +401,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
                        dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
                                                             dst->mem);
                        dst_node_size = (dst_mm->size << PAGE_SHIFT);
+                       dst_page_offset = 0;
                } else {
                        dst_node_start += cur_size;
                        dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
@@ -487,6 +489,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
        placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
        r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
        if (unlikely(r)) {
+               pr_err("Failed to find GTT space for blit from VRAM\n");
                return r;
        }
 
@@ -545,6 +548,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
        placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
        r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
        if (unlikely(r)) {
+               pr_err("Failed to find GTT space for blit to VRAM\n");
                return r;
        }
 
@@ -564,6 +568,30 @@ out_cleanup:
        return r;
 }
 
+/**
+ * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
+ *
+ * Called by amdgpu_bo_move()
+ */
+static bool amdgpu_mem_visible(struct amdgpu_device *adev,
+                              struct ttm_mem_reg *mem)
+{
+       struct drm_mm_node *nodes = mem->mm_node;
+
+       if (mem->mem_type == TTM_PL_SYSTEM ||
+           mem->mem_type == TTM_PL_TT)
+               return true;
+       if (mem->mem_type != TTM_PL_VRAM)
+               return false;
+
+       /* ttm_mem_reg_ioremap only supports contiguous memory */
+       if (nodes->size != mem->num_pages)
+               return false;
+
+       return ((nodes->start + nodes->size) << PAGE_SHIFT)
+               <= adev->gmc.visible_vram_size;
+}
+
 /**
  * amdgpu_bo_move - Move a buffer object to a new memory location
  *
@@ -608,8 +636,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
                return 0;
        }
 
-       if (!adev->mman.buffer_funcs_enabled)
+       if (!adev->mman.buffer_funcs_enabled) {
+               r = -ENODEV;
                goto memcpy;
+       }
 
        if (old_mem->mem_type == TTM_PL_VRAM &&
            new_mem->mem_type == TTM_PL_SYSTEM) {
@@ -624,10 +654,16 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 
        if (r) {
 memcpy:
-               r = ttm_bo_move_memcpy(bo, ctx, new_mem);
-               if (r) {
+               /* Check that all memory is CPU accessible */
+               if (!amdgpu_mem_visible(adev, old_mem) ||
+                   !amdgpu_mem_visible(adev, new_mem)) {
+                       pr_err("Move buffer fallback to memcpy unavailable\n");
                        return r;
                }
+
+               r = ttm_bo_move_memcpy(bo, ctx, new_mem);
+               if (r)
+                       return r;
        }
 
        if (bo->type == ttm_bo_type_device &&
@@ -2059,9 +2095,9 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
        mm_node = bo->tbo.mem.mm_node;
        num_loops = 0;
        while (num_pages) {
-               uint32_t byte_count = mm_node->size << PAGE_SHIFT;
+               uint64_t byte_count = mm_node->size << PAGE_SHIFT;
 
-               num_loops += DIV_ROUND_UP(byte_count, max_bytes);
+               num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
                num_pages -= mm_node->size;
                ++mm_node;
        }
@@ -2087,12 +2123,13 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
        mm_node = bo->tbo.mem.mm_node;
 
        while (num_pages) {
-               uint32_t byte_count = mm_node->size << PAGE_SHIFT;
+               uint64_t byte_count = mm_node->size << PAGE_SHIFT;
                uint64_t dst_addr;
 
                dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
                while (byte_count) {
-                       uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
+                       uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
+                                                          max_bytes);
 
                        amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
                                                dst_addr, cur_size_in_bytes);
index c352a519ddd4f365081fc5ea1c1479a570db54e5..bfaa0eac3213fa93a137d60464c90a32bc6db8d6 100644 (file)
@@ -262,6 +262,12 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
                                  le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
                        DRM_DEBUG("toc_size_bytes: %u\n",
                                  le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
+                       DRM_DEBUG("kdb_header_version: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
+                       DRM_DEBUG("kdb_offset_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
+                       DRM_DEBUG("kdb_size_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
                }
        } else {
                DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
index f46944453c6eafbbe4940f46690f7dda7c02b1b9..c1fb6dc86440d880593e9554d301dbacffe5274c 100644 (file)
@@ -85,6 +85,9 @@ struct psp_firmware_header_v1_1 {
        uint32_t toc_header_version;
        uint32_t toc_offset_bytes;
        uint32_t toc_size_bytes;
+       uint32_t kdb_header_version;
+       uint32_t kdb_offset_bytes;
+       uint32_t kdb_size_bytes;
 };
 
 /* version_major=1, version_minor=0 */
index 07a7e3820b7ba6006d1cb381c91b0e3ceaab302a..59dd204498c52dff4bc1d1e62ecefa34e419d87f 100644 (file)
@@ -390,7 +390,8 @@ static uint32_t parse_clk(char *buf, bool min)
                 if (!ptr)
                         break;
                 ptr+=2;
-                clk = simple_strtoul(ptr, NULL, 10);
+               if (kstrtou32(ptr, 10, &clk))
+                       return 0;
         } while (!min);
 
         return clk * 100;
index ee41d5592c5113fb515ee21f59585b41cd8f2c07..1675d5837c3c8b0995585b79ba26c443d2629c54 100644 (file)
@@ -109,6 +109,13 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
        /* Pending on emulation bring up */
 };
 
+#define DEFAULT_SH_MEM_CONFIG \
+       ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
+        (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
+        (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
+        (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
+
+
 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
@@ -995,6 +1002,12 @@ static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
                start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 }
 
+static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
+                                                                         u32 me, u32 pipe, u32 q, u32 vm)
+ {
+       nv_grbm_select(adev, me, pipe, q, vm);
+ }
+
 
 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
        .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
@@ -1002,6 +1015,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
        .read_wave_data = &gfx_v10_0_read_wave_data,
        .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
        .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
+       .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
 };
 
 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
@@ -1408,7 +1422,6 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
 {
        int i;
-       uint32_t sh_mem_config;
        uint32_t sh_mem_bases;
 
        /*
@@ -1419,15 +1432,11 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
         */
        sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
 
-       sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
-                       SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
-                       SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
-
        mutex_lock(&adev->srbm_mutex);
        for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
                nv_grbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
-               WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+               WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
                WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
        }
        nv_grbm_select(adev, 0, 0, 0, 0);
@@ -1520,17 +1529,8 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
        for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
                nv_grbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
-               if (i == 0) {
-                       tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
-                                           SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-                       tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_MODE, 0);
-                       WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
-                       WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
-               } else {
-                       tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
-                                           SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-                       tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_MODE, 0);
-                       WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
+               WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
+               if (i != 0) {
                        tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
                                (adev->gmc.private_aperture_start >> 48));
                        tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
index 789e900905e913557be92496f6071fe7c8969ef2..7f0a63628c43a72956fb2efd24cd077917690419 100644 (file)
@@ -3043,7 +3043,7 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
 }
 
 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
-                                 u32 me, u32 pipe, u32 q)
+                                 u32 me, u32 pipe, u32 q, u32 vm)
 {
        DRM_INFO("Not implemented\n");
 }
index 341b5024e598241f1f3d879102aadf23889c1027..0db9f488da7eb4a0db8672cb88ab4d16a0c5a20f 100644 (file)
@@ -4169,9 +4169,9 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
 }
 
 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
-                                 u32 me, u32 pipe, u32 q)
+                                 u32 me, u32 pipe, u32 q, u32 vm)
 {
-       cik_srbm_select(adev, me, pipe, q, 0);
+       cik_srbm_select(adev, me, pipe, q, vm);
 }
 
 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
index 032e76dbc51f9872dcd9a697e7404f376717cb26..5f401b41ef7ce67cf6aefcc59010ca4d090e1db5 100644 (file)
@@ -3436,9 +3436,9 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
 }
 
 static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
-                                 u32 me, u32 pipe, u32 q)
+                                 u32 me, u32 pipe, u32 q, u32 vm)
 {
-       vi_srbm_select(adev, me, pipe, q, 0);
+       vi_srbm_select(adev, me, pipe, q, vm);
 }
 
 static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
index 5ba3323767108d1c8885267334af64c98c3b04b3..f4c4eea625268045795cb0dbfc892d2be823aacc 100644 (file)
@@ -1313,9 +1313,9 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
 }
 
 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
-                                 u32 me, u32 pipe, u32 q)
+                                 u32 me, u32 pipe, u32 q, u32 vm)
 {
-       soc15_grbm_select(adev, me, pipe, q, 0);
+       soc15_grbm_select(adev, me, pipe, q, vm);
 }
 
 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
@@ -1942,11 +1942,15 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
                if (i == 0) {
                        tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
                                            SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+                       tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
+                                           !!amdgpu_noretry);
                        WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
                        WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
                } else {
                        tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
                                            SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+                       tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
+                                           !!amdgpu_noretry);
                        WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
                        tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
                                (adev->gmc.private_aperture_start >> 48));
index 9f0f189fc111c849617b6070b0c97781051d3ed8..15986748f59fa6d2393aa653ea9bd0758999bc8e 100644 (file)
@@ -236,7 +236,8 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
                                    block_size);
                /* Send no-retry XNACK on fault to suppress VM fault storm. */
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
-                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1);
+                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+                                   !amdgpu_noretry);
                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
index b7de60a156232c182793cd19d45c8c0232308e85..d605b4963f8aca31b308470b6d910cd1eaa4055e 100644 (file)
@@ -215,7 +215,8 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
                                adev->vm_manager.block_size - 9);
                /* Send no-retry XNACK on fault to suppress VM fault storm. */
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
-                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+                                   !amdgpu_noretry);
                WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);
                WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
index 05d1d448c8f5c177be5dbdd71d1b9bbe3e39345b..dc5ce03034d35bc5c491f029574e37ea38338edf 100644 (file)
@@ -265,7 +265,8 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
                                    block_size);
                /* Send no-retry XNACK on fault to suppress VM fault storm. */
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
-                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 1);
+                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+                                   !amdgpu_noretry);
                WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
                WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
                WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
index 37a1a318ae63b5fc9919a81b9e43dd5465a8d972..0f9549f19ade230d1a650e44990689afb19f1f5c 100644 (file)
@@ -205,7 +205,8 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
                                    adev->vm_manager.block_size - 9);
                /* Send no-retry XNACK on fault to suppress VM fault storm. */
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
-                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+                                   RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+                                   !amdgpu_noretry);
                WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i, tmp);
                WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
                WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
index ad430cbcd72fcd8e57e654690a086ca3a89c5c12..662612f89c70b5f2990a111aa740d350541a7127 100644 (file)
@@ -392,8 +392,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 #if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
                        amdgpu_device_ip_block_add(adev, &dm_ip_block);
-#else
-#      warning "Enable CONFIG_DRM_AMD_DC for display support on navi."
 #endif
                amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
                amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
index 61744e2d16fbc5cb82a4b44ddfb45d72f5840ac1..41b72588adcf50bcecbcf79a51fca15b23ff0b46 100644 (file)
@@ -103,6 +103,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
                        adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
                        adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
                                        le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
+                       adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
+                       adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
+                                       le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
                }
                break;
        default:
@@ -177,6 +180,48 @@ out:
        return err;
 }
 
+static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
+{
+       int ret;
+       uint32_t psp_gfxdrv_command_reg = 0;
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t sol_reg;
+
+       /* Check tOS sign of life register to confirm sys driver and sOS
+        * are already been loaded.
+        */
+       sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+       if (sol_reg) {
+               psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+               dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
+               return 0;
+       }
+
+       /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+       if (ret)
+               return ret;
+
+       memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+
+       /* Copy PSP KDB binary to memory */
+       memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size);
+
+       /* Provide the sys driver to bootloader */
+       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
+              (uint32_t)(psp->fw_pri_mc_addr >> 20));
+       psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE;
+       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
+              psp_gfxdrv_command_reg);
+
+       /* Wait for bootloader to signify that is ready having  bit 31 of C2PMSG_35 set to 1*/
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+
+       return ret;
+}
+
 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
 {
        int ret;
@@ -190,7 +235,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
        if (sol_reg) {
                psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
-               printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
+               dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version);
                return 0;
        }
 
@@ -208,7 +253,7 @@ static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
        /* Provide the sys driver to bootloader */
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
               (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 1 << 16;
+       psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
               psp_gfxdrv_command_reg);
 
@@ -249,7 +294,7 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
        /* Provide the PSP secure OS to bootloader */
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
               (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 2 << 16;
+       psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
               psp_gfxdrv_command_reg);
 
@@ -822,6 +867,7 @@ static int psp_v11_0_rlc_autoload_start(struct psp_context *psp)
 
 static const struct psp_funcs psp_v11_0_funcs = {
        .init_microcode = psp_v11_0_init_microcode,
+       .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
        .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
        .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
        .ring_init = psp_v11_0_ring_init,
index 2ea77269203728bbec3438bf85579bb5995c45a0..019c47feee42f2d0a2f8c699b993d4f5bea679bf 100644 (file)
@@ -155,7 +155,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
        /* Provide the sys driver to bootloader */
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
               (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 1 << 16;
+       psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
               psp_gfxdrv_command_reg);
 
@@ -218,7 +218,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
        /* Provide the PSP secure OS to bootloader */
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
               (uint32_t)(psp->fw_pri_mc_addr >> 20));
-       psp_gfxdrv_command_reg = 2 << 16;
+       psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
               psp_gfxdrv_command_reg);
 
index 87152d8ef0df8735522272bb324c4b0ae2b607e4..23265414d44867b81c36d85f1ef87e67013ca95f 100644 (file)
@@ -649,8 +649,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 #if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
                        amdgpu_device_ip_block_add(adev, &dm_ip_block);
-#else
-#      warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 #endif
                if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
                        amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
@@ -671,8 +669,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 #if defined(CONFIG_DRM_AMD_DC)
                else if (amdgpu_device_has_dc_support(adev))
                        amdgpu_device_ip_block_add(adev, &dm_ip_block);
-#else
-#      warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
 #endif
                amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
                break;
@@ -717,9 +713,15 @@ static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
                return;
 
        /* Set the 2 events that we wish to watch, defined above */
-       /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
+       /* Reg 40 is # received msgs */
        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
-       perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+       /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
+       if (adev->asic_type == CHIP_VEGA20)
+               perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
+                                       EVENT1_SEL, 108);
+       else
+               perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
+                                       EVENT1_SEL, 104);
 
        /* Write to enable desired perf counters */
        WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
index d40ed1a828dda2f0d0536e66cef00af045371894..6575ddcfcf00c3e8381d675bcf138b708853575f 100644 (file)
@@ -59,7 +59,6 @@
 
 #include "vid.h"
 #include "vi.h"
-#include "vi_dpm.h"
 #include "gmc_v8_0.h"
 #include "gmc_v7_0.h"
 #include "gfx_v8_0.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/vi_dpm.h b/drivers/gpu/drm/amd/amdgpu/vi_dpm.h
deleted file mode 100644 (file)
index c43e03f..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __VI_DPM_H__
-#define __VI_DPM_H__
-
-extern const struct amd_ip_funcs cz_dpm_ip_funcs;
-int cz_smu_init(struct amdgpu_device *adev);
-int cz_smu_start(struct amdgpu_device *adev);
-int cz_smu_fini(struct amdgpu_device *adev);
-
-#endif
index 584748c23f14a68da105b563bccf83ce4011f09d..e6a4288bfaa6ab5824ca672653875c49144be803 100644 (file)
@@ -1157,12 +1157,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
 
        mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
                        q->properties.type)];
-       /*
-        * Eviction state logic: mark all queues as evicted, even ones
-        * not currently active. Restoring inactive queues later only
-        * updates the is_evicted flag but is a no-op otherwise.
-        */
-       q->properties.is_evicted = !!qpd->evicted;
+
        if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
                q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
                dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
@@ -1173,9 +1168,16 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
                retval = -ENOMEM;
                goto out_deallocate_doorbell;
        }
+
+       dqm_lock(dqm);
+       /*
+        * Eviction state logic: mark all queues as evicted, even ones
+        * not currently active. Restoring inactive queues later only
+        * updates the is_evicted flag but is a no-op otherwise.
+        */
+       q->properties.is_evicted = !!qpd->evicted;
        mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
                                &q->gart_mqd_addr, &q->properties);
-       dqm_lock(dqm);
 
        list_add(&q->list, &qpd->queues_list);
        qpd->queue_count++;
index e9fe393823716d6d4c98e2fff9d8201756efde16..95a82ac455f2ba1609426ecc797231d865b77ec5 100644 (file)
@@ -61,7 +61,7 @@ static int update_qpd_v9(struct device_queue_manager *dqm,
                qpd->sh_mem_config =
                                SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
                                        SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
-               if (noretry &&
+               if (amdgpu_noretry &&
                    !dqm->dev->device_info->needs_iommu_device)
                        qpd->sh_mem_config |=
                                1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
index 08a0feb9d0a03579048a7f13ba04d8853bce12f4..3933fb6a371efb706073bbf0d183727d3f421581 100644 (file)
@@ -157,7 +157,7 @@ extern int ignore_crat;
 /*
  * Set sh_mem_config.retry_disable on Vega10
  */
-extern int noretry;
+extern int amdgpu_noretry;
 
 /*
  * Halt if HWS hang is detected
index da09586258617914a7fc8a7683feb57651d9f98f..7e6c3ee82f5b233ef3730b78896f10e8c2a92166 100644 (file)
@@ -150,6 +150,9 @@ void pqm_uninit(struct process_queue_manager *pqm)
        struct process_queue_node *pqn, *next;
 
        list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
+               if (pqn->q && pqn->q->gws)
+                       amdgpu_amdkfd_remove_gws_from_process(pqm->process->kgd_process_info,
+                               pqn->q->gws);
                uninit_queue(pqn->q);
                list_del(&pqn->process_queue_list);
                kfree(pqn);
index 7073cfcf04e858c8f1ad5bde51188a8eec7abae0..f954bf61af28a7d4208bf519d1f6b4f3ffb50492 100644 (file)
@@ -5,6 +5,7 @@ menu "Display Engine Configuration"
 config DRM_AMD_DC
        bool "AMD DC - Enable new display engine"
        default y
+       select SND_HDA_COMPONENT if SND_HDA_CORE
        select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
        help
          Choose this option if you want to use the new display engine
index 0242d693f4f6e94239f723e13cc622866540d4b5..4a29f72334d0fa88d738a93f5bd3778c30a81615 100644 (file)
@@ -56,6 +56,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/pci.h>
 #include <linux/firmware.h>
+#include <linux/component.h>
 
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_uapi.h>
@@ -65,6 +66,7 @@
 #include <drm/drm_fourcc.h>
 #include <drm/drm_edid.h>
 #include <drm/drm_vblank.h>
+#include <drm/drm_audio_component.h>
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
@@ -508,6 +510,139 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 
 }
 
+static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
+                                         int pipe, bool *enabled,
+                                         unsigned char *buf, int max_bytes)
+{
+       struct drm_device *dev = dev_get_drvdata(kdev);
+       struct amdgpu_device *adev = dev->dev_private;
+       struct drm_connector *connector;
+       struct drm_connector_list_iter conn_iter;
+       struct amdgpu_dm_connector *aconnector;
+       int ret = 0;
+
+       *enabled = false;
+
+       mutex_lock(&adev->dm.audio_lock);
+
+       drm_connector_list_iter_begin(dev, &conn_iter);
+       drm_for_each_connector_iter(connector, &conn_iter) {
+               aconnector = to_amdgpu_dm_connector(connector);
+               if (aconnector->audio_inst != port)
+                       continue;
+
+               *enabled = true;
+               ret = drm_eld_size(connector->eld);
+               memcpy(buf, connector->eld, min(max_bytes, ret));
+
+               break;
+       }
+       drm_connector_list_iter_end(&conn_iter);
+
+       mutex_unlock(&adev->dm.audio_lock);
+
+       DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
+
+       return ret;
+}
+
+static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
+       .get_eld = amdgpu_dm_audio_component_get_eld,
+};
+
+static int amdgpu_dm_audio_component_bind(struct device *kdev,
+                                      struct device *hda_kdev, void *data)
+{
+       struct drm_device *dev = dev_get_drvdata(kdev);
+       struct amdgpu_device *adev = dev->dev_private;
+       struct drm_audio_component *acomp = data;
+
+       acomp->ops = &amdgpu_dm_audio_component_ops;
+       acomp->dev = kdev;
+       adev->dm.audio_component = acomp;
+
+       return 0;
+}
+
+static void amdgpu_dm_audio_component_unbind(struct device *kdev,
+                                         struct device *hda_kdev, void *data)
+{
+       struct drm_device *dev = dev_get_drvdata(kdev);
+       struct amdgpu_device *adev = dev->dev_private;
+       struct drm_audio_component *acomp = data;
+
+       acomp->ops = NULL;
+       acomp->dev = NULL;
+       adev->dm.audio_component = NULL;
+}
+
+static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
+       .bind   = amdgpu_dm_audio_component_bind,
+       .unbind = amdgpu_dm_audio_component_unbind,
+};
+
+static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
+{
+       int i, ret;
+
+       if (!amdgpu_audio)
+               return 0;
+
+       adev->mode_info.audio.enabled = true;
+
+       adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
+
+       for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
+               adev->mode_info.audio.pin[i].channels = -1;
+               adev->mode_info.audio.pin[i].rate = -1;
+               adev->mode_info.audio.pin[i].bits_per_sample = -1;
+               adev->mode_info.audio.pin[i].status_bits = 0;
+               adev->mode_info.audio.pin[i].category_code = 0;
+               adev->mode_info.audio.pin[i].connected = false;
+               adev->mode_info.audio.pin[i].id =
+                       adev->dm.dc->res_pool->audios[i]->inst;
+               adev->mode_info.audio.pin[i].offset = 0;
+       }
+
+       ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
+       if (ret < 0)
+               return ret;
+
+       adev->dm.audio_registered = true;
+
+       return 0;
+}
+
+static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
+{
+       if (!amdgpu_audio)
+               return;
+
+       if (!adev->mode_info.audio.enabled)
+               return;
+
+       if (adev->dm.audio_registered) {
+               component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
+               adev->dm.audio_registered = false;
+       }
+
+       /* TODO: Disable audio? */
+
+       adev->mode_info.audio.enabled = false;
+}
+
+void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
+{
+       struct drm_audio_component *acomp = adev->dm.audio_component;
+
+       if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
+               DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
+
+               acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
+                                                pin, -1);
+       }
+}
+
 static int amdgpu_dm_init(struct amdgpu_device *adev)
 {
        struct dc_init_data init_data;
@@ -518,6 +653,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
        memset(&init_data, 0, sizeof(init_data));
 
        mutex_init(&adev->dm.dc_lock);
+       mutex_init(&adev->dm.audio_lock);
 
        if(amdgpu_dm_irq_init(adev)) {
                DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
@@ -621,6 +757,8 @@ error:
 
 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 {
+       amdgpu_dm_audio_fini(adev);
+
        amdgpu_dm_destroy_drm_device(&adev->dm);
 
        /* DC Destroy TODO: Replace destroy DAL */
@@ -641,6 +779,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
                adev->dm.freesync_module = NULL;
        }
 
+       mutex_destroy(&adev->dm.audio_lock);
        mutex_destroy(&adev->dm.dc_lock);
 
        return;
@@ -1888,6 +2027,10 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
        if (r)
                return r;
 
+       r = amdgpu_dm_audio_init(adev);
+       if (r)
+               return r;
+
        return 0;
 }
 
@@ -4834,6 +4977,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
        aconnector->base.stereo_allowed = false;
        aconnector->base.dpms = DRM_MODE_DPMS_OFF;
        aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
+       aconnector->audio_inst = -1;
        mutex_init(&aconnector->hpd_lock);
 
        /*
@@ -5728,6 +5872,81 @@ cleanup:
        kfree(bundle);
 }
 
+static void amdgpu_dm_commit_audio(struct drm_device *dev,
+                                  struct drm_atomic_state *state)
+{
+       struct amdgpu_device *adev = dev->dev_private;
+       struct amdgpu_dm_connector *aconnector;
+       struct drm_connector *connector;
+       struct drm_connector_state *old_con_state, *new_con_state;
+       struct drm_crtc_state *new_crtc_state;
+       struct dm_crtc_state *new_dm_crtc_state;
+       const struct dc_stream_status *status;
+       int i, inst;
+
+       /* Notify device removals. */
+       for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
+               if (old_con_state->crtc != new_con_state->crtc) {
+                       /* CRTC changes require notification. */
+                       goto notify;
+               }
+
+               if (!new_con_state->crtc)
+                       continue;
+
+               new_crtc_state = drm_atomic_get_new_crtc_state(
+                       state, new_con_state->crtc);
+
+               if (!new_crtc_state)
+                       continue;
+
+               if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+                       continue;
+
+       notify:
+               aconnector = to_amdgpu_dm_connector(connector);
+
+               mutex_lock(&adev->dm.audio_lock);
+               inst = aconnector->audio_inst;
+               aconnector->audio_inst = -1;
+               mutex_unlock(&adev->dm.audio_lock);
+
+               amdgpu_dm_audio_eld_notify(adev, inst);
+       }
+
+       /* Notify audio device additions. */
+       for_each_new_connector_in_state(state, connector, new_con_state, i) {
+               if (!new_con_state->crtc)
+                       continue;
+
+               new_crtc_state = drm_atomic_get_new_crtc_state(
+                       state, new_con_state->crtc);
+
+               if (!new_crtc_state)
+                       continue;
+
+               if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+                       continue;
+
+               new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
+               if (!new_dm_crtc_state->stream)
+                       continue;
+
+               status = dc_stream_get_status(new_dm_crtc_state->stream);
+               if (!status)
+                       continue;
+
+               aconnector = to_amdgpu_dm_connector(connector);
+
+               mutex_lock(&adev->dm.audio_lock);
+               inst = status->audio_inst;
+               aconnector->audio_inst = inst;
+               mutex_unlock(&adev->dm.audio_lock);
+
+               amdgpu_dm_audio_eld_notify(adev, inst);
+       }
+}
+
 /*
  * Enable interrupts on CRTCs that are newly active, undergone
  * a modeset, or have active planes again.
@@ -6106,6 +6325,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
        /* Enable interrupts for CRTCs going from 0 to n active planes. */
        amdgpu_dm_enable_crtc_interrupts(dev, state, false);
 
+       /* Update audio instances for each connector. */
+       amdgpu_dm_commit_audio(dev, state);
+
        /*
         * send vblank event on all events not handled in flip and
         * mark consumed event for drm_atomic_helper_commit_hw_done
index baca5dc22b92c4a8cf070f3a84661c61627fb15b..b89cbbfcc0e9f91bd590ae7cc3ca543a4f743267 100644 (file)
@@ -143,6 +143,28 @@ struct amdgpu_display_manager {
         */
        struct mutex dc_lock;
 
+       /**
+        * @audio_lock:
+        *
+        * Guards access to audio instance changes.
+        */
+       struct mutex audio_lock;
+
+       /**
+        * @audio_component:
+        *
+        * Used to notify ELD changes to sound driver.
+        */
+       struct drm_audio_component *audio_component;
+
+       /**
+        * @audio_registered:
+        *
+        * True if the audio component has been registered
+        * successfully, false otherwise.
+        */
+       bool audio_registered;
+
        /**
         * @irq_handler_list_low_tab:
         *
@@ -254,6 +276,9 @@ struct amdgpu_dm_connector {
        int max_vfreq ;
        int pixel_clock_mhz;
 
+       /* Audio instance - protected by audio_lock. */
+       int audio_inst;
+
        struct mutex hpd_lock;
 
        bool fake_enable;
index eac09bfe3be2fa789961e7b0eb5997f231ab631d..592fa499c9f86f3ff6780dd9c7eafeb1554509e9 100644 (file)
@@ -308,7 +308,8 @@ static void pp_to_dc_clock_levels_with_voltage(
                        DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
        for (i = 0; i < clk_level_info->num_levels; i++) {
-               DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
+               DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
+                        pp_clks->data[i].voltage_in_mv);
                clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
                clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
        }
@@ -910,11 +911,11 @@ void dm_pp_get_funcs(
                /* todo set_pme_wa_enable cause 4k@6ohz display not light up */
                funcs->nv_funcs.set_pme_wa_enable = NULL;
                /* todo debug waring message */
-               funcs->nv_funcs.set_hard_min_uclk_by_freq = NULL;
+               funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
                /* todo  compare data with window driver*/
-               funcs->nv_funcs.get_maximum_sustainable_clocks = NULL;
+               funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
                /*todo  compare data with window driver */
-               funcs->nv_funcs.get_uclk_dpm_states = NULL;
+               funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
                break;
 #endif
        default:
index 173fcfb5abe610dff5127bc333b800466ca445ca..51a78283a86da510837ce3ab3b6d3ae6bc1801bd 100644 (file)
@@ -175,32 +175,22 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
        if (res_pool != NULL) {
                struct dc_firmware_info fw_info = { { 0 } };
 
-               if (dc->ctx->dc_bios->funcs->get_firmware_info(
-                               dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
-                               res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
-
-                               if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-                                       // On FPGA these dividers are currently not configured by GDB
-                                       res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                       res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                               } else if (res_pool->dccg && res_pool->hubbub) {
-                                       // If DCCG reference frequency cannot be determined (usually means not set to xtalin) then this is a critical error
-                                       // as this value must be known for DCHUB programming
-                                       (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
-                                                       fw_info.pll_info.crystal_frequency,
-                                                       &res_pool->ref_clocks.dccg_ref_clock_inKhz);
-
-                                       // Similarly, if DCHUB reference frequency cannot be determined, then it is also a critical error
-                                       (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
-                                                       res_pool->ref_clocks.dccg_ref_clock_inKhz,
-                                                       &res_pool->ref_clocks.dchub_ref_clock_inKhz);
-                               } else {
-                                       // Not all ASICs have DCCG sw component
-                                       res_pool->ref_clocks.dccg_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                                       res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz;
-                               }
-                       } else
-                               ASSERT_CRITICAL(false);
+               if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
+                               &fw_info) == BP_RESULT_OK) {
+                       res_pool->ref_clocks.xtalin_clock_inKhz =
+                               fw_info.pll_info.crystal_frequency;
+                       /* initialize with firmware data first, no all
+                        * ASIC have DCCG SW component. FPGA or
+                        * simulation need initialization of
+                        * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
+                        * with xtalin_clock_inKhz
+                        */
+                       res_pool->ref_clocks.dccg_ref_clock_inKhz =
+                               res_pool->ref_clocks.xtalin_clock_inKhz;
+                       res_pool->ref_clocks.dchub_ref_clock_inKhz =
+                               res_pool->ref_clocks.xtalin_clock_inKhz;
+               } else
+                       ASSERT_CRITICAL(false);
        }
 
        return res_pool;
@@ -2011,6 +2001,9 @@ enum dc_status resource_map_pool_resources(
                if (context->streams[i] == stream) {
                        context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
                        context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
+                       context->stream_status[i].audio_inst =
+                               pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
+
                        return DC_OK;
                }
 
index e253a5c591f604f00e8bf35b21b6113fb6fe93e9..0fa1c26bc20db4faad5a29d4aaf568a8533403fe 100644 (file)
@@ -42,6 +42,7 @@ struct dc_stream_status {
        int primary_otg_inst;
        int stream_enc_inst;
        int plane_count;
+       int audio_inst;
        struct timing_sync_info timing_sync_info;
        struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
 };
index 1b68de27ba74f83dee4eee05bf7b45cd5b34203e..e9721a906592d757b3750759fd6344c694c7fe14 100644 (file)
@@ -10,7 +10,13 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 DCN20 += dcn20_dsc.o
 endif
 
-CFLAGS_dcn20_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
+ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+       cc_stack_align := -mpreferred-stack-boundary=4
+else ifneq ($(call cc-option, -mstack-alignment=16),)
+       cc_stack_align := -mstack-alignment=16
+endif
+
+CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
 
 AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
 
index 6925d25d24573cfc96297b4584b3ca2d5f098526..0b84a322b8a2c01af95de8aad35765338e9e5d28 100644 (file)
@@ -523,6 +523,7 @@ static void dcn20_init_hw(struct dc *dc)
        struct dc_bios *dcb = dc->ctx->dc_bios;
        struct resource_pool *res_pool = dc->res_pool;
        struct dc_state  *context = dc->current_state;
+       struct dc_firmware_info fw_info = { { 0 } };
 
        if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
                dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -546,6 +547,30 @@ static void dcn20_init_hw(struct dc *dc)
        } else {
                if (!dcb->funcs->is_accelerated_mode(dcb)) {
                        bios_golden_init(dc);
+                       if (dc->ctx->dc_bios->funcs->get_firmware_info(
+                                       dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
+                               res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
+
+                               if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+                                       if (res_pool->dccg && res_pool->hubbub) {
+
+                                               (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+                                                               fw_info.pll_info.crystal_frequency,
+                                                               &res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+                                               (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+                                                               res_pool->ref_clocks.dccg_ref_clock_inKhz,
+                                                               &res_pool->ref_clocks.dchub_ref_clock_inKhz);
+                                       } else {
+                                               // Not all ASICs have DCCG sw component
+                                               res_pool->ref_clocks.dccg_ref_clock_inKhz =
+                                                               res_pool->ref_clocks.xtalin_clock_inKhz;
+                                               res_pool->ref_clocks.dchub_ref_clock_inKhz =
+                                                               res_pool->ref_clocks.xtalin_clock_inKhz;
+                                       }
+                               }
+                       } else
+                               ASSERT_CRITICAL(false);
                        disable_vga(dc->hwseq);
                }
 
index 4e52df82c9936597d22df67b537a8da4a9d6f016..d200bc3cec714c22f6389e65bec4c56df6d4ad50 100644 (file)
@@ -2415,7 +2415,7 @@ struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
                ASSERT(0);
 
        if (!idle_pipe)
-               return false;
+               return NULL;
 
        idle_pipe->stream = head_pipe->stream;
        idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
@@ -2576,6 +2576,9 @@ static void cap_soc_clocks(
                                                && max_clocks.uClockInKhz != 0)
                        bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
 
+               // HACK: Force every uclk to max for now to "disable" uclk switching.
+               bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
+
                if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
                                                && max_clocks.fabricClockInKhz != 0)
                        bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
@@ -2783,6 +2786,8 @@ static bool init_soc_bounding_box(struct dc *dc,
                                le32_to_cpu(bb->vmm_page_size_bytes);
                dcn2_0_soc.dram_clock_change_latency_us =
                                fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
+               // HACK!! Lower uclock latency switch time so we don't switch
+               dcn2_0_soc.dram_clock_change_latency_us = 10;
                dcn2_0_soc.writeback_dram_clock_change_latency_us =
                                fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
                dcn2_0_soc.return_bus_width_bytes =
@@ -2824,6 +2829,7 @@ static bool init_soc_bounding_box(struct dc *dc,
                struct pp_smu_nv_clock_table max_clocks = {0};
                unsigned int uclk_states[8] = {0};
                unsigned int num_states = 0;
+               int i;
                enum pp_smu_status status;
                bool clock_limits_available = false;
                bool uclk_states_available = false;
@@ -2845,6 +2851,10 @@ static bool init_soc_bounding_box(struct dc *dc,
                        clock_limits_available = (status == PP_SMU_RESULT_OK);
                }
 
+               // HACK: Use the max uclk_states value for all elements.
+               for (i = 0; i < num_states; i++)
+                       uclk_states[i] = uclk_states[num_states - 1];
+
                if (clock_limits_available && uclk_states_available && num_states)
                        update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
                else if (clock_limits_available)
index c5d5b94e2604c2c181aae10a25fa51df66ff66ac..e019cd9447e8db48f3bdc8a3ba61a7df32f212df 100644 (file)
@@ -1,10 +1,18 @@
 #
 # Makefile for the 'dsc' sub-component of DAL.
 
-CFLAGS_rc_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
-CFLAGS_rc_calc_dpi.o := -mhard-float -msse -mpreferred-stack-boundary=4
-CFLAGS_codec_main_amd.o := -mhard-float -msse -mpreferred-stack-boundary=4
-CFLAGS_dc_dsc.o := -mhard-float -msse -mpreferred-stack-boundary=4
+ifneq ($(call cc-option, -mpreferred-stack-boundary=4),)
+       cc_stack_align := -mpreferred-stack-boundary=4
+else ifneq ($(call cc-option, -mstack-alignment=16),)
+       cc_stack_align := -mstack-alignment=16
+endif
+
+dsc_ccflags := -mhard-float -msse $(cc_stack_align)
+
+CFLAGS_rc_calc.o := $(dsc_ccflags)
+CFLAGS_rc_calc_dpi.o := $(dsc_ccflags)
+CFLAGS_codec_main_amd.o := $(dsc_ccflags)
+CFLAGS_dc_dsc.o := $(dsc_ccflags)
 
 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
 
index d352b8d7636510178fee0b48967c4b98e1cf1b3d..a0a7211438f226a171eb71cfb1754c575707af92 100644 (file)
@@ -26,7 +26,7 @@
 #include <drm/amd_asic_type.h>
 
 
-#define AMD_MAX_USEC_TIMEOUT           200000  /* 200 ms */
+#define AMD_MAX_USEC_TIMEOUT           1000000  /* 1000 ms */
 
 /*
  * Chip flags
index 3093917adc2d3b278d4d2662240017620c926548..f1565c448de5169812d4aa5e289ae10b7b2b7508 100644 (file)
@@ -69,6 +69,9 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
        if (min <= 0 && max <= 0)
                return -EINVAL;
 
+       if (!smu_clk_dpm_is_enabled(smu, clk_type))
+               return 0;
+
        clk_id = smu_clk_get_index(smu, clk_type);
        if (clk_id < 0)
                return clk_id;
@@ -102,6 +105,9 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
        if (min <= 0 && max <= 0)
                return -EINVAL;
 
+       if (!smu_clk_dpm_is_enabled(smu, clk_type))
+               return 0;
+
        clk_id = smu_clk_get_index(smu, clk_type);
        if (clk_id < 0)
                return clk_id;
@@ -135,23 +141,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
        if (!min && !max)
                return -EINVAL;
 
-       switch (clk_type) {
-       case SMU_UCLK:
-               if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
-                       pr_warn("uclk dpm is not enabled\n");
-                       return 0;
-               }
-               break;
-       case SMU_GFXCLK:
-       case SMU_SCLK:
-               if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
-                       pr_warn("gfxclk dpm is not enabled\n");
-                       return 0;
-               }
-               break;
-       default:
-               break;
-       }
+       if (!smu_clk_dpm_is_enabled(smu, clk_type))
+               return 0;
 
        mutex_lock(&smu->mutex);
        clk_id = smu_clk_get_index(smu, clk_type);
@@ -194,6 +185,9 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
        if (!value)
                return -EINVAL;
 
+       if (!smu_clk_dpm_is_enabled(smu, clk_type))
+               return 0;
+
        clk_id = smu_clk_get_index(smu, clk_type);
        if (clk_id < 0)
                return clk_id;
@@ -222,6 +216,35 @@ int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
        return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 }
 
+bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
+{
+       enum smu_feature_mask feature_id = 0;
+
+       switch (clk_type) {
+       case SMU_MCLK:
+       case SMU_UCLK:
+               feature_id = SMU_FEATURE_DPM_UCLK_BIT;
+               break;
+       case SMU_GFXCLK:
+       case SMU_SCLK:
+               feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
+               break;
+       case SMU_SOCCLK:
+               feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
+               break;
+       default:
+               return true;
+       }
+
+       if(!smu_feature_is_enabled(smu, feature_id)) {
+               pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, feature_id);
+               return false;
+       }
+
+       return true;
+}
+
+
 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
                           bool gate)
 {
@@ -300,7 +323,7 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
        return ret;
 }
 
-int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
+int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
                     void *table_data, bool drv2smu)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
@@ -327,7 +350,7 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index,
        ret = smu_send_smc_msg_with_param(smu, drv2smu ?
                                          SMU_MSG_TransferTableDram2Smu :
                                          SMU_MSG_TransferTableSmu2Dram,
-                                         table_id);
+                                         table_id | ((argument & 0xFFFF) << 16));
        if (ret)
                return ret;
 
@@ -1372,10 +1395,10 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
                        break;
 
                case AMD_DPM_FORCED_LEVEL_AUTO:
+               case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
                        ret = smu_unforce_dpm_levels(smu);
                        break;
 
-               case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
                case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
                case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
                case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
@@ -1385,8 +1408,9 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
                                                         &soc_mask);
                        if (ret)
                                return ret;
-                       smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
-                       smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
+                       smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
+                       smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+                       smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
                        break;
 
                case AMD_DPM_FORCED_LEVEL_MANUAL:
@@ -1441,17 +1465,16 @@ int smu_handle_task(struct smu_context *smu,
 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
 {
        struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+       enum amd_dpm_forced_level level;
 
        if (!smu_dpm_ctx->dpm_context)
                return -EINVAL;
 
        mutex_lock(&(smu->mutex));
-       if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
-               smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
-       }
+       level = smu_dpm_ctx->dpm_level;
        mutex_unlock(&(smu->mutex));
 
-       return smu_dpm_ctx->dpm_level;
+       return level;
 }
 
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
index 1cd5a8b5cdc179a30d231cdd1079fec8b410373f..b760f95e7fa7adb850e99117c45b94452d277068 100644 (file)
@@ -1067,8 +1067,6 @@ static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
        PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
                            "Failed to allocate hwmgr->pptable!", return -ENOMEM);
 
-       memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information));
-
        powerplay_table = get_powerplay_table(hwmgr);
 
        PP_ASSERT_WITH_CODE((NULL != powerplay_table),
index c97324ef7db241b7c15c30fbf42e06561bace4c2..1af992fb0bdedce0f4d89d0059a334a510d92a00 100644 (file)
@@ -937,7 +937,7 @@ extern int smu_feature_is_supported(struct smu_context *smu,
 extern int smu_feature_set_supported(struct smu_context *smu,
                                     enum smu_feature_mask mask, bool enable);
 
-int smu_update_table(struct smu_context *smu, uint32_t table_index,
+int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
                     void *table_data, bool drv2smu);
 
 bool is_support_sw_smu(struct amdgpu_device *adev);
@@ -973,5 +973,6 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
+bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
 
 #endif
index 195c4ae67058554d1d2bf194cedf9762f79a96e3..755d51f9c6a9fb6f967b7f4ebb8418777fd4a01c 100644 (file)
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if
 // any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x12
+#define SMU11_DRIVER_IF_VERSION 0x13
 
 #define PPTABLE_V20_SMU_VERSION 3
 
@@ -615,6 +615,7 @@ typedef struct {
   uint16_t     UclkAverageLpfTau;
   uint16_t     GfxActivityLpfTau;
   uint16_t     UclkActivityLpfTau;
+  uint16_t     SocketPowerLpfTau;
 
 
   uint32_t     MmHubPadding[8];
@@ -665,7 +666,8 @@ typedef struct {
   uint32_t ThrottlerStatus       ;
 
   uint8_t  LinkDpmLevel;
-  uint8_t  Padding[3];
+  uint16_t AverageSocketPower;
+  uint8_t  Padding;
 
 
   uint32_t     MmHubPadding[7];
index 880fe0930d9e42dd26d61b7c38b3faee369b477f..2dae0ae0829ef0de9df11e83f2e692eb54ad0868 100644 (file)
@@ -331,7 +331,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
                                | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
                                | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
                                | FEATURE_MASK(FEATURE_BACO_BIT)
-                               | FEATURE_MASK(FEATURE_ACDC_BIT);
+                               | FEATURE_MASK(FEATURE_ACDC_BIT)
+                               | FEATURE_MASK(FEATURE_GFX_SS_BIT)
+                               | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
+                               | FEATURE_MASK(FEATURE_FW_CTF_BIT);
 
        if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
@@ -339,8 +342,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
                                | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 
        if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
-               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
-                               | FEATURE_MASK(FEATURE_GFXOFF_BIT);
+               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
                /* TODO: remove it once fw fix the bug */
                *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
        }
@@ -465,9 +467,6 @@ static int navi10_append_powerplay_table(struct smu_context *smu)
        smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 
        if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
-               *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
-                                       | FEATURE_MASK(FEATURE_GFXOFF_BIT);
-
                /* TODO: remove it once SMU fw fix it */
                smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
        }
@@ -614,7 +613,7 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 
        memset(&metrics, 0, sizeof(metrics));
 
-       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
+       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
        if (ret)
                return ret;
 
@@ -709,7 +708,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 {
        int ret = 0;
-       uint32_t min_sclk_freq = 0;
+       uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 
        ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
        if (ret)
@@ -717,6 +716,12 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
 
        smu->pstate_sclk = min_sclk_freq * 100;
 
+       ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
+       if (ret)
+               return ret;
+
+       smu->pstate_mclk = min_mclk_freq * 100;
+
        return ret;
 }
 
@@ -827,27 +832,20 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
        return ret;
 }
 
-static int navi10_unforce_dpm_levels(struct smu_context *smu) {
-
+static int navi10_unforce_dpm_levels(struct smu_context *smu)
+{
        int ret = 0, i = 0;
        uint32_t min_freq, max_freq;
        enum smu_clk_type clk_type;
 
-       struct clk_feature_map {
-               enum smu_clk_type clk_type;
-               uint32_t        feature;
-       } clk_feature_map[] = {
-               {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
-               {SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
-               {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
+       enum smu_clk_type clks[] = {
+               SMU_GFXCLK,
+               SMU_MCLK,
+               SMU_SOCCLK,
        };
 
-       for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
-               if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
-                       continue;
-
-               clk_type = clk_feature_map[i].clk_type;
-
+       for (i = 0; i < ARRAY_SIZE(clks); i++) {
+               clk_type = clks[i];
                ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
                if (ret)
                        return ret;
@@ -868,7 +866,7 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
        if (!value)
                return -EINVAL;
 
-       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics,
+       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
                               false);
        if (ret)
                return ret;
@@ -890,7 +888,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu,
 
        msleep(1);
 
-       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
+       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
                               (void *)&metrics, false);
        if (ret)
                return ret;
@@ -931,7 +929,7 @@ static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
 
        memset(&metrics, 0, sizeof(metrics));
 
-       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
+       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
                               (void *)&metrics, false);
        if (ret)
                return ret;
@@ -997,7 +995,7 @@ static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
                /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
                workload_type = smu_workload_get_type(smu, i);
                result = smu_update_table(smu,
-                                         SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
+                                         SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
                                          (void *)(&activity_monitor), false);
                if (result) {
                        pr_err("[%s] Failed to get activity monitor!", __func__);
@@ -1070,7 +1068,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
                        return -EINVAL;
 
                ret = smu_update_table(smu,
-                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
+                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
                                       (void *)(&activity_monitor), false);
                if (ret) {
                        pr_err("[%s] Failed to get activity monitor!", __func__);
@@ -1114,7 +1112,7 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
                }
 
                ret = smu_update_table(smu,
-                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
+                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
                                       (void *)(&activity_monitor), true);
                if (ret) {
                        pr_err("[%s] Failed to set activity monitor!", __func__);
@@ -1157,14 +1155,14 @@ static int navi10_get_profiling_clk_mask(struct smu_context *smu,
                        ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
                        if (ret)
                                return ret;
-                       *sclk_mask = level_count - 1;
+                       *mclk_mask = level_count - 1;
                }
 
                if(soc_mask) {
                        ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
                        if (ret)
                                return ret;
-                       *sclk_mask = level_count - 1;
+                       *soc_mask = level_count - 1;
                }
        }
 
@@ -1280,7 +1278,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu,
        if (!value)
                return -EINVAL;
 
-       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *)&metrics, false);
+       ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
        if (ret)
                return ret;
 
index a87b86ae2cc5605ece331ffbb1776019eae87f8b..95c7c4dae5236cdc61323502c414a346fdca2473 100644 (file)
@@ -261,14 +261,20 @@ static int smu_v11_0_check_fw_version(struct smu_context *smu)
        smu_minor = (smu_version >> 8) & 0xff;
        smu_debug = (smu_version >> 0) & 0xff;
 
-
+       /*
+        * 1. if_version mismatch is not critical as our fw is designed
+        * to be backward compatible.
+        * 2. New fw usually brings some optimizations. But that's visible
+        * only on the paired driver.
+        * Considering above, we just leave user a warning message instead
+        * of halt driver loading.
+        */
        if (if_version != smu->smc_if_version) {
                pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
                        "smu fw version = 0x%08x (%d.%d.%d)\n",
                        smu->smc_if_version, if_version,
                        smu_version, smu_major, smu_minor, smu_debug);
-               pr_err("SMU driver if version not matched\n");
-               ret = -EINVAL;
+               pr_warn("SMU driver if version not matched\n");
        }
 
        return ret;
@@ -703,7 +709,7 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
        struct smu_table_context *table_context = &smu->smu_table;
        int ret = 0;
 
-       ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
+       ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
                               table_context->driver_pptable, true);
 
        return ret;
@@ -722,7 +728,7 @@ static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
        if (!table->cpu_addr)
                return -EINVAL;
 
-       ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
+       ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
                                true);
 
        return ret;
index 6c81cb91ebae87209c7616fd21f0347907a82855..15590fd86ef4ac5d3fb4a36c8a2467c61ad9390e 100644 (file)
@@ -2705,8 +2705,6 @@ static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
        cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
        cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
 
-       memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-
        result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
 
        if (0 == result)
index 9e0dd56fe7c50d3d3a74d8b72d5bd0b03a6050de..732005c03a82d89f7528ee067ea93c3f259d7195 100644 (file)
@@ -2634,8 +2634,6 @@ static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
        cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
        cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
 
-       memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-
        result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
 
        if (0 == result)
index ba3394303b9c2812bc58e0baa5cd763a65248c6d..f19bac7ef7ba6cfa15dc906a65c1124c605d91f2 100644 (file)
@@ -3117,8 +3117,6 @@ static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
        cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
                        cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
 
-       memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-
        result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
 
        if (!result)
index a76a22a18eb451ad60a900a5a99f31a33ee336a0..bb9bb09cfc7a2fc779e261aae0d8366d19c4557a 100644 (file)
@@ -319,7 +319,7 @@ static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
                       AMDGPU_GEM_DOMAIN_VRAM);
 
        smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
-       if (smu_table->metrics_table)
+       if (!smu_table->metrics_table)
                return -ENOMEM;
        smu_table->metrics_time = 0;
 
@@ -441,7 +441,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
 {
        ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
        struct smu_table_context *table_context = &smu->smu_table;
-       int ret;
 
        if (!table_context->power_play_table)
                return -EINVAL;
@@ -455,9 +454,7 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
        table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
        table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
 
-       ret = vega20_setup_od8_information(smu);
-
-       return ret;
+       return 0;
 }
 
 static int vega20_append_powerplay_table(struct smu_context *smu)
@@ -992,7 +989,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
                break;
 
        case SMU_SOCCLK:
-               ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now);
+               ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
                if (ret) {
                        pr_err("Attempt to get current socclk Failed!");
                        return ret;
@@ -1013,7 +1010,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
                break;
 
        case SMU_FCLK:
-               ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now);
+               ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
                if (ret) {
                        pr_err("Attempt to get current fclk Failed!");
                        return ret;
@@ -1028,7 +1025,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
                break;
 
        case SMU_DCEFCLK:
-               ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now);
+               ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
                if (ret) {
                        pr_err("Attempt to get current dcefclk Failed!");
                        return ret;
@@ -1502,11 +1499,17 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu)
 
        od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
 
-       if (od8_settings)
+       if (!od8_settings)
                return -ENOMEM;
 
        smu->od_settings = (void *)od8_settings;
 
+       ret = vega20_setup_od8_information(smu);
+       if (ret) {
+               pr_err("Retrieve board OD limits failed!\n");
+               return ret;
+       }
+
        if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
                if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
                    od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
@@ -1677,7 +1680,7 @@ static int vega20_get_metrics_table(struct smu_context *smu,
        int ret = 0;
 
        if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
-               ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
+               ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
                                (void *)smu_table->metrics_table, false);
                if (ret) {
                        pr_info("Failed to export SMU metrics table!\n");
@@ -1706,7 +1709,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu,
                if (!table_context->overdrive_table)
                        return -ENOMEM;
 
-               ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
+               ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
                                       table_context->overdrive_table, false);
                if (ret) {
                        pr_err("Failed to export over drive table!\n");
@@ -1718,7 +1721,7 @@ static int vega20_set_default_od_settings(struct smu_context *smu,
                        return ret;
        }
 
-       ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
+       ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
                               table_context->overdrive_table, true);
        if (ret) {
                pr_err("Failed to import over drive table!\n");
@@ -1802,7 +1805,7 @@ static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
                /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
                workload_type = smu_workload_get_type(smu, i);
                result = smu_update_table(smu,
-                                         SMU_TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
+                                         SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
                                          (void *)(&activity_monitor), false);
                if (result) {
                        pr_err("[%s] Failed to get activity monitor!", __func__);
@@ -1888,7 +1891,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
 
        if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
                ret = smu_update_table(smu,
-                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
+                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
                                       (void *)(&activity_monitor), false);
                if (ret) {
                        pr_err("[%s] Failed to get activity monitor!", __func__);
@@ -1943,7 +1946,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
                }
 
                ret = smu_update_table(smu,
-                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF | WORKLOAD_PPLIB_CUSTOM_BIT << 16,
+                                      SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
                                       (void *)(&activity_monitor), true);
                if (ret) {
                        pr_err("[%s] Failed to set activity monitor!", __func__);
@@ -2492,7 +2495,7 @@ static int vega20_update_od8_settings(struct smu_context *smu,
        struct smu_table_context *table_context = &smu->smu_table;
        int ret;
 
-       ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
+       ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
                               table_context->overdrive_table, false);
        if (ret) {
                pr_err("Failed to export over drive table!\n");
@@ -2503,7 +2506,7 @@ static int vega20_update_od8_settings(struct smu_context *smu,
        if (ret)
                return ret;
 
-       ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
+       ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0,
                               table_context->overdrive_table, true);
        if (ret) {
                pr_err("Failed to import over drive table!\n");
@@ -2767,7 +2770,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
                break;
 
        case PP_OD_RESTORE_DEFAULT_TABLE:
-               ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, false);
+               ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
                if (ret) {
                        pr_err("Failed to export over drive table!\n");
                        return ret;
@@ -2776,7 +2779,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context *smu,
                break;
 
        case PP_OD_COMMIT_DPM_TABLE:
-               ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, table_context->overdrive_table, true);
+               ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
                if (ret) {
                        pr_err("Failed to import over drive table!\n");
                        return ret;
index 3f222f464eb2f2d15b37f52488cb8aadd0cea5f5..f4400788ab945af3329b0c08e98e894bcb26186c 100644 (file)
@@ -454,24 +454,6 @@ static void komeda_crtc_vblank_disable(struct drm_crtc *crtc)
        mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, false);
 }
 
-static int
-komeda_crtc_atomic_get_property(struct drm_crtc *crtc,
-                               const struct drm_crtc_state *state,
-                               struct drm_property *property, uint64_t *val)
-{
-       struct komeda_crtc *kcrtc = to_kcrtc(crtc);
-       struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(state);
-
-       if (property == kcrtc->clock_ratio_property) {
-               *val = kcrtc_st->clock_ratio;
-       } else {
-               DRM_DEBUG_DRIVER("Unknown property %s\n", property->name);
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
 static const struct drm_crtc_funcs komeda_crtc_funcs = {
        .gamma_set              = drm_atomic_helper_legacy_gamma_set,
        .destroy                = drm_crtc_cleanup,
@@ -482,7 +464,6 @@ static const struct drm_crtc_funcs komeda_crtc_funcs = {
        .atomic_destroy_state   = komeda_crtc_atomic_destroy_state,
        .enable_vblank          = komeda_crtc_vblank_enable,
        .disable_vblank         = komeda_crtc_vblank_disable,
-       .atomic_get_property    = komeda_crtc_atomic_get_property,
 };
 
 int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
@@ -518,42 +499,6 @@ int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
        return 0;
 }
 
-static int komeda_crtc_create_clock_ratio_property(struct komeda_crtc *kcrtc)
-{
-       struct drm_crtc *crtc = &kcrtc->base;
-       struct drm_property *prop;
-
-       prop = drm_property_create_range(crtc->dev, DRM_MODE_PROP_ATOMIC,
-                                        "CLOCK_RATIO", 0, U64_MAX);
-       if (!prop)
-               return -ENOMEM;
-
-       drm_object_attach_property(&crtc->base, prop, 0);
-       kcrtc->clock_ratio_property = prop;
-
-       return 0;
-}
-
-static int komeda_crtc_create_slave_planes_property(struct komeda_crtc *kcrtc)
-{
-       struct drm_crtc *crtc = &kcrtc->base;
-       struct drm_property *prop;
-
-       if (kcrtc->slave_planes == 0)
-               return 0;
-
-       prop = drm_property_create_range(crtc->dev, DRM_MODE_PROP_IMMUTABLE,
-                                        "slave_planes", 0, U32_MAX);
-       if (!prop)
-               return -ENOMEM;
-
-       drm_object_attach_property(&crtc->base, prop, kcrtc->slave_planes);
-
-       kcrtc->slave_planes_property = prop;
-
-       return 0;
-}
-
 static struct drm_plane *
 get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc)
 {
@@ -590,14 +535,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms,
 
        crtc->port = kcrtc->master->of_output_port;
 
-       err = komeda_crtc_create_clock_ratio_property(kcrtc);
-       if (err)
-               return err;
-
-       err = komeda_crtc_create_slave_planes_property(kcrtc);
-       if (err)
-               return err;
-
        return err;
 }
 
index 219fa3f0c3363636a465c40da3227447e1616cd8..8c89fc245b83f3315140418b57ec0d3c7887dc34 100644 (file)
@@ -33,11 +33,6 @@ struct komeda_plane {
         * Layers with same capabilities.
         */
        struct komeda_layer *layer;
-
-       /** @prop_img_enhancement: for on/off image enhancement */
-       struct drm_property *prop_img_enhancement;
-       /** @prop_layer_split: for on/off layer_split */
-       struct drm_property *prop_layer_split;
 };
 
 /**
@@ -52,11 +47,8 @@ struct komeda_plane_state {
        /** @zlist_node: zorder list node */
        struct list_head zlist_node;
 
-       /* @img_enhancement: on/off image enhancement
-        * @layer_split: on/off layer_split
-        */
-       u8 img_enhancement : 1,
-          layer_split : 1;
+       /** @layer_split: on/off layer_split */
+       u8 layer_split : 1;
 };
 
 /**
@@ -94,12 +86,6 @@ struct komeda_crtc {
 
        /** @disable_done: this flip_done is for tracing the disable */
        struct completion *disable_done;
-
-       /** @clock_ratio_property: property for ratio of (aclk << 32)/pxlclk */
-       struct drm_property *clock_ratio_property;
-
-       /** @slave_planes_property: property for slaves of the planes */
-       struct drm_property *slave_planes_property;
 };
 
 /**
index fc1b8613385e93b98ee0844f045d323a342a6d74..a90bcbb3cb23d6fc71a76750d69da9c1324cb098 100644 (file)
@@ -537,7 +537,8 @@ void komeda_pipeline_disable(struct komeda_pipeline *pipe,
 void komeda_pipeline_update(struct komeda_pipeline *pipe,
                            struct drm_atomic_state *old_state);
 
-void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
+void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
+                                  struct komeda_data_flow_cfg *dflow,
                                   struct drm_framebuffer *fb);
 
 #endif /* _KOMEDA_PIPELINE_H_*/
index 2b415ef2b7d368701abd82f944bff41fbe18a0da..950235af1e79852fa372f249d7f546d4b40c71c6 100644 (file)
@@ -784,9 +784,11 @@ komeda_timing_ctrlr_validate(struct komeda_timing_ctrlr *ctrlr,
        return 0;
 }
 
-void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
+void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
+                                  struct komeda_data_flow_cfg *dflow,
                                   struct drm_framebuffer *fb)
 {
+       struct komeda_scaler *scaler = layer->base.pipeline->scalers[0];
        u32 w = dflow->in_w;
        u32 h = dflow->in_h;
 
@@ -803,6 +805,17 @@ void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
 
        dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h);
        dflow->is_yuv = fb->format->is_yuv;
+
+       /* try to enable image enhancer if data flow is a 2x+ upscaling */
+       dflow->en_img_enhancement = dflow->out_w >= 2 * w ||
+                                   dflow->out_h >= 2 * h;
+
+       /* try to enable split if scaling exceed the scaler's acceptable
+        * input/output range.
+        */
+       if (dflow->en_scaling && scaler)
+               dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) ||
+                                 !in_range(&scaler->hsize, dflow->out_w);
 }
 
 static bool merger_is_available(struct komeda_pipeline *pipe,
index 04b122f28fb65066ee883840f41ecf92d2a59e71..c095af154216a0f8318762497d01dbfe25bd5746 100644 (file)
@@ -18,7 +18,6 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
                            struct komeda_data_flow_cfg *dflow)
 {
        struct komeda_plane *kplane = to_kplane(st->plane);
-       struct komeda_plane_state *kplane_st = to_kplane_st(st);
        struct drm_framebuffer *fb = st->fb;
        const struct komeda_format_caps *caps = to_kfb(fb)->format_caps;
        struct komeda_pipeline *pipe = kplane->layer->base.pipeline;
@@ -57,10 +56,7 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
                return -EINVAL;
        }
 
-       dflow->en_img_enhancement = !!kplane_st->img_enhancement;
-       dflow->en_split = !!kplane_st->layer_split;
-
-       komeda_complete_data_flow_cfg(dflow, fb);
+       komeda_complete_data_flow_cfg(kplane->layer, dflow, fb);
 
        return 0;
 }
@@ -175,8 +171,6 @@ komeda_plane_atomic_duplicate_state(struct drm_plane *plane)
 
        old = to_kplane_st(plane->state);
 
-       new->img_enhancement = old->img_enhancement;
-
        return &new->base;
 }
 
@@ -188,44 +182,6 @@ komeda_plane_atomic_destroy_state(struct drm_plane *plane,
        kfree(to_kplane_st(state));
 }
 
-static int
-komeda_plane_atomic_get_property(struct drm_plane *plane,
-                                const struct drm_plane_state *state,
-                                struct drm_property *property,
-                                uint64_t *val)
-{
-       struct komeda_plane *kplane = to_kplane(plane);
-       struct komeda_plane_state *st = to_kplane_st(state);
-
-       if (property == kplane->prop_img_enhancement)
-               *val = st->img_enhancement;
-       else if (property == kplane->prop_layer_split)
-               *val = st->layer_split;
-       else
-               return -EINVAL;
-
-       return 0;
-}
-
-static int
-komeda_plane_atomic_set_property(struct drm_plane *plane,
-                                struct drm_plane_state *state,
-                                struct drm_property *property,
-                                uint64_t val)
-{
-       struct komeda_plane *kplane = to_kplane(plane);
-       struct komeda_plane_state *st = to_kplane_st(state);
-
-       if (property == kplane->prop_img_enhancement)
-               st->img_enhancement = !!val;
-       else if (property == kplane->prop_layer_split)
-               st->layer_split = !!val;
-       else
-               return -EINVAL;
-
-       return 0;
-}
-
 static bool
 komeda_plane_format_mod_supported(struct drm_plane *plane,
                                  u32 format, u64 modifier)
@@ -245,43 +201,9 @@ static const struct drm_plane_funcs komeda_plane_funcs = {
        .reset                  = komeda_plane_reset,
        .atomic_duplicate_state = komeda_plane_atomic_duplicate_state,
        .atomic_destroy_state   = komeda_plane_atomic_destroy_state,
-       .atomic_get_property    = komeda_plane_atomic_get_property,
-       .atomic_set_property    = komeda_plane_atomic_set_property,
        .format_mod_supported   = komeda_plane_format_mod_supported,
 };
 
-static int
-komeda_plane_create_layer_properties(struct komeda_plane *kplane,
-                                    struct komeda_layer *layer)
-{
-       struct drm_device *drm = kplane->base.dev;
-       struct drm_plane *plane = &kplane->base;
-       struct drm_property *prop = NULL;
-
-       /* property: layer image_enhancement */
-       if (layer->base.supported_outputs & KOMEDA_PIPELINE_SCALERS) {
-               prop = drm_property_create_bool(drm, DRM_MODE_PROP_ATOMIC,
-                                               "img_enhancement");
-               if (!prop)
-                       return -ENOMEM;
-
-               drm_object_attach_property(&plane->base, prop, 0);
-               kplane->prop_img_enhancement = prop;
-       }
-
-       /* property: layer split */
-       if (layer->right) {
-               prop = drm_property_create_bool(drm, DRM_MODE_PROP_ATOMIC,
-                                               "layer_split");
-               if (!prop)
-                       return -ENOMEM;
-               kplane->prop_layer_split = prop;
-               drm_object_attach_property(&plane->base, prop, 0);
-       }
-
-       return 0;
-}
-
 /* for komeda, which is pipeline can be share between crtcs */
 static u32 get_possible_crtcs(struct komeda_kms_dev *kms,
                              struct komeda_pipeline *pipe)
@@ -375,10 +297,6 @@ static int komeda_plane_add(struct komeda_kms_dev *kms,
        if (err)
                goto cleanup;
 
-       err = komeda_plane_create_layer_properties(kplane, layer);
-       if (err)
-               goto cleanup;
-
        err = drm_plane_create_color_properties(plane,
                        BIT(DRM_COLOR_YCBCR_BT601) |
                        BIT(DRM_COLOR_YCBCR_BT709) |
index bb8a61f6e9a4116a19d8c82d846d4f2ad989c563..617e1f7b8472e874250bf5a951856df9fa6de36c 100644 (file)
@@ -13,7 +13,6 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer,
                         struct komeda_crtc_state *kcrtc_st,
                         struct komeda_data_flow_cfg *dflow)
 {
-       struct komeda_scaler *scaler = wb_layer->base.pipeline->scalers[0];
        struct drm_framebuffer *fb = conn_st->writeback_job->fb;
 
        memset(dflow, 0, sizeof(*dflow));
@@ -28,14 +27,7 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer,
        dflow->pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE;
        dflow->rot = DRM_MODE_ROTATE_0;
 
-       komeda_complete_data_flow_cfg(dflow, fb);
-
-       /* if scaling exceed the acceptable scaler input/output range, try to
-        * enable split.
-        */
-       if (dflow->en_scaling && scaler)
-               dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) ||
-                                 !in_range(&scaler->hsize, dflow->out_w);
+       komeda_complete_data_flow_cfg(wb_layer, dflow, fb);
 
        return 0;
 }
index cc35d492142ce4ab1aecb4729d9e1fc56c447e33..2a65434500eea60de3707ba57ea2fea40f617ea0 100644 (file)
@@ -86,7 +86,7 @@ void bochs_hw_setmode(struct bochs_device *bochs,
 void bochs_hw_setformat(struct bochs_device *bochs,
                        const struct drm_format_info *format);
 void bochs_hw_setbase(struct bochs_device *bochs,
-                     int x, int y, u64 addr);
+                     int x, int y, int stride, u64 addr);
 int bochs_hw_load_edid(struct bochs_device *bochs);
 
 /* bochs_mm.c */
index 791ab2f79947fdfb6a87a3f1d3f4da08ff69c6b2..ebfea8744fe6f2b4d48bdfd4ff38dcc560d096e0 100644 (file)
@@ -255,16 +255,22 @@ void bochs_hw_setformat(struct bochs_device *bochs,
 }
 
 void bochs_hw_setbase(struct bochs_device *bochs,
-                     int x, int y, u64 addr)
+                     int x, int y, int stride, u64 addr)
 {
-       unsigned long offset = (unsigned long)addr +
+       unsigned long offset;
+       unsigned int vx, vy, vwidth;
+
+       bochs->stride = stride;
+       offset = (unsigned long)addr +
                y * bochs->stride +
                x * (bochs->bpp / 8);
-       int vy = offset / bochs->stride;
-       int vx = (offset % bochs->stride) * 8 / bochs->bpp;
+       vy = offset / bochs->stride;
+       vx = (offset % bochs->stride) * 8 / bochs->bpp;
+       vwidth = stride * 8 / bochs->bpp;
 
        DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
                         x, y, addr, offset, vx, vy);
+       bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
        bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
        bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
 }
index 5904eddc83a51824f2b30a1216a8e3aafa8f3e39..bc19dbd531efc237b1407bcee204e28c52474d72 100644 (file)
@@ -36,7 +36,8 @@ static void bochs_plane_update(struct bochs_device *bochs,
        bochs_hw_setbase(bochs,
                         state->crtc_x,
                         state->crtc_y,
-                        gbo->bo.offset);
+                        state->fb->pitches[0],
+                        state->fb->offsets[0] + gbo->bo.offset);
        bochs_hw_setformat(bochs, state->fb->format);
 }
 
index e95fceac8f8bf38d3f837b636cd05bf0e41d2cac..56d36779d21321f0e4c74d1606b6952bdee392a9 100644 (file)
@@ -180,7 +180,8 @@ again:
 
 create_mode:
        mode = drm_mode_create_from_cmdline_mode(connector->dev, cmdline_mode);
-       list_add(&mode->head, &connector->modes);
+       if (mode)
+               list_add(&mode->head, &connector->modes);
 
        return mode;
 }
index 3afed5677946689758acafd640ef65ec7985f035..b3f2cf7eae9c3388ef8b544346dbc5b649174bc7 100644 (file)
@@ -141,7 +141,7 @@ static void drm_connector_get_cmdline_mode(struct drm_connector *connector)
 
        DRM_DEBUG_KMS("cmdline mode for connector %s %s %dx%d@%dHz%s%s%s\n",
                      connector->name,
-                     mode->name ? mode->name : "",
+                     mode->name,
                      mode->xres, mode->yres,
                      mode->refresh_specified ? mode->refresh : 60,
                      mode->rb ? " reduced blanking" : "",
index 57e6408288c80f6adb86c2b29b23a1b0e1829627..74a5739df506aaed0994f842e024f55fec4ea4aa 100644 (file)
@@ -158,6 +158,9 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
        int interlace;
        u64 tmp;
 
+       if (!hdisplay || !vdisplay)
+               return NULL;
+
        /* allocate the drm_display_mode structure. If failure, we will
         * return directly
         */
@@ -392,6 +395,9 @@ drm_gtf_mode_complex(struct drm_device *dev, int hdisplay, int vdisplay,
        int hsync, hfront_porch, vodd_front_porch_lines;
        unsigned int tmp1, tmp2;
 
+       if (!hdisplay || !vdisplay)
+               return NULL;
+
        drm_mode = drm_mode_create(dev);
        if (!drm_mode)
                return NULL;
@@ -1448,7 +1454,7 @@ static int drm_mode_parse_cmdline_refresh(const char *str, char **end_ptr,
 }
 
 static int drm_mode_parse_cmdline_extra(const char *str, int length,
-                                       struct drm_connector *connector,
+                                       const struct drm_connector *connector,
                                        struct drm_cmdline_mode *mode)
 {
        int i;
@@ -1493,7 +1499,7 @@ static int drm_mode_parse_cmdline_extra(const char *str, int length,
 
 static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length,
                                           bool extras,
-                                          struct drm_connector *connector,
+                                          const struct drm_connector *connector,
                                           struct drm_cmdline_mode *mode)
 {
        const char *str_start = str;
@@ -1555,7 +1561,7 @@ static int drm_mode_parse_cmdline_res_mode(const char *str, unsigned int length,
 }
 
 static int drm_mode_parse_cmdline_options(char *str, size_t len,
-                                         struct drm_connector *connector,
+                                         const struct drm_connector *connector,
                                          struct drm_cmdline_mode *mode)
 {
        unsigned int rotation = 0;
@@ -1689,7 +1695,7 @@ static int drm_mode_parse_cmdline_options(char *str, size_t len,
  * True if a valid modeline has been parsed, false otherwise.
  */
 bool drm_mode_parse_command_line_for_connector(const char *mode_option,
-                                              struct drm_connector *connector,
+                                              const struct drm_connector *connector,
                                               struct drm_cmdline_mode *mode)
 {
        const char *name;
index d8a0bcd02f34c4314c669455e56634845a60ae56..ffd95bfeaa94cf253e1fb96ce896313733b6ae25 100644 (file)
@@ -90,6 +90,12 @@ static const struct drm_dmi_panel_orientation_data itworks_tw891 = {
        .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
 };
 
+static const struct drm_dmi_panel_orientation_data lcd720x1280_rightside_up = {
+       .width = 720,
+       .height = 1280,
+       .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
 static const struct drm_dmi_panel_orientation_data lcd800x1280_rightside_up = {
        .width = 800,
        .height = 1280,
@@ -123,6 +129,12 @@ static const struct dmi_system_id orientation_data[] = {
                  DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
                },
                .driver_data = (void *)&gpd_micropc,
+       }, {    /* GPD MicroPC (later BIOS versions with proper DMI strings) */
+               .matches = {
+                 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "GPD"),
+                 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MicroPC"),
+               },
+               .driver_data = (void *)&lcd720x1280_rightside_up,
        }, {    /*
                 * GPD Pocket, note that the the DMI data is less generic then
                 * it seems, devices with a board-vendor of "AMI Corporation"
index b0f53f4f71bf05e08b4919b5f812b4eb91527a1b..7a62fa04272daa7d99a55e8f626ce3310a8fbcf2 100644 (file)
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0
+# SPDX-License-Identifier: MIT
 ccflags-y += -I $(srctree)/$(src)/include
 ccflags-y += -I $(srctree)/$(src)/include/nvkm
 ccflags-y += -I $(srctree)/$(src)/nvkm
index 65a3990b4e164fcc0b4a2c24ac7fd50dbc37165b..975c4e2269366d57e928eedbbbc669d24744379f 100644 (file)
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0
+# SPDX-License-Identifier: MIT
 nouveau-y += dispnv04/arb.o
 nouveau-y += dispnv04/crtc.o
 nouveau-y += dispnv04/cursor.o
index ebf860bd59af01dd8146dbad104b6146e86c1b9d..16e09f6b91139205717317099cfd5160d7ecf6ac 100644 (file)
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: MIT
 #include <drm/drmP.h>
 #include <drm/drm_mode.h>
 #include "nouveau_drv.h"
index c6ed20a09f4ae1b4edd2d16964c0910c72fbf4aa..6ccfc09bcf0f7c10583abfe835d0d10ab4a0fec5 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NV04_DISPLAY_H__
 #define __NV04_DISPLAY_H__
 #include <subdev/bios.h>
index 475c630308d1f23b871cc9ba6a5c915d2205a3cc..e0c435eae66464b90c00be7edc4fbe4c831b7049 100644 (file)
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0
+# SPDX-License-Identifier: MIT
 nouveau-y += dispnv50/disp.o
 nouveau-y += dispnv50/lut.o
 
index 7ba373f493b298ea90326321df28daab7de21ce2..8497768f1b4102ac76d7e5d45257aec2bb72a82b 100644 (file)
@@ -322,8 +322,13 @@ nv50_outp_atomic_check_view(struct drm_encoder *encoder,
                switch (connector->connector_type) {
                case DRM_MODE_CONNECTOR_LVDS:
                case DRM_MODE_CONNECTOR_eDP:
-                       /* Force use of scaler for non-EDID modes. */
-                       if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
+                       /* Don't force scaler for EDID modes with
+                        * same size as the native one (e.g. different
+                        * refresh rate)
+                        */
+                       if (adjusted_mode->hdisplay == native_mode->hdisplay &&
+                           adjusted_mode->vdisplay == native_mode->vdisplay &&
+                           adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
                                break;
                        mode = native_mode;
                        asyc->scaler.full = true;
index 48a6485ec4e0bc1dc0bb3f5d6cc076d8be700409..929d93b1677e73c3d94501c4f236201b2c556f53 100644 (file)
@@ -169,14 +169,34 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh,
         */
        switch (mode) {
        case DRM_MODE_SCALE_CENTER:
-               asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
-               asyh->view.oH = min((u16)umode_vdisplay, asyh->view.oH);
-               /* fall-through */
+               /* NOTE: This will cause scaling when the input is
+                * larger than the output.
+                */
+               asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
+               asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
+               break;
        case DRM_MODE_SCALE_ASPECT:
-               if (asyh->view.oH < asyh->view.oW) {
+               /* Determine whether the scaling should be on width or on
+                * height. This is done by comparing the aspect ratios of the
+                * sizes. If the output AR is larger than input AR, that means
+                * we want to change the width (letterboxed on the
+                * left/right), otherwise on the height (letterboxed on the
+                * top/bottom).
+                *
+                * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
+                * screen will have letterboxes on the left/right. However a
+                * 16:9 (1.777) AR image on that same screen will have
+                * letterboxes on the top/bottom.
+                *
+                * inputAR = iW / iH; outputAR = oW / oH
+                * outputAR > inputAR is equivalent to oW * iH > iW * oH
+                */
+               if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
+                       /* Recompute output width, i.e. left/right letterbox */
                        u32 r = (asyh->view.iW << 19) / asyh->view.iH;
                        asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
                } else {
+                       /* Recompute output height, i.e. top/bottom letterbox */
                        u32 r = (asyh->view.iH << 19) / asyh->view.iW;
                        asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
                }
index 1a8b45b4631f890c386ee16d6cd9cfd0fd301768..65d432a5bd6cf7a25e0cd283df1d7459c8faf1e1 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL0002_H__
 #define __NVIF_CL0002_H__
 
index c0d5eba4f8fc55f3d469bf1844277e92d5f22d39..d490d401870ad77e22446161d13ccf2d47ff4b2f 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL0046_H__
 #define __NVIF_CL0046_H__
 
index d0e8f35d9e92a4170fab3705f33489f0a4cbae73..c960c449e430b9c52632327ef694597fa807443e 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL006B_H__
 #define __NVIF_CL006B_H__
 
index 4cbed03293676742c5e5b2b72f50537df63a0e1e..cd9a2e687bb61ba96cfe347ef3b25cc9e8e78fb5 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL0080_H__
 #define __NVIF_CL0080_H__
 
index 989690fe3cd88ec8330d1ed798efb71b4141a3ca..9df289c7a84f7bbf69d23e5f9846efeb0ebc9b45 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL506E_H__
 #define __NVIF_CL506E_H__
 
index 5137b6879abdc9de6f8cbce6c7716983570c79d3..327c96a994bbe8ba14acf489b65f7073f3112548 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL506F_H__
 #define __NVIF_CL506F_H__
 
index bced8198726912ae4c8b7cf17a776adeddbc27c2..38bf4f38e8692a386ba87cd4f6a2d7de5239e91e 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL5070_H__
 #define __NVIF_CL5070_H__
 
index 36e5372185969417b88bdc68a7edd4ebf1dc96e1..3b2a9809b8cef0f730d3a36ab899a188f128fa1f 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL507A_H__
 #define __NVIF_CL507A_H__
 
index 3e643b752bfcc6e45654fc32de0ca8270b6d597a..0f3d05581ea51c0939ad6b1a6755ecac695215dd 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL507B_H__
 #define __NVIF_CL507B_H__
 
index fd9e336d0a241fb6a1d83231da6e343f5f0102be..7da8813f4f5c47b986936e31ffc65e9eebae33a7 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL507C_H__
 #define __NVIF_CL507C_H__
 
index e994c6894e3ec7c618f7dff8525f4fae9d553525..4a56e42d8bc90bea6f5db43f72c609ae1a378997 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL507D_H__
 #define __NVIF_CL507D_H__
 
index 8082d2fde248448772d8b5e58718783e4988cc25..633936cb631337d4687db9f64fd29fdde077d2a9 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL507E_H__
 #define __NVIF_CL507E_H__
 
index 1a875090b251ddc4183b273cdcfc30382791ba58..1b6496d3158031d45cd3b7d3d75d2711350c7595 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL826E_H__
 #define __NVIF_CL826E_H__
 
index e4e50cfe88f16cf9b6929039967181ab27f0d9fa..148602264a764b9111b0bae6dc0a0c191624098a 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL826F_H__
 #define __NVIF_CL826F_H__
 
index ab0fa8adb756cbd77d7fe607e91019f50c1dab58..3823d6891b5560a588f83b70d47d0a65f023b21d 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL906F_H__
 #define __NVIF_CL906F_H__
 
index e4c8de6d00b71f8ccbd866130573f8435f9ab826..599d858afa3618bcc190fe26b68f0cc6346fc240 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CL9097_H__
 #define __NVIF_CL9097_H__
 
index 81401eb970ea68798356a667e7249cfea9d34fda..cfa18f1fbf83818afd33cdd3f09b8f9e6a6eb164 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CLA06F_H__
 #define __NVIF_CLA06F_H__
 
index 7d556a1c92fac98d173ca7e00064d6f366d829ed..f704ae600e948b2eb708cc3f4f6c841381f354eb 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CLASS_H__
 #define __NVIF_CLASS_H__
 
index 6b14d7e3f6bbc5708a25e2f80c3ec965842c181e..f66885891238ebb3a70a6425c0f20936340b0244 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CLC36F_H__
 #define __NVIF_CLC36F_H__
 
index 89b18189d43b394d48eb8c9f259d54508a8d1c44..970a5ac4cb9571a61a1714378a1fc27225a24caa 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CLC37B_H__
 #define __NVIF_CLC37B_H__
 
index 899db9e915efa1019ecdf320f97a28f0e96159a2..7ea23695e7e166b9c1478837341e83e7ac6a170f 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CLC37E_H__
 #define __NVIF_CLC37E_H__
 
index f5df8b30c599366abcda890ec3c3288cb4747c39..e63c6c965b543d08939dab8f9111eb6ae4978d11 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_CLIENT_H__
 #define __NVIF_CLIENT_H__
 
index ef839bd1d37ee2919f268dac62b1c733f33d0198..25d969dcf67d0182f0fca491dd6834fe49533d5e 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_DEVICE_H__
 #define __NVIF_DEVICE_H__
 
index 93bccd45a042c1fe472bd77fe6ec5a3a14a0e650..8e85b936eaa041da8369903d08ca6c13feab54f1 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_DRIVER_H__
 #define __NVIF_DRIVER_H__
 #include <nvif/os.h>
index ec5c924f576aadffcfad0b76eec907be8e02dfaa..a6b1ee4f10caf4167e913a1fccf1f63f08e30278 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_EVENT_H__
 #define __NVIF_EVENT_H__
 
index 30ecd31db5df0505743448f4249e4c00b4290659..f7b8f8f48760142e7709496e7b12d7d0bad9bb05 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_IF0000_H__
 #define __NVIF_IF0000_H__
 
index ca921526221575f95bdc80b982326cbf390cfe90..4ced50e98ced8ebf3276018357ec990424871498 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_IF0001_H__
 #define __NVIF_IF0001_H__
 
index d9235c01119618530f988c2e54292fbf98bc42f4..df2915d6a61e940e3e9e7e64988d3cab4cd94f45 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_IF0002_H__
 #define __NVIF_IF0002_H__
 
index ae30b8261b88231ca3f6390014933b4f1e9f5de0..78467da07c373582e60379331f90f77b9a545761 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_IF0003_H__
 #define __NVIF_IF0003_H__
 
index b35547c8ea362ea90fc058a7aaf5d11f2aa653e2..d324c73c27fb5dd9ac41f8d90f0665720fc39a7d 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_IF0004_H__
 #define __NVIF_IF0004_H__
 
index 8ed0ae101715bf2dd56fa3cc88e234e65e5d824a..fb9305b3b32c179e6ba16399f3c293bc9c5a817f 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_IF0005_H__
 #define __NVIF_IF0005_H__
 #define NV10_NVSW_NTFY_UEVENT                                              0x00
index b93d586a2304e02c810c5cd24cf2ecf052f6673f..886c63fe753fbc4ff0b83b3d881f97d83655b9ec 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_IOCTL_H__
 #define __NVIF_IOCTL_H__
 
index 4ed1692306575f0b1b9594dad7f71eb99480a272..6863732eb286f63ca0cb16d07c397fb6e3a4395d 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_NOTIFY_H__
 #define __NVIF_NOTIFY_H__
 
index 8407651f6ac6ef2b3327953d3114118f85d58acf..604fabc0e689ea8740b920eb1d299758f23ffd09 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_OBJECT_H__
 #define __NVIF_OBJECT_H__
 
index fd09b28429723cd7aa91be61975b199cd1730074..429d0106c1238d9fb4c02c779479bc9ca91acf7b 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NOUVEAU_OS_H__
 #define __NOUVEAU_OS_H__
 
index 7f0d9f6cc1e7ef4613b66b9219058571a02e1c1d..0584b938e8f990358e77f3baee9ae26b6304857b 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVIF_UNPACK_H__
 #define __NVIF_UNPACK_H__
 
index 757fac823a10fa9f0de9c4962829bab818044615..5d7017fe5039b8e4c35e9b0ed7166e38f8a5a368 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_CLIENT_H__
 #define __NVKM_CLIENT_H__
 #define nvkm_client(p) container_of((p), struct nvkm_client, object)
index 966d1822dd809703f823029a081778d1f2fe57d0..b4a9c7d991ca46bc08dcb2cb3d6d6c2ccd419160 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_DEBUG_H__
 #define __NVKM_DEBUG_H__
 #define NV_DBG_FATAL    0
index 642492344196c5339c95f5fae6f0321becad5e23..6d55cd0476aaab10a19c2060a46e622ac2c088ab 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_DEVICE_H__
 #define __NVKM_DEVICE_H__
 #include <core/oclass.h>
index 8a2be5b635e22a3dbb38b5dd06695764161eda6a..c6b401a6ea236e1a66366a5c26e0fffdfcf54f04 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_ENGINE_H__
 #define __NVKM_ENGINE_H__
 #define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev)
index 38acbde2de4f27987b89fa5569e8d0430e0fc182..ce98efd4b209f5f0e814599c25c8e1ea2ca2b2e1 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_ENUM_H__
 #define __NVKM_ENUM_H__
 #include <core/os.h>
index d3c45e90a1c1346fe4e5a0f533ea3a56e0ccea04..a7a413f07a7892f27292ef205a7a3ea005be3301 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_EVENT_H__
 #define __NVKM_EVENT_H__
 #include <core/os.h>
index 54da9c6bc8d57172a0d9ec8287e032dd4cfdb016..383370c3242807b154f3ac8d1cf845cb22ae71ae 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_FIRMWARE_H__
 #define __NVKM_FIRMWARE_H__
 #include <core/subdev.h>
index 10eeaeebc242d54e735fe53e901741672cc89694..0f515ec28fa9a7e15e33a376592b8a78fa3a8b26 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_GPUOBJ_H__
 #define __NVKM_GPUOBJ_H__
 #include <core/memory.h>
index e2d39192fa26c170c3739ecc2b68dd09213f0856..71ed147ad077395c7038f797dfc9a3dc4917a1d2 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_IOCTL_H__
 #define __NVKM_IOCTL_H__
 #include <core/os.h>
index f34c80310861ed9446342e304ec385ed775a610d..b23bf6109f2d28a634df13382707e1bcb9813492 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_MEMORY_H__
 #define __NVKM_MEMORY_H__
 #include <core/os.h>
index b0726c39429ea8441629ecf59375598f6aae2f6c..4ecfbde8853770a9d8ef7ca38ee427b9af754301 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_MM_H__
 #define __NVKM_MM_H__
 #include <core/os.h>
index 4eb82bc563f3a4f28a345701ac4b9233563e7114..3d358a66db3a3d16d425f54ccedde6f9a4da8b42 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_NOTIFY_H__
 #define __NVKM_NOTIFY_H__
 #include <core/os.h>
index 270f893cc15456e0776785064faa0e3c8723834c..7efcd5d2f2fffea4a8c8208cd74d1ce4cc44d07a 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_OBJECT_H__
 #define __NVKM_OBJECT_H__
 #include <core/oclass.h>
index d950d5ee188b8e3cbff7e8ec2d454b73c5e4e851..0e70a9afba33d4566ca0555ae53fc3035ee6e60c 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_OPROXY_H__
 #define __NVKM_OPROXY_H__
 #define nvkm_oproxy(p) container_of((p), struct nvkm_oproxy, base)
index a34a79bacbd0a0f035b5e95d6952460f70fb4840..6882eb7c7e2696f0a55e3495b7c651049658ef59 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_OPTION_H__
 #define __NVKM_OPTION_H__
 #include <core/os.h>
index 445602d1e8d3a987396807c587860c73a8eeb408..029a416197db3c64cf687448d0e0d8ee95d672bb 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_OS_H__
 #define __NVKM_OS_H__
 #include <nvif/os.h>
index 4c7f647d2dc960049ef2343a3ca38de83cb33eb1..b4b5df3e16101f48d59fb38200ba01636d8ed7e3 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_DEVICE_PCI_H__
 #define __NVKM_DEVICE_PCI_H__
 #include <core/device.h>
index d5d789663aca392d9eee88a3073beacbb374922b..bc2d1dcccb4e8dd7201f218ec3a20c0aa8351dd5 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_RAMHT_H__
 #define __NVKM_RAMHT_H__
 #include <core/gpuobj.h>
index 85a0777c2ce444c85f9411ae52afe5ac98341dbe..1218f28c14baba31cd93e7453de2694cda24e4d1 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_SUBDEV_H__
 #define __NVKM_SUBDEV_H__
 #include <core/device.h>
index 5c102d0206a7abf298231949a56c94cb76249036..924009dd2bb07488113d260550d9f94afccde966 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_DEVICE_TEGRA_H__
 #define __NVKM_DEVICE_TEGRA_H__
 #include <core/device.h>
index 40613983fccb3acb5535417fa355a5f130aac1df..f938f024db8107e95ddc3d6925bc13231943d616 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_BSP_H__
 #define __NVKM_BSP_H__
 #include <engine/xtensa.h>
index 5f3650692e4dae9a45baa7ee3d07bfad822ef9bf..86f420f4630b28320f17960000ff616eab9399fc 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_CE_H__
 #define __NVKM_CE_H__
 #include <engine/falcon.h>
index 72b9da2de7c2d288d467d9bafd397695731a0372..66c5c5e275208f51157e411cf30047dd6d5309d5 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_CIPHER_H__
 #define __NVKM_CIPHER_H__
 #include <core/engine.h>
index 3026b22d44fb9a284f96410f0cdf3259b6f938bf..5a96c942d912f0c68edc9227fd7eab1ef08ab503 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_DISP_H__
 #define __NVKM_DISP_H__
 #define nvkm_disp(p) container_of((p), struct nvkm_disp, engine)
index f0c1b2c8c78c2f3bddb3ccd315083659b84e0a35..2e12cdb6bb9357f0a77d84563a7003b07d8b38c9 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: MIT */
 #ifndef __NVKM_DMA_H__
 #define __NVKM_DMA_H__
 #include <core/engine.h>
index 6427747b6f77ffc4f599881808524dc357d276c5..23b582d696c619522cbc9e6e41827ddf99dfb559 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Ide