Merge remote-tracking branches 'asoc/topic/adsp', 'asoc/topic/ak4613', 'asoc/topic...
authorMark Brown <broonie@kernel.org>
Sun, 30 Apr 2017 13:15:45 +0000 (22:15 +0900)
committerMark Brown <broonie@kernel.org>
Sun, 30 Apr 2017 13:15:45 +0000 (22:15 +0900)
sound/soc/blackfin/bfin-eval-adau1373.c
sound/soc/blackfin/bfin-eval-adav80x.c
sound/soc/codecs/Kconfig
sound/soc/codecs/ak4613.c
sound/soc/codecs/wm_adsp.c
sound/soc/codecs/wm_adsp.h

index 72ac789884262bbdc41e63adfcabe1dee3911814..64b88fdc1f6cfc3af2bcc5500a70731c12d2f462 100644 (file)
@@ -119,7 +119,7 @@ static int bfin_eval_adau1373_codec_init(struct snd_soc_pcm_runtime *rtd)
 
        return ret;
 }
-static struct snd_soc_ops bfin_eval_adau1373_ops = {
+static const struct snd_soc_ops bfin_eval_adau1373_ops = {
        .hw_params = bfin_eval_adau1373_hw_params,
 };
 
index 1037477d10b2f962cf6d7ea13844d01539bdeafb..99e5ecabdcda3c23d8beef43bdca4ccd56b0e160 100644 (file)
@@ -64,7 +64,7 @@ static int bfin_eval_adav80x_codec_init(struct snd_soc_pcm_runtime *rtd)
        return 0;
 }
 
-static struct snd_soc_ops bfin_eval_adav80x_ops = {
+static const struct snd_soc_ops bfin_eval_adav80x_ops = {
        .hw_params = bfin_eval_adav80x_hw_params,
 };
 
index e49e9da7f1f6e41028a0ca832e76e7dce0bc1c01..43539c3b713576cce73095c5bb2b2cb5a60f30bd 100644 (file)
@@ -303,12 +303,14 @@ config SND_SOC_ADAU1761
        select SND_SOC_ADAU17X1
 
 config SND_SOC_ADAU1761_I2C
-       tristate
+       tristate "Analog Devices AU1761 CODEC - I2C"
+       depends on I2C
        select SND_SOC_ADAU1761
        select REGMAP_I2C
 
 config SND_SOC_ADAU1761_SPI
-       tristate
+       tristate "Analog Devices AU1761 CODEC - SPI"
+       depends on SPI
        select SND_SOC_ADAU1761
        select REGMAP_SPI
 
index e819dd8c82fdced146515a9da7c604f783bc2d32..b2dfddead22774cc85a9b4612b8edbfd3ceffa5c 100644 (file)
 #define DFS_DOUBLE_SPEED       (1 << 2)
 #define DFS_QUAD_SPEED         (2 << 2)
 
+/* ICTRL */
+#define ICTRL_MASK     (0x3)
+
+/* OCTRL */
+#define OCTRL_MASK     (0x3F)
+
 struct ak4613_formats {
        unsigned int width;
        unsigned int fmt;
@@ -365,8 +371,8 @@ static int ak4613_dai_hw_params(struct snd_pcm_substream *substream,
        snd_soc_update_bits(codec, CTRL1, FMT_MASK, fmt_ctrl);
        snd_soc_update_bits(codec, CTRL2, DFS_MASK, ctrl2);
 
-       snd_soc_write(codec, ICTRL, priv->ic);
-       snd_soc_write(codec, OCTRL, priv->oc);
+       snd_soc_update_bits(codec, ICTRL, ICTRL_MASK, priv->ic);
+       snd_soc_update_bits(codec, OCTRL, OCTRL_MASK, priv->oc);
 
 hw_params_end:
        if (ret < 0)
index bbdb72f73df19ddf954daab19d3deb222208dc7c..20695b691aff7a8e34c255d92ace0283018b3b26 100644 (file)
 #define ADSP1_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 #define ADSP1_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 
-#define ADSP2_CONTROL        0x0
-#define ADSP2_CLOCKING       0x1
-#define ADSP2_STATUS1        0x4
-#define ADSP2_WDMA_CONFIG_1 0x30
-#define ADSP2_WDMA_CONFIG_2 0x31
-#define ADSP2_RDMA_CONFIG_1 0x34
-
-#define ADSP2_SCRATCH0        0x40
-#define ADSP2_SCRATCH1        0x41
-#define ADSP2_SCRATCH2        0x42
-#define ADSP2_SCRATCH3        0x43
+#define ADSP2_CONTROL                     0x0
+#define ADSP2_CLOCKING                    0x1
+#define ADSP2V2_CLOCKING                  0x2
+#define ADSP2_STATUS1                     0x4
+#define ADSP2_WDMA_CONFIG_1               0x30
+#define ADSP2_WDMA_CONFIG_2               0x31
+#define ADSP2V2_WDMA_CONFIG_2             0x32
+#define ADSP2_RDMA_CONFIG_1               0x34
+
+#define ADSP2_SCRATCH0                    0x40
+#define ADSP2_SCRATCH1                    0x41
+#define ADSP2_SCRATCH2                    0x42
+#define ADSP2_SCRATCH3                    0x43
+
+#define ADSP2V2_SCRATCH0_1                0x40
+#define ADSP2V2_SCRATCH2_3                0x42
 
 /*
  * ADSP2 Control
 #define ADSP2_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
 #define ADSP2_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
 
+/*
+ * ADSP2V2 clocking
+ */
+#define ADSP2V2_CLK_SEL_MASK             0x70000  /* CLK_SEL_ENA */
+#define ADSP2V2_CLK_SEL_SHIFT                 16  /* CLK_SEL_ENA */
+#define ADSP2V2_CLK_SEL_WIDTH                  3  /* CLK_SEL_ENA */
+
+#define ADSP2V2_RATE_MASK                 0x7800  /* DSP_RATE */
+#define ADSP2V2_RATE_SHIFT                    11  /* DSP_RATE */
+#define ADSP2V2_RATE_WIDTH                     4  /* DSP_RATE */
+
 /*
  * ADSP2 Status 1
  */
 #define ADSP2_RAM_RDY_SHIFT                    0
 #define ADSP2_RAM_RDY_WIDTH                    1
 
+/*
+ * ADSP2 Lock support
+ */
+#define ADSP2_LOCK_CODE_0                    0x5555
+#define ADSP2_LOCK_CODE_1                    0xAAAA
+
+#define ADSP2_WATCHDOG                       0x0A
+#define ADSP2_BUS_ERR_ADDR                   0x52
+#define ADSP2_REGION_LOCK_STATUS             0x64
+#define ADSP2_LOCK_REGION_1_LOCK_REGION_0    0x66
+#define ADSP2_LOCK_REGION_3_LOCK_REGION_2    0x68
+#define ADSP2_LOCK_REGION_5_LOCK_REGION_4    0x6A
+#define ADSP2_LOCK_REGION_7_LOCK_REGION_6    0x6C
+#define ADSP2_LOCK_REGION_9_LOCK_REGION_8    0x6E
+#define ADSP2_LOCK_REGION_CTRL               0x7A
+#define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR    0x7C
+
+#define ADSP2_REGION_LOCK_ERR_MASK           0x8000
+#define ADSP2_SLAVE_ERR_MASK                 0x4000
+#define ADSP2_WDT_TIMEOUT_STS_MASK           0x2000
+#define ADSP2_CTRL_ERR_PAUSE_ENA             0x0002
+#define ADSP2_CTRL_ERR_EINT                  0x0001
+
+#define ADSP2_BUS_ERR_ADDR_MASK              0x00FFFFFF
+#define ADSP2_XMEM_ERR_ADDR_MASK             0x0000FFFF
+#define ADSP2_PMEM_ERR_ADDR_MASK             0x7FFF0000
+#define ADSP2_PMEM_ERR_ADDR_SHIFT            16
+#define ADSP2_WDT_ENA_MASK                   0xFFFFFFFD
+
+#define ADSP2_LOCK_REGION_SHIFT              16
+
 #define ADSP_MAX_STD_CTRL_SIZE               512
 
 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS         100
@@ -683,6 +730,9 @@ static const struct soc_enum wm_adsp_fw_enum[] = {
        SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
        SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
        SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
+       SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
+       SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
+       SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
 };
 
 const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
@@ -694,6 +744,12 @@ const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
                     wm_adsp_fw_get, wm_adsp_fw_put),
        SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
                     wm_adsp_fw_get, wm_adsp_fw_put),
+       SOC_ENUM_EXT("DSP5 Firmware", wm_adsp_fw_enum[4],
+                    wm_adsp_fw_get, wm_adsp_fw_put),
+       SOC_ENUM_EXT("DSP6 Firmware", wm_adsp_fw_enum[5],
+                    wm_adsp_fw_get, wm_adsp_fw_put),
+       SOC_ENUM_EXT("DSP7 Firmware", wm_adsp_fw_enum[6],
+                    wm_adsp_fw_get, wm_adsp_fw_put),
 };
 EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
 
@@ -750,6 +806,29 @@ static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
                 be16_to_cpu(scratch[3]));
 }
 
+static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
+{
+       u32 scratch[2];
+       int ret;
+
+       ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1,
+                             scratch, sizeof(scratch));
+
+       if (ret) {
+               adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
+               return;
+       }
+
+       scratch[0] = be32_to_cpu(scratch[0]);
+       scratch[1] = be32_to_cpu(scratch[1]);
+
+       adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
+                scratch[0] & 0xFFFF,
+                scratch[0] >> 16,
+                scratch[1] & 0xFFFF,
+                scratch[1] >> 16);
+}
+
 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
 {
        return container_of(ext, struct wm_coeff_ctl, bytes_ext);
@@ -2435,10 +2514,17 @@ static int wm_adsp2_ena(struct wm_adsp *dsp)
        unsigned int val;
        int ret, count;
 
-       ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
-                                      ADSP2_SYS_ENA, ADSP2_SYS_ENA);
-       if (ret != 0)
-               return ret;
+       switch (dsp->rev) {
+       case 0:
+               ret = regmap_update_bits_async(dsp->regmap,
+                                              dsp->base + ADSP2_CONTROL,
+                                              ADSP2_SYS_ENA, ADSP2_SYS_ENA);
+               if (ret != 0)
+                       return ret;
+               break;
+       default:
+               break;
+       }
 
        /* Wait for the RAM to start, should be near instantaneous */
        for (count = 0; count < 10; ++count) {
@@ -2497,11 +2583,17 @@ static void wm_adsp2_boot_work(struct work_struct *work)
        if (ret != 0)
                goto err_ena;
 
-       /* Turn DSP back off until we are ready to run */
-       ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
-                                ADSP2_SYS_ENA, 0);
-       if (ret != 0)
-               goto err_ena;
+       switch (dsp->rev) {
+       case 0:
+               /* Turn DSP back off until we are ready to run */
+               ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
+                                        ADSP2_SYS_ENA, 0);
+               if (ret != 0)
+                       goto err_ena;
+               break;
+       default:
+               break;
+       }
 
        dsp->booted = true;
 
@@ -2523,12 +2615,21 @@ static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
 {
        int ret;
 
-       ret = regmap_update_bits_async(dsp->regmap,
-                                      dsp->base + ADSP2_CLOCKING,
-                                      ADSP2_CLK_SEL_MASK,
-                                      freq << ADSP2_CLK_SEL_SHIFT);
-       if (ret != 0)
-               adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
+       switch (dsp->rev) {
+       case 0:
+               ret = regmap_update_bits_async(dsp->regmap,
+                                              dsp->base + ADSP2_CLOCKING,
+                                              ADSP2_CLK_SEL_MASK,
+                                              freq << ADSP2_CLK_SEL_SHIFT);
+               if (ret) {
+                       adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
+                       return;
+               }
+               break;
+       default:
+               /* clock is handled by parent codec driver */
+               break;
+       }
 }
 
 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
@@ -2568,6 +2669,18 @@ int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
 }
 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
 
+static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
+{
+       switch (dsp->rev) {
+       case 0:
+       case 1:
+               return;
+       default:
+               regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
+                                  ADSP2_WDT_ENA_MASK, 0);
+       }
+}
+
 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
                         struct snd_kcontrol *kcontrol, int event,
                         unsigned int freq)
@@ -2640,6 +2753,8 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
                if (ret != 0)
                        goto err;
 
+               wm_adsp2_lock(dsp, dsp->lock_regions);
+
                ret = regmap_update_bits(dsp->regmap,
                                         dsp->base + ADSP2_CONTROL,
                                         ADSP2_CORE_ENA | ADSP2_START,
@@ -2663,23 +2778,49 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
                /* Tell the firmware to cleanup */
                wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
 
+               wm_adsp_stop_watchdog(dsp);
+
                /* Log firmware state, it can be useful for analysis */
-               wm_adsp2_show_fw_status(dsp);
+               switch (dsp->rev) {
+               case 0:
+                       wm_adsp2_show_fw_status(dsp);
+                       break;
+               default:
+                       wm_adsp2v2_show_fw_status(dsp);
+                       break;
+               }
 
                mutex_lock(&dsp->pwr_lock);
 
                dsp->running = false;
 
-               regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
+               regmap_update_bits(dsp->regmap,
+                                  dsp->base + ADSP2_CONTROL,
                                   ADSP2_CORE_ENA | ADSP2_START, 0);
 
                /* Make sure DMAs are quiesced */
-               regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
-               regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
-               regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
-
-               regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
-                                  ADSP2_SYS_ENA, 0);
+               switch (dsp->rev) {
+               case 0:
+                       regmap_write(dsp->regmap,
+                                    dsp->base + ADSP2_RDMA_CONFIG_1, 0);
+                       regmap_write(dsp->regmap,
+                                    dsp->base + ADSP2_WDMA_CONFIG_1, 0);
+                       regmap_write(dsp->regmap,
+                                    dsp->base + ADSP2_WDMA_CONFIG_2, 0);
+
+                       regmap_update_bits(dsp->regmap,
+                                          dsp->base + ADSP2_CONTROL,
+                                          ADSP2_SYS_ENA, 0);
+                       break;
+               default:
+                       regmap_write(dsp->regmap,
+                                    dsp->base + ADSP2_RDMA_CONFIG_1, 0);
+                       regmap_write(dsp->regmap,
+                                    dsp->base + ADSP2_WDMA_CONFIG_1, 0);
+                       regmap_write(dsp->regmap,
+                                    dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
+                       break;
+               }
 
                if (wm_adsp_fw[dsp->fw].num_caps != 0)
                        wm_adsp_buffer_free(dsp);
@@ -2732,15 +2873,22 @@ int wm_adsp2_init(struct wm_adsp *dsp)
 {
        int ret;
 
-       /*
-        * Disable the DSP memory by default when in reset for a small
-        * power saving.
-        */
-       ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
-                                ADSP2_MEM_ENA, 0);
-       if (ret != 0) {
-               adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
-               return ret;
+       switch (dsp->rev) {
+       case 0:
+               /*
+                * Disable the DSP memory by default when in reset for a small
+                * power saving.
+                */
+               ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
+                                        ADSP2_MEM_ENA, 0);
+               if (ret) {
+                       adsp_err(dsp,
+                                "Failed to clear memory retention: %d\n", ret);
+                       return ret;
+               }
+               break;
+       default:
+               break;
        }
 
        INIT_LIST_HEAD(&dsp->alg_regions);
@@ -3523,4 +3671,94 @@ int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
 }
 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
 
+int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
+{
+       struct regmap *regmap = dsp->regmap;
+       unsigned int code0, code1, lock_reg;
+
+       if (!(lock_regions & WM_ADSP2_REGION_ALL))
+               return 0;
+
+       lock_regions &= WM_ADSP2_REGION_ALL;
+       lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
+
+       while (lock_regions) {
+               code0 = code1 = 0;
+               if (lock_regions & BIT(0)) {
+                       code0 = ADSP2_LOCK_CODE_0;
+                       code1 = ADSP2_LOCK_CODE_1;
+               }
+               if (lock_regions & BIT(1)) {
+                       code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
+                       code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
+               }
+               regmap_write(regmap, lock_reg, code0);
+               regmap_write(regmap, lock_reg, code1);
+               lock_regions >>= 2;
+               lock_reg += 2;
+       }
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(wm_adsp2_lock);
+
+irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp)
+{
+       unsigned int val;
+       struct regmap *regmap = dsp->regmap;
+       int ret = 0;
+
+       ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
+       if (ret) {
+               adsp_err(dsp,
+                       "Failed to read Region Lock Ctrl register: %d\n", ret);
+               return IRQ_HANDLED;
+       }
+
+       if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
+               adsp_err(dsp, "watchdog timeout error\n");
+               wm_adsp_stop_watchdog(dsp);
+       }
+
+       if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
+               if (val & ADSP2_SLAVE_ERR_MASK)
+                       adsp_err(dsp, "bus error: slave error\n");
+               else
+                       adsp_err(dsp, "bus error: region lock error\n");
+
+               ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
+               if (ret) {
+                       adsp_err(dsp,
+                                "Failed to read Bus Err Addr register: %d\n",
+                                ret);
+                       return IRQ_HANDLED;
+               }
+
+               adsp_err(dsp, "bus error address = 0x%x\n",
+                        val & ADSP2_BUS_ERR_ADDR_MASK);
+
+               ret = regmap_read(regmap,
+                                 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
+                                 &val);
+               if (ret) {
+                       adsp_err(dsp,
+                                "Failed to read Pmem Xmem Err Addr register: %d\n",
+                                ret);
+                       return IRQ_HANDLED;
+               }
+
+               adsp_err(dsp, "xmem error address = 0x%x\n",
+                        val & ADSP2_XMEM_ERR_ADDR_MASK);
+               adsp_err(dsp, "pmem error address = 0x%x\n",
+                        (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
+                        ADSP2_PMEM_ERR_ADDR_SHIFT);
+       }
+
+       regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
+                          ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
+
+       return IRQ_HANDLED;
+}
+EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
+
 MODULE_LICENSE("GPL v2");
index 3706b11053a331856e7049bc880870f3849fabc8..41cc11c19b837cbcdd815c18794d025e2156abfd 100644 (file)
 #define WM_ADSP_COMPR_OK                 0
 #define WM_ADSP_COMPR_VOICE_TRIGGER      1
 
+#define WM_ADSP2_REGION_0 BIT(0)
+#define WM_ADSP2_REGION_1 BIT(1)
+#define WM_ADSP2_REGION_2 BIT(2)
+#define WM_ADSP2_REGION_3 BIT(3)
+#define WM_ADSP2_REGION_4 BIT(4)
+#define WM_ADSP2_REGION_5 BIT(5)
+#define WM_ADSP2_REGION_6 BIT(6)
+#define WM_ADSP2_REGION_7 BIT(7)
+#define WM_ADSP2_REGION_8 BIT(8)
+#define WM_ADSP2_REGION_9 BIT(9)
+#define WM_ADSP2_REGION_1_9 (WM_ADSP2_REGION_1 | \
+               WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \
+               WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | \
+               WM_ADSP2_REGION_6 | WM_ADSP2_REGION_7 | \
+               WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9)
+#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9)
+
 struct wm_adsp_region {
        int type;
        unsigned int base;
@@ -40,6 +57,7 @@ struct wm_adsp_compr_buf;
 
 struct wm_adsp {
        const char *part;
+       int rev;
        int num;
        int type;
        struct device *dev;
@@ -75,6 +93,8 @@ struct wm_adsp {
 
        struct mutex pwr_lock;
 
+       unsigned int lock_regions;
+
 #ifdef CONFIG_DEBUG_FS
        struct dentry *debugfs_root;
        char *wmfw_file_name;
@@ -113,6 +133,10 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
                         struct snd_kcontrol *kcontrol, int event,
                         unsigned int freq);
+
+int wm_adsp2_lock(struct wm_adsp *adsp, unsigned int regions);
+irqreturn_t wm_adsp2_bus_error(struct wm_adsp *adsp);
+
 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
                   struct snd_kcontrol *kcontrol, int event);