Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 15 Jun 2009 16:40:05 +0000 (09:40 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 15 Jun 2009 16:40:05 +0000 (09:40 -0700)
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1244 commits)
  pkt_sched: Rename PSCHED_US2NS and PSCHED_NS2US
  ipv4: Fix fib_trie rebalancing
  Bluetooth: Fix issue with uninitialized nsh.type in DTL-1 driver
  Bluetooth: Fix Kconfig issue with RFKILL integration
  PIM-SM: namespace changes
  ipv4: update ARPD help text
  net: use a deferred timer in rt_check_expire
  ieee802154: fix kconfig bool/tristate muckup
  bonding: initialization rework
  bonding: use is_zero_ether_addr
  bonding: network device names are case sensative
  bonding: elminate bad refcount code
  bonding: fix style issues
  bonding: fix destructor
  bonding: remove bonding read/write semaphore
  bonding: initialize before registration
  bonding: bond_create always called with default parameters
  x_tables: Convert printk to pr_err
  netfilter: conntrack: optional reliable conntrack event delivery
  list_nulls: add hlist_nulls_add_head and hlist_nulls_del
  ...

234 files changed:
Documentation/filesystems/nilfs2.txt
Documentation/kernel-parameters.txt
Documentation/powerpc/dts-bindings/ecm.txt [new file with mode: 0644]
Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
Documentation/powerpc/dts-bindings/fsl/esdhc.txt
Documentation/powerpc/dts-bindings/fsl/mcm.txt [new file with mode: 0644]
arch/powerpc/Kconfig
arch/powerpc/Kconfig.debug
arch/powerpc/Makefile
arch/powerpc/boot/dts/gef_ppc9a.dts
arch/powerpc/boot/dts/gef_sbc310.dts
arch/powerpc/boot/dts/gef_sbc610.dts
arch/powerpc/boot/dts/ksi8560.dts
arch/powerpc/boot/dts/mpc832x_mds.dts
arch/powerpc/boot/dts/mpc832x_rdb.dts
arch/powerpc/boot/dts/mpc8349emitx.dts
arch/powerpc/boot/dts/mpc8349emitxgp.dts
arch/powerpc/boot/dts/mpc834x_mds.dts
arch/powerpc/boot/dts/mpc836x_mds.dts
arch/powerpc/boot/dts/mpc836x_rdk.dts
arch/powerpc/boot/dts/mpc8377_mds.dts
arch/powerpc/boot/dts/mpc8378_mds.dts
arch/powerpc/boot/dts/mpc8379_mds.dts
arch/powerpc/boot/dts/mpc8536ds.dts
arch/powerpc/boot/dts/mpc8540ads.dts
arch/powerpc/boot/dts/mpc8541cds.dts
arch/powerpc/boot/dts/mpc8544ds.dts
arch/powerpc/boot/dts/mpc8548cds.dts
arch/powerpc/boot/dts/mpc8555cds.dts
arch/powerpc/boot/dts/mpc8560ads.dts
arch/powerpc/boot/dts/mpc8568mds.dts
arch/powerpc/boot/dts/mpc8569mds.dts [new file with mode: 0644]
arch/powerpc/boot/dts/mpc8572ds.dts
arch/powerpc/boot/dts/mpc8572ds_36b.dts
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
arch/powerpc/boot/dts/mpc8610_hpcd.dts
arch/powerpc/boot/dts/mpc8641_hpcn.dts
arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts [new file with mode: 0644]
arch/powerpc/boot/dts/p2020ds.dts [new file with mode: 0644]
arch/powerpc/boot/dts/sbc8349.dts
arch/powerpc/boot/dts/sbc8548.dts
arch/powerpc/boot/dts/sbc8560.dts
arch/powerpc/boot/dts/sbc8641d.dts
arch/powerpc/boot/dts/sequoia.dts
arch/powerpc/boot/dts/socrates.dts
arch/powerpc/boot/dts/stx_gp3_8560.dts
arch/powerpc/boot/dts/tqm8540.dts
arch/powerpc/boot/dts/tqm8541.dts
arch/powerpc/boot/dts/tqm8548-bigflash.dts
arch/powerpc/boot/dts/tqm8548.dts
arch/powerpc/boot/dts/tqm8555.dts
arch/powerpc/boot/dts/tqm8560.dts
arch/powerpc/boot/dts/virtex440-ml510.dts [new file with mode: 0644]
arch/powerpc/boot/dts/warp.dts
arch/powerpc/configs/40x/acadia_defconfig
arch/powerpc/configs/40x/ep405_defconfig
arch/powerpc/configs/40x/kilauea_defconfig
arch/powerpc/configs/40x/makalu_defconfig
arch/powerpc/configs/40x/virtex_defconfig
arch/powerpc/configs/44x/arches_defconfig
arch/powerpc/configs/44x/bamboo_defconfig
arch/powerpc/configs/44x/canyonlands_defconfig
arch/powerpc/configs/44x/ebony_defconfig
arch/powerpc/configs/44x/katmai_defconfig
arch/powerpc/configs/44x/rainier_defconfig
arch/powerpc/configs/44x/redwood_defconfig
arch/powerpc/configs/44x/sam440ep_defconfig
arch/powerpc/configs/44x/sequoia_defconfig
arch/powerpc/configs/44x/taishan_defconfig
arch/powerpc/configs/44x/virtex5_defconfig
arch/powerpc/include/asm/cpm2.h
arch/powerpc/include/asm/dma-mapping.h
arch/powerpc/include/asm/elf.h
arch/powerpc/include/asm/emulated_ops.h [new file with mode: 0644]
arch/powerpc/include/asm/feature-fixups.h
arch/powerpc/include/asm/lppaca.h
arch/powerpc/include/asm/machdep.h
arch/powerpc/include/asm/mmu.h
arch/powerpc/include/asm/mpc86xx.h [deleted file]
arch/powerpc/include/asm/paca.h
arch/powerpc/include/asm/page.h
arch/powerpc/include/asm/pci-bridge.h
arch/powerpc/include/asm/pgtable-ppc64.h
arch/powerpc/include/asm/ppc-opcode.h
arch/powerpc/include/asm/ppc_asm.h
arch/powerpc/include/asm/ptrace.h
arch/powerpc/include/asm/qe.h
arch/powerpc/include/asm/scatterlist.h
arch/powerpc/include/asm/swiotlb.h [new file with mode: 0644]
arch/powerpc/include/asm/system.h
arch/powerpc/include/asm/xilinx_pci.h [new file with mode: 0644]
arch/powerpc/kernel/Makefile
arch/powerpc/kernel/align.c
arch/powerpc/kernel/asm-offsets.c
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/dma-swiotlb.c [new file with mode: 0644]
arch/powerpc/kernel/dma.c
arch/powerpc/kernel/exceptions-64s.S [new file with mode: 0644]
arch/powerpc/kernel/ftrace.c
arch/powerpc/kernel/head_32.S
arch/powerpc/kernel/head_64.S
arch/powerpc/kernel/head_booke.h
arch/powerpc/kernel/irq.c
arch/powerpc/kernel/lparcfg.c
arch/powerpc/kernel/misc_64.S
arch/powerpc/kernel/paca.c
arch/powerpc/kernel/pci-common.c
arch/powerpc/kernel/pci_32.c
arch/powerpc/kernel/pci_64.c
arch/powerpc/kernel/pci_dn.c
arch/powerpc/kernel/process.c
arch/powerpc/kernel/prom.c
arch/powerpc/kernel/ptrace.c
arch/powerpc/kernel/rtas_pci.c
arch/powerpc/kernel/setup_32.c
arch/powerpc/kernel/setup_64.c
arch/powerpc/kernel/time.c
arch/powerpc/kernel/traps.c
arch/powerpc/kernel/vector.S
arch/powerpc/mm/Makefile
arch/powerpc/mm/hash_native_64.c
arch/powerpc/mm/init_64.c
arch/powerpc/mm/mmu_context_nohash.c
arch/powerpc/mm/numa.c
arch/powerpc/oprofile/op_model_fsl_emb.c
arch/powerpc/platforms/40x/Kconfig
arch/powerpc/platforms/40x/Makefile
arch/powerpc/platforms/40x/kilauea.c [deleted file]
arch/powerpc/platforms/40x/makalu.c [deleted file]
arch/powerpc/platforms/40x/ppc40x_simple.c
arch/powerpc/platforms/40x/virtex.c
arch/powerpc/platforms/44x/Kconfig
arch/powerpc/platforms/44x/Makefile
arch/powerpc/platforms/44x/virtex.c
arch/powerpc/platforms/44x/virtex_ml510.c [new file with mode: 0644]
arch/powerpc/platforms/44x/warp.c
arch/powerpc/platforms/52xx/efika.c
arch/powerpc/platforms/52xx/mpc52xx_pci.c
arch/powerpc/platforms/82xx/pq2ads.h
arch/powerpc/platforms/85xx/Kconfig
arch/powerpc/platforms/85xx/mpc85xx_ds.c
arch/powerpc/platforms/85xx/mpc85xx_mds.c
arch/powerpc/platforms/86xx/gef_ppc9a.c
arch/powerpc/platforms/86xx/gef_sbc310.c
arch/powerpc/platforms/86xx/gef_sbc610.c
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
arch/powerpc/platforms/86xx/mpc86xx_smp.c
arch/powerpc/platforms/86xx/sbc8641d.c
arch/powerpc/platforms/8xx/mpc885ads.h
arch/powerpc/platforms/Kconfig
arch/powerpc/platforms/Kconfig.cputype
arch/powerpc/platforms/cell/celleb_pci.c
arch/powerpc/platforms/cell/celleb_scc_epci.c
arch/powerpc/platforms/cell/celleb_scc_pciex.c
arch/powerpc/platforms/cell/spufs/inode.c
arch/powerpc/platforms/chrp/pci.c
arch/powerpc/platforms/fsl_uli1575.c
arch/powerpc/platforms/iseries/iommu.c
arch/powerpc/platforms/iseries/pci.c
arch/powerpc/platforms/powermac/pic.c
arch/powerpc/platforms/powermac/setup.c
arch/powerpc/platforms/ps3/smp.c
arch/powerpc/platforms/pseries/iommu.c
arch/powerpc/platforms/pseries/lpar.c
arch/powerpc/platforms/pseries/rtasd.c
arch/powerpc/platforms/pseries/setup.c
arch/powerpc/sysdev/Makefile
arch/powerpc/sysdev/cpm2.c
arch/powerpc/sysdev/fsl_msi.c
arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pci.h
arch/powerpc/sysdev/fsl_rio.c
arch/powerpc/sysdev/fsl_soc.c
arch/powerpc/sysdev/indirect_pci.c
arch/powerpc/sysdev/mpic.c
arch/powerpc/sysdev/ppc4xx_pci.c
arch/powerpc/sysdev/qe_lib/qe.c
arch/powerpc/sysdev/tsi108_pci.c
arch/powerpc/sysdev/xilinx_intc.c
arch/powerpc/sysdev/xilinx_pci.c [new file with mode: 0644]
arch/powerpc/xmon/xmon.c
drivers/char/viotape.c
drivers/i2c/busses/i2c-ibm_iic.c
drivers/macintosh/therm_adt746x.c
drivers/net/ucc_geth.c
drivers/net/ucc_geth.h
drivers/of/base.c
drivers/pci/Makefile
drivers/rapidio/rio-scan.c
drivers/regulator/Kconfig
drivers/regulator/Makefile
drivers/regulator/da903x.c
drivers/regulator/fixed.c
drivers/regulator/lp3971.c [new file with mode: 0644]
drivers/regulator/max1586.c [new file with mode: 0644]
drivers/regulator/pcf50633-regulator.c
drivers/regulator/userspace-consumer.c [new file with mode: 0644]
drivers/regulator/virtual.c
drivers/regulator/wm8350-regulator.c
drivers/regulator/wm8400-regulator.c
drivers/video/xilinxfb.c
fs/nilfs2/bmap.c
fs/nilfs2/bmap.h
fs/nilfs2/btnode.c
fs/nilfs2/btnode.h
fs/nilfs2/btree.c
fs/nilfs2/btree.h
fs/nilfs2/cpfile.c
fs/nilfs2/cpfile.h
fs/nilfs2/dat.c
fs/nilfs2/dat.h
fs/nilfs2/direct.c
fs/nilfs2/direct.h
fs/nilfs2/gcinode.c
fs/nilfs2/inode.c
fs/nilfs2/ioctl.c
fs/nilfs2/mdt.c
fs/nilfs2/nilfs.h
fs/nilfs2/recovery.c
fs/nilfs2/segbuf.c
fs/nilfs2/seglist.h [deleted file]
fs/nilfs2/segment.c
fs/nilfs2/segment.h
fs/nilfs2/sufile.c
fs/nilfs2/sufile.h
fs/nilfs2/super.c
fs/nilfs2/the_nilfs.c
fs/ramfs/inode.c
include/linux/pci_ids.h
include/linux/regulator/lp3971.h [new file with mode: 0644]
include/linux/regulator/max1586.h [new file with mode: 0644]
include/linux/regulator/userspace-consumer.h [new file with mode: 0644]

index 55c4300abfcbf88b852b4360690209d7004e8091..01539f4106763f8b9ad283d7e315a4b9c3639a73 100644 (file)
@@ -39,9 +39,8 @@ Features which NILFS2 does not support yet:
        - extended attributes
        - POSIX ACLs
        - quotas
-       - writable snapshots
-       - remote backup (CDP)
-       - data integrity
+       - fsck
+       - resize
        - defragmentation
 
 Mount options
index 5f66ba295c5d376599e6942b4f917ad38d9dab9e..ad38006307725ff2a563d9e86e78230df0879e22 100644 (file)
@@ -491,6 +491,13 @@ and is between 256 and 4096 characters. It is defined in the file
                        Also note the kernel might malfunction if you disable
                        some critical bits.
 
+       cmo_free_hint=  [PPC] Format: { yes | no }
+                       Specify whether pages are marked as being inactive
+                       when they are freed.  This is used in CMO environments
+                       to determine OS memory pressure for page stealing by
+                       a hypervisor.
+                       Default: yes
+
        code_bytes      [X86] How many bytes of object code to print
                        in an oops report.
                        Range: 0 - 8192
diff --git a/Documentation/powerpc/dts-bindings/ecm.txt b/Documentation/powerpc/dts-bindings/ecm.txt
new file mode 100644 (file)
index 0000000..f514f29
--- /dev/null
@@ -0,0 +1,64 @@
+=====================================================================
+E500 LAW & Coherency Module Device Tree Binding
+Copyright (C) 2009 Freescale Semiconductor Inc.
+=====================================================================
+
+Local Access Window (LAW) Node
+
+The LAW node represents the region of CCSR space where local access
+windows are configured.  For ECM based devices this is the first 4k
+of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
+number of local access windows as specified by fsl,num-laws.
+
+PROPERTIES
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,ecm-law"
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  The value specifies the
+          physical address offset and length of the CCSR space
+          registers.
+
+  - fsl,num-laws
+      Usage: required
+      Value type: <u32>
+      Definition: The value specifies the number of local access
+          windows for this device.
+
+=====================================================================
+
+E500 Coherency Module Node
+
+The E500 LAW node represents the region of CCSR space where ECM config
+and error reporting registers exist, this is the second 4k (0x1000)
+of CCSR space.
+
+PROPERTIES
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,CHIP-ecm", "fsl,ecm" where
+      CHIP is the processor (mpc8572, mpc8544, etc.)
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  The value specifies the
+          physical address offset and length of the CCSR space
+          registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop-encoded-array>
+
+   - interrupt-parent
+      Usage: required
+      Value type: <phandle>
+
+=====================================================================
index 78790d58dc2cb19ec93a290c4201fa94ce3bf6cf..6e37be1eeb2d2cc190780db3d01829acabbf950f 100644 (file)
@@ -17,6 +17,9 @@ Required properties:
 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
 - reg : offset and length of the device registers.
 - bus-frequency : the clock frequency for QUICC Engine.
+- fsl,qe-num-riscs: define how many RISC engines the QE has.
+- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
+  threads.
 
 Recommended properties
 - brg-frequency : the internal clock source frequency for baud-rate
index 60084655776384b8ffbf210b18d71896c5c04c4d..5093ddf900da63bd61217d97899a3ac1435e01b5 100644 (file)
@@ -5,8 +5,7 @@ for MMC, SD, and SDIO types of memory cards.
 
 Required properties:
   - compatible : should be
-    "fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors.
-    "fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors.
+    "fsl,<chip>-esdhc", "fsl,esdhc"
   - reg : should contain eSDHC registers location and length.
   - interrupts : should contain eSDHC interrupt.
   - interrupt-parent : interrupt source phandle.
@@ -15,7 +14,7 @@ Required properties:
 Example:
 
 sdhci@2e000 {
-       compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
+       compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
        reg = <0x2e000 0x1000>;
        interrupts = <42 0x8>;
        interrupt-parent = <&ipic>;
diff --git a/Documentation/powerpc/dts-bindings/fsl/mcm.txt b/Documentation/powerpc/dts-bindings/fsl/mcm.txt
new file mode 100644 (file)
index 0000000..4ceda9b
--- /dev/null
@@ -0,0 +1,64 @@
+=====================================================================
+MPX LAW & Coherency Module Device Tree Binding
+Copyright (C) 2009 Freescale Semiconductor Inc.
+=====================================================================
+
+Local Access Window (LAW) Node
+
+The LAW node represents the region of CCSR space where local access
+windows are configured.  For MCM based devices this is the first 4k
+of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
+number of local access windows as specified by fsl,num-laws.
+
+PROPERTIES
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,mcm-law"
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  The value specifies the
+          physical address offset and length of the CCSR space
+          registers.
+
+  - fsl,num-laws
+      Usage: required
+      Value type: <u32>
+      Definition: The value specifies the number of local access
+          windows for this device.
+
+=====================================================================
+
+MPX Coherency Module Node
+
+The MPX LAW node represents the region of CCSR space where MCM config
+and error reporting registers exist, this is the second 4k (0x1000)
+of CCSR space.
+
+PROPERTIES
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,CHIP-mcm", "fsl,mcm" where
+      CHIP is the processor (mpc8641, mpc8610, etc.)
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  The value specifies the
+          physical address offset and length of the CCSR space
+          registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop-encoded-array>
+
+   - interrupt-parent
+      Usage: required
+      Value type: <phandle>
+
+=====================================================================
index cdc9a6ff4be823a356521e00b7d35eb15b28e013..93a61898b25936f5d0abeef302745f7ca25b91c3 100644 (file)
@@ -42,6 +42,10 @@ config GENERIC_HARDIRQS
        bool
        default y
 
+config GENERIC_HARDIRQS_NO__DO_IRQ
+       bool
+       default y
+
 config HAVE_SETUP_PER_CPU_AREA
        def_bool PPC64
 
@@ -296,9 +300,19 @@ config IOMMU_VMERGE
 config IOMMU_HELPER
        def_bool PPC64
 
+config SWIOTLB
+       bool "SWIOTLB support"
+       default n
+       select IOMMU_HELPER
+       ---help---
+         Support for IO bounce buffering for systems without an IOMMU.
+         This allows us to DMA to the full physical address space on
+         platforms where the size of a physical address is larger
+         than the bus address.  Not all platforms support this.
+
 config PPC_NEED_DMA_SYNC_OPS
        def_bool y
-       depends on NOT_COHERENT_CACHE
+       depends on (NOT_COHERENT_CACHE || SWIOTLB)
 
 config HOTPLUG_CPU
        bool "Support for enabling/disabling CPUs"
index a1098e23221fb1debd36fc62bf54740f1829a3e4..d79a902d155af69406d9d8b9199ea4519cd44669 100644 (file)
@@ -41,6 +41,19 @@ config HCALL_STATS
          This option will add a small amount of overhead to all hypervisor
          calls.
 
+config PPC_EMULATED_STATS
+       bool "Emulated instructions tracking"
+       depends on DEBUG_FS
+       help
+         Adds code to keep track of the number of instructions that are
+         emulated by the in-kernel emulator. Counters for the various classes
+         of emulated instructions are available under
+         powerpc/emulated_instructions/ in the root of the debugfs file
+         system. Optionally (controlled by
+         powerpc/emulated_instructions/do_warn in debugfs), rate-limited
+         warnings can be printed to the console when instructions are
+         emulated.
+
 config CODE_PATCHING_SELFTEST
        bool "Run self-tests of the code-patching code."
        depends on DEBUG_KERNEL
index 551fc58c05cf7d4299acf91b71fa0f395ac75ed9..bc35f4e2b81cd0cfa65a536dfc99e877410f268e 100644 (file)
@@ -142,6 +142,7 @@ head-$(CONFIG_FSL_BOOKE)    := arch/powerpc/kernel/head_fsl_booke.o
 
 head-$(CONFIG_PPC64)           += arch/powerpc/kernel/entry_64.o
 head-$(CONFIG_PPC_FPU)         += arch/powerpc/kernel/fpu.o
+head-$(CONFIG_ALTIVEC)         += arch/powerpc/kernel/vector.o
 
 core-y                         += arch/powerpc/kernel/ \
                                   arch/powerpc/mm/ \
index 53a7a6255909b10fe8d732fa27ba0b4b0f46a3e0..910944edd886fdfa42994adedfbe4757668bd084 100644 (file)
                device_type = "soc";
                compatible = "fsl,mpc8641-soc", "simple-bus";
                ranges = <0x0 0xfef00000 0x00100000>;
-               reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index 1569117e5ddc6fd8ac0bd7f6afd53507ee5978c1..0f4c9ec2c3a619523108360f315b1fc0dd83fa73 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xfef00000 0x00100000>;
-               reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index 6582dbd36da7ff5b99de958f7bec0841ca7270db..217f8aa6672579afef8b710e733d628ad7058b20 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xfef00000 0x00100000>;
-               reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <33333333>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c1: i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
index c9cfd374bffb327ce8be53dadcd48d39935be113..bdb7fc0fa3327c53e0ccfc8bf054a12684766a20 100644 (file)
                ranges = <0x00000000 0xfdf00000 0x00100000>;
                bus-frequency = <0>;                            /* Fixed by bootwrapper */
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
index 57c595bf10717f23036a9d292b6025c26f273afa..436c9c671dd9c86edabd0ca1054490e806b7c841 100644 (file)
                reg = <0xe0100000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <198000000>;
+               fsl,qe-num-riscs = <1>;
+               fsl,qe-num-snums = <28>;
 
                muram@10000 {
                        #address-cells = <1>;
        };
 
        pci0: pci@e0008500 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x11 AD17 */
index 4319bd70a580beaa65a992eb92c6b94e91285c7c..9a0952f74b812555b3208d877618f3ff00f57891 100644 (file)
                reg = <0xe0100000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <198000000>;
+               fsl,qe-num-riscs = <1>;
+               fsl,qe-num-snums = <28>;
 
                muram@10000 {
                        #address-cells = <1>;
        };
 
        pci0: pci@e0008500 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x10 AD16 (USB) */
index 1ae38f0ddef885d32e25d13e7bee99009ddb1766..e3eeaeda91876e037561277baef3d22170dc6f93 100644 (file)
        };
 
        pci0: pci@e0008500 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x10 - SATA */
        };
 
        pci1: pci@e0008600 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x0E - MiniPCI Slot */
index 662abe1fb80488f1dd97ba7cbcdd03469471086d..eb732115f01604efa1a839a6daf3b108e9c83ea9 100644 (file)
        };
 
        pci0: pci@e0008600 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                                /* IDSEL 0x0F - PCI Slot */
index d9f0a2325fa4fddbc93f8019a94446f76d4d0cdc..a2553a6f90096bdc179c09b4877b8544df47bcdd 100644 (file)
        };
 
        pci0: pci@e0008500 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
        };
 
        pci1: pci@e0008600 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index 6e34f170fa62ba3b38a60eab064138b7b75e34f6..39ff4c829cafd125e0db34484cea04df1a393e99 100644 (file)
                reg = <0xe0100000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <396000000>;
+               fsl,qe-num-riscs = <2>;
+               fsl,qe-num-snums = <28>;
 
                muram@10000 {
                        #address-cells = <1>;
        };
 
        pci0: pci@e0008500 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index 37b789510d68bc160b191a53717a916e293ea361..6315d6fcc58aa87aeb0acc2617c9366a441a4f66 100644 (file)
                        clock-frequency = <0>;
                        bus-frequency = <0>;
                        brg-frequency = <0>;
+                       fsl,qe-num-riscs = <2>;
+                       fsl,qe-num-snums = <28>;
 
                        muram@10000 {
                                #address-cells = <1>;
index 963708017e6c304fa5c11846e3c12abc903cf482..67bb372c94511ae2dd35d9e3478e2d2f96fa48e6 100644 (file)
        };
 
        pci0: pci@e0008500 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index 651ff2f9db2d9e3ab963953752579aae34da3bf3..a955a577db810ffc68f6ad16f2e2f8f8ad19d884 100644 (file)
        };
 
        pci0: pci@e0008500 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index d6f208b8297a834de4c97a3b4521650819311e41..d266ddbfc28d0551da3e68d2424636dd566fe41e 100644 (file)
        };
 
        pci0: pci@e0008500 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index b31c5041350b18b983ef055ee1d2e79250741bb2..e781ad2f1f8aca20d0312636ac9f974b8898ab81 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xffe00000 0x100000>;
-               reg = <0xffe00000 0x1000>;
                bus-frequency = <0>;            // Filled out by uboot.
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8536-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8536-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@ffe08000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
        };
 
        pci1: pcie@ffe09000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci2: pcie@ffe0a000 {
-               cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci3: pcie@ffe0b000 {
-               cell-index = <3>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
index ddd67be10b033f6afa6683aa67654ea66f173c30..9dc292962a9a395a6b6f6daace2313f1258720c8 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
                bus-frequency = <0>;
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8540-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,8540-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index e45097f44fbde4fecc1a2df04d0a8700283e391b..9a3ad311aedfc62402338cf470a2373417332307 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8541-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,8541-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                interrupt-map = <
 
        };
 
        pci1: pci@e0009000 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index 7c6932be01978222a964fa47f932991952b92959..98e94b465662c4dfef1b8a8805721251eb157078 100644 (file)
                compatible = "simple-bus";
 
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;            // Filled out by uboot.
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8544-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,8544-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8540-pci";
                device_type = "pci";
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
        };
 
        pci1: pcie@e0009000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci2: pcie@e000a000 {
-               cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci3: pcie@e000b000 {
-               cell-index = <3>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
index 804e903532939c59caa7f1681a2c7a00fb1da89a..475be1433fe104ce4484d46454344a0c929e039e 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,8548-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x4 (PCIX Slot 2) */
        };
 
        pci1: pci@e0009000 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
        };
 
        pci2: pcie@e000a000 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index 9484f0729b1080bd2342e3efe622c3437cbcaf97..065b2f093de2527e60aef62abd9079bbcf9a5d16 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
                bus-frequency = <0>;
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,8555-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
                interrupt-map = <
 
        };
 
        pci1: pci@e0009000 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index cc2acf87d02fdac479cdb8ca99ad29c5decd1402..a5bb1ec70a5ac5805bd8c63dbaea192d995d498f 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x200>;
                bus-frequency = <330000000>;
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,8540-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
index 9d52e3b250474782ebabc42cdd18d5b410f33044..00c2bbda70134db027f1d169d9d1814c4317d545 100644 (file)
@@ -26,6 +26,7 @@
                serial1 = &serial1;
                pci0 = &pci0;
                pci1 = &pci1;
+               rapidio0 = &rio0;
        };
 
        cpus {
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x1000>;
                bus-frequency = <0>;
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8568-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,8568-memory-controller";
                        reg = <0x2000 0x1000>;
                        device_type = "open-pic";
                };
 
+               msi@41600 {
+                       compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
+                       reg = <0x41600 0x80>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <
+                               0xe0 0
+                               0xe1 0
+                               0xe2 0
+                               0xe3 0
+                               0xe4 0
+                               0xe5 0
+                               0xe6 0
+                               0xe7 0>;
+                       interrupt-parent = <&mpic>;
+               };
+
                par_io@e0100 {
                        reg = <0xe0100 0x100>;
                        device_type = "par_io";
                reg = <0xe0080000 0x480>;
                brg-frequency = <0>;
                bus-frequency = <396000000>;
+               fsl,qe-num-riscs = <2>;
+               fsl,qe-num-snums = <28>;
 
                muram@10000 {
                        #address-cells = <1>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x12 AD18 */
 
        /* PCI Express */
        pci1: pcie@e000a000 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
                                  0x0 0x800000>;
                };
        };
+
+       rio0: rapidio@e00c00000 {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
+               reg = <0xe00c0000 0x20000>;
+               ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
+               interrupts = <48 2 /* error     */
+                             49 2 /* bell_outb */
+                             50 2 /* bell_inb  */
+                             53 2 /* msg1_tx   */
+                             54 2 /* msg1_rx   */
+                             55 2 /* msg2_tx   */
+                             56 2 /* msg2_rx   */>;
+               interrupt-parent = <&mpic>;
+       };
 };
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
new file mode 100644 (file)
index 0000000..39c2927
--- /dev/null
@@ -0,0 +1,583 @@
+/*
+ * MPC8569E MDS Device Tree Source
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+       model = "MPC8569EMDS";
+       compatible = "fsl,MPC8569EMDS";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       aliases {
+               serial0 = &serial0;
+               serial1 = &serial1;
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
+               ethernet3 = &enet3;
+               pci1 = &pci1;
+               rapidio0 = &rio0;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8569@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <0x8000>;                // L1, 32K
+                       i-cache-size = <0x8000>;                // L1, 32K
+                       timebase-frequency = <0>;
+                       bus-frequency = <0>;
+                       clock-frequency = <0>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+       };
+
+       localbus@e0005000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
+               reg = <0xe0005000 0x1000>;
+               interrupts = <19 2>;
+               interrupt-parent = <&mpic>;
+
+               ranges = <0x0 0x0 0xfe000000 0x02000000
+                         0x1 0x0 0xf8000000 0x00008000
+                         0x2 0x0 0xf0000000 0x04000000
+                         0x3 0x0 0xfc000000 0x00008000
+                         0x4 0x0 0xf8008000 0x00008000
+                         0x5 0x0 0xf8010000 0x00008000>;
+
+               nor@0,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "cfi-flash";
+                       reg = <0x0 0x0 0x02000000>;
+                       bank-width = <2>;
+                       device-width = <1>;
+               };
+
+               bcsr@1,0 {
+                       compatible = "fsl,mpc8569mds-bcsr";
+                       reg = <1 0 0x8000>;
+               };
+
+               nand@3,0 {
+                       compatible = "fsl,mpc8569-fcm-nand",
+                                    "fsl,elbc-fcm-nand";
+                       reg = <3 0 0x8000>;
+               };
+
+               pib@4,0 {
+                       compatible = "fsl,mpc8569mds-pib";
+                       reg = <4 0 0x8000>;
+               };
+
+               pib@5,0 {
+                       compatible = "fsl,mpc8569mds-pib";
+                       reg = <5 0 0x8000>;
+               };
+       };
+
+       soc@e0000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "fsl,mpc8569-immr", "simple-bus";
+               ranges = <0x0 0xe0000000 0x100000>;
+               bus-frequency = <0>;
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8569-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,mpc8569-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+
+                       rtc@68 {
+                               compatible = "dallas,ds1374";
+                               reg = <0x68>;
+                       };
+               };
+
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,mpc8569-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x80000>; // L2, 512K
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8569-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8569-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8569-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8569-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               sdhci@2e000 {
+                       compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
+                       reg = <0x2e000 0x1000>;
+                       interrupts = <72 0x8>;
+                       interrupt-parent = <&mpic>;
+                       /* Filled in by U-Boot */
+                       clock-frequency = <0>;
+                       status = "disabled";
+               };
+
+               crypto@30000 {
+                       compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+                               "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+                       reg = <0x30000 0x10000>;
+                       interrupts = <45 2 58 2>;
+                       interrupt-parent = <&mpic>;
+                       fsl,num-channels = <4>;
+                       fsl,channel-fifo-len = <24>;
+                       fsl,exec-units-mask = <0xbfe>;
+                       fsl,descriptor-types-mask = <0x3ab0ebf>;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+
+               msi@41600 {
+                       compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
+                       reg = <0x41600 0x80>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <
+                               0xe0 0
+                               0xe1 0
+                               0xe2 0
+                               0xe3 0
+                               0xe4 0
+                               0xe5 0
+                               0xe6 0
+                               0xe7 0>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {
+                       compatible = "fsl,mpc8569-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+
+               par_io@e0100 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0xe0100 0x100>;
+                       ranges = <0x0 0xe0100 0x100>;
+                       device_type = "par_io";
+                       num-ports = <7>;
+
+                       qe_pio_e: gpio-controller@80 {
+                               #gpio-cells = <2>;
+                               compatible = "fsl,mpc8569-qe-pario-bank",
+                                            "fsl,mpc8323-qe-pario-bank";
+                               reg = <0x80 0x18>;
+                               gpio-controller;
+                       };
+
+                       pio1: ucc_pin@01 {
+                               pio-map = <
+                       /* port  pin  dir  open_drain  assignment  has_irq */
+                                       0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                       0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                       0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
+                                       0x0  0x0  0x1  0x0  0x3  0x0    /* ENET1_TXD0_SER1_TXD0 */
+                                       0x0  0x1  0x1  0x0  0x3  0x0    /* ENET1_TXD1_SER1_TXD1 */
+                                       0x0  0x2  0x1  0x0  0x1  0x0    /* ENET1_TXD2_SER1_TXD2 */
+                                       0x0  0x3  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
+                                       0x0  0x6  0x2  0x0  0x3  0x0    /* ENET1_RXD0_SER1_RXD0 */
+                                       0x0  0x7  0x2  0x0  0x1  0x0    /* ENET1_RXD1_SER1_RXD1 */
+                                       0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
+                                       0x0  0x9  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
+                                       0x0  0x4  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
+                                       0x0  0xc  0x2  0x0  0x3  0x0    /* ENET1_RX_DV_SER1_CTS_B */
+                                       0x2  0x8  0x2  0x0  0x1  0x0    /* ENET1_GRXCLK */
+                                       0x2  0x14 0x1  0x0  0x2  0x0>;  /* ENET1_GTXCLK */
+                       };
+
+                       pio2: ucc_pin@02 {
+                               pio-map = <
+                       /* port  pin  dir  open_drain  assignment  has_irq */
+                                       0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                       0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                       0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
+                                       0x0  0xe  0x1  0x0  0x2  0x0    /* ENET2_TXD0_SER2_TXD0 */
+                                       0x0  0xf  0x1  0x0  0x2  0x0    /* ENET2_TXD1_SER2_TXD1 */
+                                       0x0  0x10 0x1  0x0  0x1  0x0    /* ENET2_TXD2_SER2_TXD2 */
+                                       0x0  0x11 0x1  0x0  0x1  0x0    /* ENET2_TXD3_SER2_TXD3 */
+                                       0x0  0x14 0x2  0x0  0x2  0x0    /* ENET2_RXD0_SER2_RXD0 */
+                                       0x0  0x15 0x2  0x0  0x1  0x0    /* ENET2_RXD1_SER2_RXD1 */
+                                       0x0  0x16 0x2  0x0  0x1  0x0    /* ENET2_RXD2_SER2_RXD2 */
+                                       0x0  0x17 0x2  0x0  0x1  0x0    /* ENET2_RXD3_SER2_RXD3 */
+                                       0x0  0x12 0x1  0x0  0x2  0x0    /* ENET2_TX_EN_SER2_RTS_B */
+                                       0x0  0x1a 0x2  0x0  0x3  0x0    /* ENET2_RX_DV_SER2_CTS_B */
+                                       0x2  0x3  0x2  0x0  0x1  0x0    /* ENET2_GRXCLK */
+                                       0x2  0x2 0x1  0x0  0x2  0x0>;   /* ENET2_GTXCLK */
+                       };
+
+                       pio3: ucc_pin@03 {
+                               pio-map = <
+                       /* port  pin  dir  open_drain  assignment  has_irq */
+                                       0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                       0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                       0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
+                                       0x0  0x1d 0x1  0x0  0x2  0x0    /* ENET3_TXD0_SER3_TXD0 */
+                                       0x0  0x1e 0x1  0x0  0x3  0x0    /* ENET3_TXD1_SER3_TXD1 */
+                                       0x0  0x1f 0x1  0x0  0x2  0x0    /* ENET3_TXD2_SER3_TXD2 */
+                                       0x1  0x0  0x1  0x0  0x3  0x0    /* ENET3_TXD3_SER3_TXD3 */
+                                       0x1  0x3  0x2  0x0  0x3  0x0    /* ENET3_RXD0_SER3_RXD0 */
+                                       0x1  0x4  0x2  0x0  0x1  0x0    /* ENET3_RXD1_SER3_RXD1 */
+                                       0x1  0x5  0x2  0x0  0x2  0x0    /* ENET3_RXD2_SER3_RXD2 */
+                                       0x1  0x6  0x2  0x0  0x3  0x0    /* ENET3_RXD3_SER3_RXD3 */
+                                       0x1  0x1  0x1  0x0  0x1  0x0    /* ENET3_TX_EN_SER3_RTS_B */
+                                       0x1  0x9  0x2  0x0  0x3  0x0    /* ENET3_RX_DV_SER3_CTS_B */
+                                       0x2  0x9  0x2  0x0  0x2  0x0    /* ENET3_GRXCLK */
+                                       0x2  0x19 0x1  0x0  0x2  0x0>;  /* ENET3_GTXCLK */
+                       };
+
+                       pio4: ucc_pin@04 {
+                               pio-map = <
+                       /* port  pin  dir  open_drain  assignment  has_irq */
+                                       0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                       0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
+                                       0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
+                                       0x1  0xc  0x1  0x0  0x2  0x0    /* ENET4_TXD0_SER4_TXD0 */
+                                       0x1  0xd  0x1  0x0  0x2  0x0    /* ENET4_TXD1_SER4_TXD1 */
+                                       0x1  0xe  0x1  0x0  0x1  0x0    /* ENET4_TXD2_SER4_TXD2 */
+                                       0x1  0xf  0x1  0x0  0x2  0x0    /* ENET4_TXD3_SER4_TXD3 */
+                                       0x1  0x12 0x2  0x0  0x2  0x0    /* ENET4_RXD0_SER4_RXD0 */
+                                       0x1  0x13 0x2  0x0  0x1  0x0    /* ENET4_RXD1_SER4_RXD1 */
+                                       0x1  0x14 0x2  0x0  0x1  0x0    /* ENET4_RXD2_SER4_RXD2 */
+                                       0x1  0x15 0x2  0x0  0x2  0x0    /* ENET4_RXD3_SER4_RXD3 */
+                                       0x1  0x10 0x1  0x0  0x2  0x0    /* ENET4_TX_EN_SER4_RTS_B */
+                                       0x1  0x18 0x2  0x0  0x3  0x0    /* ENET4_RX_DV_SER4_CTS_B */
+                                       0x2  0x11 0x2  0x0  0x2  0x0    /* ENET4_GRXCLK */
+                                       0x2  0x18 0x1  0x0  0x2  0x0>;  /* ENET4_GTXCLK */
+                       };
+               };
+       };
+
+       qe@e0080000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "qe";
+               compatible = "fsl,qe";
+               ranges = <0x0 0xe0080000 0x40000>;
+               reg = <0xe0080000 0x480>;
+               brg-frequency = <0>;
+               bus-frequency = <0>;
+               fsl,qe-num-riscs = <4>;
+               fsl,qe-num-snums = <46>;
+
+               qeic: interrupt-controller@80 {
+                       interrupt-controller;
+                       compatible = "fsl,qe-ic";
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       reg = <0x80 0x80>;
+                       interrupts = <46 2 46 2>; //high:30 low:30
+                       interrupt-parent = <&mpic>;
+               };
+
+               spi@4c0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
+                       reg = <0x4c0 0x40>;
+                       cell-index = <0>;
+                       interrupts = <2>;
+                       interrupt-parent = <&qeic>;
+                       gpios = <&qe_pio_e 30 0>;
+                       mode = "cpu-qe";
+
+                       serial-flash@0 {
+                               compatible = "stm,m25p40";
+                               reg = <0>;
+                               spi-max-frequency = <25000000>;
+                       };
+               };
+
+               spi@500 {
+                       cell-index = <1>;
+                       compatible = "fsl,spi";
+                       reg = <0x500 0x40>;
+                       interrupts = <1>;
+                       interrupt-parent = <&qeic>;
+                       mode = "cpu";
+               };
+
+               enet0: ucc@2000 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       cell-index = <1>;
+                       reg = <0x2000 0x200>;
+                       interrupts = <32>;
+                       interrupt-parent = <&qeic>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       rx-clock-name = "none";
+                       tx-clock-name = "clk12";
+                       pio-handle = <&pio1>;
+                       phy-handle = <&qe_phy0>;
+                       phy-connection-type = "rgmii-id";
+               };
+
+               mdio@2120 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x2120 0x18>;
+                       compatible = "fsl,ucc-mdio";
+
+                       qe_phy0: ethernet-phy@07 {
+                               interrupt-parent = <&mpic>;
+                               interrupts = <1 1>;
+                               reg = <0x7>;
+                               device_type = "ethernet-phy";
+                       };
+                       qe_phy1: ethernet-phy@01 {
+                               interrupt-parent = <&mpic>;
+                               interrupts = <2 1>;
+                               reg = <0x1>;
+                               device_type = "ethernet-phy";
+                       };
+                       qe_phy2: ethernet-phy@02 {
+                               interrupt-parent = <&mpic>;
+                               interrupts = <3 1>;
+                               reg = <0x2>;
+                               device_type = "ethernet-phy";
+                       };
+                       qe_phy3: ethernet-phy@03 {
+                               interrupt-parent = <&mpic>;
+                               interrupts = <4 1>;
+                               reg = <0x3>;
+                               device_type = "ethernet-phy";
+                       };
+               };
+
+               enet2: ucc@2200 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       cell-index = <3>;
+                       reg = <0x2200 0x200>;
+                       interrupts = <34>;
+                       interrupt-parent = <&qeic>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       rx-clock-name = "none";
+                       tx-clock-name = "clk12";
+                       pio-handle = <&pio3>;
+                       phy-handle = <&qe_phy2>;
+                       phy-connection-type = "rgmii-id";
+               };
+
+               enet1: ucc@3000 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       cell-index = <2>;
+                       reg = <0x3000 0x200>;
+                       interrupts = <33>;
+                       interrupt-parent = <&qeic>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       rx-clock-name = "none";
+                       tx-clock-name = "clk17";
+                       pio-handle = <&pio2>;
+                       phy-handle = <&qe_phy1>;
+                       phy-connection-type = "rgmii-id";
+               };
+
+               enet3: ucc@3200 {
+                       device_type = "network";
+                       compatible = "ucc_geth";
+                       cell-index = <4>;
+                       reg = <0x3200 0x200>;
+                       interrupts = <35>;
+                       interrupt-parent = <&qeic>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       rx-clock-name = "none";
+                       tx-clock-name = "clk17";
+                       pio-handle = <&pio4>;
+                       phy-handle = <&qe_phy3>;
+                       phy-connection-type = "rgmii-id";
+               };
+
+               muram@10000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,qe-muram", "fsl,cpm-muram";
+                       ranges = <0x0 0x10000 0x20000>;
+
+                       data-only@0 {
+                               compatible = "fsl,qe-muram-data",
+                                            "fsl,cpm-muram-data";
+                               reg = <0x0 0x20000>;
+                       };
+               };
+
+       };
+
+       /* PCI Express */
+       pci1: pcie@e000a000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0xe000a000 0x1000>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 (PEX) */
+                       00000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       00000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       00000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+
+               interrupt-parent = <&mpic>;
+               interrupts = <26 2>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+                         0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
+               clock-frequency = <33333333>;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0xa0000000
+                                 0x2000000 0x0 0xa0000000
+                                 0x0 0x10000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x800000>;
+               };
+       };
+
+       rio0: rapidio@e00c00000 {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
+               reg = <0xe00c0000 0x20000>;
+               ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
+               interrupts = <48 2 /* error     */
+                             49 2 /* bell_outb */
+                             50 2 /* bell_inb  */
+                             53 2 /* msg1_tx   */
+                             54 2 /* msg1_rx   */
+                             55 2 /* msg2_tx   */
+                             56 2 /* msg2_rx   */>;
+               interrupt-parent = <&mpic>;
+       };
+};
index 6e79a4169088554deec5f5231c9db5ea88f5bc1b..cafc1285c140778990d04e3096f81bcc032f0ffd 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0 0xffe00000 0x100000>;
-               reg = <0 0xffe00000 0 0x1000>;  // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8572-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pcie@ffe08000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci1: pcie@ffe09000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci2: pcie@ffe0a000 {
-               cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
index dbd81a76474265134e0b2c8e3bbd30d2d05efb12..f6365db3b97dbc62eed6d565f0d21c6b886f8ebb 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xf 0xffe00000 0x100000>;
-               reg = <0xf 0xffe00000 0 0x1000>;        // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8572-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pcie@fffe08000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
                #address-cells = <3>;
                reg = <0xf 0xffe08000 0 0x1000>;
                bus-range = <0 255>;
-               ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
+               ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <0x2000000 0x0 0xc0000000
-                                 0x2000000 0x0 0xc0000000
+                       ranges = <0x2000000 0x0 0xe0000000
+                                 0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
 
                                  0x1000000 0x0 0x0
                                reg = <0x0 0x0 0x0 0x0 0x0>;
                                #size-cells = <2>;
                                #address-cells = <3>;
-                               ranges = <0x2000000 0x0 0xc0000000
-                                         0x2000000 0x0 0xc0000000
+                               ranges = <0x2000000 0x0 0xe0000000
+                                         0x2000000 0x0 0xe0000000
                                          0x0 0x20000000
 
                                          0x1000000 0x0 0x0
        };
 
        pci1: pcie@fffe09000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
                #address-cells = <3>;
                reg = <0xf 0xffe09000 0 0x1000>;
                bus-range = <0 255>;
-               ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+               ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <0x2000000 0x0 0xc0000000
-                                 0x2000000 0x0 0xc0000000
+                       ranges = <0x2000000 0x0 0xe0000000
+                                 0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
 
                                  0x1000000 0x0 0x0
        };
 
        pci2: pcie@fffe0a000 {
-               cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
                #address-cells = <3>;
                reg = <0xf 0xffe0a000 0 0x1000>;
                bus-range = <0 255>;
-               ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
+               ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <0x2000000 0x0 0xc0000000
-                                 0x2000000 0x0 0xc0000000
+                       ranges = <0x2000000 0x0 0xe0000000
+                                 0x2000000 0x0 0xe0000000
                                  0x0 0x20000000
 
                                  0x1000000 0x0 0x0
index 2bc0c71896538bb06183eb93b27f5fb618bdd4d7..5bd1011fde960d083d4ab496736eaf48388e0221 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xffe00000 0x100000>;
-               reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8572-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pcie@ffe08000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci1: pcie@ffe09000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
index 159cb3a875f0b13bf6773e7f41c1df29c69e7c3d..0efc3456e2976e6ee67673aabb5232fe69589b34 100644 (file)
@@ -58,7 +58,6 @@
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x0 0xffe00000 0x100000>;
-               reg = <0xffe00000 0x1000>;      // CCSRBAR & soc regs, remove once parse code for immrbase fixed
                bus-frequency = <0>;            // Filled out by uboot.
 
                L2: l2-cache-controller@20000 {
        };
 
        pci2: pcie@ffe0a000 {
-               cell-index = <2>;
                compatible = "fsl,mpc8548-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
index 1bd3ebe114377baf5c0c748e05f5ee4a6a31bb87..cfc2c60d1f5f4ccd9aee8484bf3d6f78db26513c 100644 (file)
                device_type = "soc";
                compatible = "fsl,mpc8610-immr", "simple-bus";
                ranges = <0x0 0xe0000000 0x00100000>;
-               reg = <0xe0000000 0x1000>;
                bus-frequency = <0>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8610-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8610-pci";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci1: pcie@e000a000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
index d72beb192460043e81e54e34270f6bee081011d3..848320e4d3c4060049e6d78b1449aa24a62b8606 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x00000000 0xffe00000 0x00100000>;
-               reg = <0xffe00000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
        };
 
        pci0: pcie@ffe08000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci1: pcie@ffe09000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
new file mode 100644 (file)
index 0000000..8be8e70
--- /dev/null
@@ -0,0 +1,609 @@
+/*
+ * MPC8641 HPCN Device Tree Source
+ *
+ * Copyright 2008-2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+       model = "MPC8641HPCN";
+       compatible = "fsl,mpc8641hpcn";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
+               ethernet3 = &enet3;
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci0 = &pci0;
+               pci1 = &pci1;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,8641@0 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <32768>;         // L1, 32K
+                       i-cache-size = <32768>;         // L1, 32K
+                       timebase-frequency = <0>;       // 33 MHz, from uboot
+                       bus-frequency = <0>;            // From uboot
+                       clock-frequency = <0>;          // From uboot
+               };
+               PowerPC,8641@1 {
+                       device_type = "cpu";
+                       reg = <1>;
+                       d-cache-line-size = <32>;       // 32 bytes
+                       i-cache-line-size = <32>;       // 32 bytes
+                       d-cache-size = <32768>;         // L1, 32K
+                       i-cache-size = <32768>;         // L1, 32K
+                       timebase-frequency = <0>;       // 33 MHz, from uboot
+                       bus-frequency = <0>;            // From uboot
+                       clock-frequency = <0>;          // From uboot
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x00000000 0x0 0x40000000>;  // 1G at 0x0
+       };
+
+       localbus@fffe05000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,mpc8641-localbus", "simple-bus";
+               reg = <0x0f 0xffe05000 0x0 0x1000>;
+               interrupts = <19 2>;
+               interrupt-parent = <&mpic>;
+
+               ranges = <0 0 0xf 0xef800000 0x00800000
+                         2 0 0xf 0xffdf8000 0x00008000
+                         3 0 0xf 0xffdf0000 0x00008000>;
+
+               flash@0,0 {
+                       compatible = "cfi-flash";
+                       reg = <0 0 0x00800000>;
+                       bank-width = <2>;
+                       device-width = <2>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       partition@0 {
+                               label = "kernel";
+                               reg = <0x00000000 0x00300000>;
+                       };
+                       partition@300000 {
+                               label = "firmware b";
+                               reg = <0x00300000 0x00100000>;
+                               read-only;
+                       };
+                       partition@400000 {
+                               label = "fs";
+                               reg = <0x00400000 0x00300000>;
+                       };
+                       partition@700000 {
+                               label = "firmware a";
+                               reg = <0x00700000 0x00100000>;
+                               read-only;
+                       };
+               };
+       };
+
+       soc8641@fffe00000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "simple-bus";
+               ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
+               bus-frequency = <0>;
+
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,mpc8641-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,mpc8641-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,mpc8641-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,mpc8641-dma-channel",
+                                               "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "TSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+                       phy-connection-type = "rgmii-id";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@0 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <10 1>;
+                                       reg = <0>;
+                                       device_type = "ethernet-phy";
+                               };
+                               phy1: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <10 1>;
+                                       reg = <1>;
+                                       device_type = "ethernet-phy";
+                               };
+                               phy2: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <10 1>;
+                                       reg = <2>;
+                                       device_type = "ethernet-phy";
+                               };
+                               phy3: ethernet-phy@3 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <10 1>;
+                                       reg = <3>;
+                                       device_type = "ethernet-phy";
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "TSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+                       phy-connection-type = "rgmii-id";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               enet2: ethernet@26000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <2>;
+                       device_type = "network";
+                       model = "TSEC";
+                       compatible = "gianfar";
+                       reg = <0x26000 0x1000>;
+                       ranges = <0x0 0x26000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <31 2 32 2 33 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi2>;
+                       phy-handle = <&phy2>;
+                       phy-connection-type = "rgmii-id";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi2: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               enet3: ethernet@27000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <3>;
+                       device_type = "network";
+                       model = "TSEC";
+                       compatible = "gianfar";
+                       reg = <0x27000 0x1000>;
+                       ranges = <0x0 0x27000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <37 2 38 2 39 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi3>;
+                       phy-handle = <&phy3>;
+                       phy-connection-type = "rgmii-id";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi3: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <28 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+
+               global-utilities@e0000 {
+                       compatible = "fsl,mpc8641-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+       };
+
+       pci0: pcie@fffe08000 {
+               cell-index = <0>;
+               compatible = "fsl,mpc8641-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0x0f 0xffe08000 0x0 0x1000>;
+               bus-range = <0x0 0xff>;
+               ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
+                         0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <24 2>;
+               interrupt-map-mask = <0xff00 0 0 7>;
+               interrupt-map = <
+                       /* IDSEL 0x11 func 0 - PCI slot 1 */
+                       0x8800 0 0 1 &mpic 2 1
+                       0x8800 0 0 2 &mpic 3 1
+                       0x8800 0 0 3 &mpic 4 1
+                       0x8800 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x11 func 1 - PCI slot 1 */
+                       0x8900 0 0 1 &mpic 2 1
+                       0x8900 0 0 2 &mpic 3 1
+                       0x8900 0 0 3 &mpic 4 1
+                       0x8900 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x11 func 2 - PCI slot 1 */
+                       0x8a00 0 0 1 &mpic 2 1
+                       0x8a00 0 0 2 &mpic 3 1
+                       0x8a00 0 0 3 &mpic 4 1
+                       0x8a00 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x11 func 3 - PCI slot 1 */
+                       0x8b00 0 0 1 &mpic 2 1
+                       0x8b00 0 0 2 &mpic 3 1
+                       0x8b00 0 0 3 &mpic 4 1
+                       0x8b00 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x11 func 4 - PCI slot 1 */
+                       0x8c00 0 0 1 &mpic 2 1
+                       0x8c00 0 0 2 &mpic 3 1
+                       0x8c00 0 0 3 &mpic 4 1
+                       0x8c00 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x11 func 5 - PCI slot 1 */
+                       0x8d00 0 0 1 &mpic 2 1
+                       0x8d00 0 0 2 &mpic 3 1
+                       0x8d00 0 0 3 &mpic 4 1
+                       0x8d00 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x11 func 6 - PCI slot 1 */
+                       0x8e00 0 0 1 &mpic 2 1
+                       0x8e00 0 0 2 &mpic 3 1
+                       0x8e00 0 0 3 &mpic 4 1
+                       0x8e00 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x11 func 7 - PCI slot 1 */
+                       0x8f00 0 0 1 &mpic 2 1
+                       0x8f00 0 0 2 &mpic 3 1
+                       0x8f00 0 0 3 &mpic 4 1
+                       0x8f00 0 0 4 &mpic 1 1
+
+                       /* IDSEL 0x12 func 0 - PCI slot 2 */
+                       0x9000 0 0 1 &mpic 3 1
+                       0x9000 0 0 2 &mpic 4 1
+                       0x9000 0 0 3 &mpic 1 1
+                       0x9000 0 0 4 &mpic 2 1
+
+                       /* IDSEL 0x12 func 1 - PCI slot 2 */
+                       0x9100 0 0 1 &mpic 3 1
+                       0x9100 0 0 2 &mpic 4 1
+                       0x9100 0 0 3 &mpic 1 1
+                       0x9100 0 0 4 &mpic 2 1
+
+                       /* IDSEL 0x12 func 2 - PCI slot 2 */
+                       0x9200 0 0 1 &mpic 3 1
+                       0x9200 0 0 2 &mpic 4 1
+                       0x9200 0 0 3 &mpic 1 1
+                       0x9200 0 0 4 &mpic 2 1
+
+                       /* IDSEL 0x12 func 3 - PCI slot 2 */
+                       0x9300 0 0 1 &mpic 3 1
+                       0x9300 0 0 2 &mpic 4 1
+                       0x9300 0 0 3 &mpic 1 1
+                       0x9300 0 0 4 &mpic 2 1
+
+                       /* IDSEL 0x12 func 4 - PCI slot 2 */
+                       0x9400 0 0 1 &mpic 3 1
+                       0x9400 0 0 2 &mpic 4 1
+                       0x9400 0 0 3 &mpic 1 1
+                       0x9400 0 0 4 &mpic 2 1
+
+                       /* IDSEL 0x12 func 5 - PCI slot 2 */
+                       0x9500 0 0 1 &mpic 3 1
+                       0x9500 0 0 2 &mpic 4 1
+                       0x9500 0 0 3 &mpic 1 1
+                       0x9500 0 0 4 &mpic 2 1
+
+                       /* IDSEL 0x12 func 6 - PCI slot 2 */
+                       0x9600 0 0 1 &mpic 3 1
+                       0x9600 0 0 2 &mpic 4 1
+                       0x9600 0 0 3 &mpic 1 1
+                       0x9600 0 0 4 &mpic 2 1
+
+                       /* IDSEL 0x12 func 7 - PCI slot 2 */
+                       0x9700 0 0 1 &mpic 3 1
+                       0x9700 0 0 2 &mpic 4 1
+                       0x9700 0 0 3 &mpic 1 1
+                       0x9700 0 0 4 &mpic 2 1
+
+                       // IDSEL 0x1c  USB
+                       0xe000 0 0 1 &i8259 12 2
+                       0xe100 0 0 2 &i8259 9 2
+                       0xe200 0 0 3 &i8259 10 2
+                       0xe300 0 0 4 &i8259 11 2
+
+                       // IDSEL 0x1d  Audio
+                       0xe800 0 0 1 &i8259 6 2
+
+                       // IDSEL 0x1e Legacy
+                       0xf000 0 0 1 &i8259 7 2
+                       0xf100 0 0 1 &i8259 7 2
+
+                       // IDSEL 0x1f IDE/SATA
+                       0xf800 0 0 1 &i8259 14 2
+                       0xf900 0 0 1 &i8259 5 2
+                       >;
+
+               pcie@0 {
+                       reg = <0 0 0 0 0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x02000000 0x0 0xe0000000
+                                 0x02000000 0x0 0xe0000000
+                                 0x0 0x20000000
+
+                                 0x01000000 0x0 0x00000000
+                                 0x01000000 0x0 0x00000000
+                                 0x0 0x00010000>;
+                       uli1575@0 {
+                               reg = <0 0 0 0 0>;
+                               #size-cells = <2>;
+                               #address-cells = <3>;
+                               ranges = <0x02000000 0x0 0xe0000000
+                                         0x02000000 0x0 0xe0000000
+                                         0x0 0x20000000
+                                         0x01000000 0x0 0x00000000
+                                         0x01000000 0x0 0x00000000
+                                         0x0 0x00010000>;
+                               isa@1e {
+                                       device_type = "isa";
+                                       #interrupt-cells = <2>;
+                                       #size-cells = <1>;
+                                       #address-cells = <2>;
+                                       reg = <0xf000 0 0 0 0>;
+                                       ranges = <1 0 0x01000000 0 0
+                                                 0x00001000>;
+                                       interrupt-parent = <&i8259>;
+
+                                       i8259: interrupt-controller@20 {
+                                               reg = <1 0x20 2
+                                                      1 0xa0 2
+                                                      1 0x4d0 2>;
+                                               interrupt-controller;
+                                               device_type = "interrupt-controller";
+                                               #address-cells = <0>;
+                                               #interrupt-cells = <2>;
+                                               compatible = "chrp,iic";
+                                               interrupts = <9 2>;
+                                               interrupt-parent = <&mpic>;
+                                       };
+
+                                       i8042@60 {
+                                               #size-cells = <0>;
+                                               #address-cells = <1>;
+                                               reg = <1 0x60 1 1 0x64 1>;
+                                               interrupts = <1 3 12 3>;
+                                               interrupt-parent =
+                                                       <&i8259>;
+
+                                               keyboard@0 {
+                                                       reg = <0>;
+                                                       compatible = "pnpPNP,303";
+                                               };
+
+                                               mouse@1 {
+                                                       reg = <1>;
+                                                       compatible = "pnpPNP,f03";
+                                               };
+                                       };
+
+                                       rtc@70 {
+                                               compatible =
+                                                       "pnpPNP,b00";
+                                               reg = <1 0x70 2>;
+                                       };
+
+                                       gpio@400 {
+                                               reg = <1 0x400 0x80>;
+                                       };
+                               };
+                       };
+               };
+
+       };
+
+       pci1: pcie@fffe09000 {
+               cell-index = <1>;
+               compatible = "fsl,mpc8641-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0x0f 0xffe09000 0x0 0x1000>;
+               bus-range = <0x0 0xff>;
+               ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
+                         0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <25 2>;
+               interrupt-map-mask = <0xf800 0 0 7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0x0000 0 0 1 &mpic 4 1
+                       0x0000 0 0 2 &mpic 5 1
+                       0x0000 0 0 3 &mpic 6 1
+                       0x0000 0 0 4 &mpic 7 1
+                       >;
+               pcie@0 {
+                       reg = <0 0 0 0 0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x02000000 0x0 0xe0000000
+                                 0x02000000 0x0 0xe0000000
+                                 0x0 0x20000000
+
+                                 0x01000000 0x0 0x00000000
+                                 0x01000000 0x0 0x00000000
+                                 0x0 0x00010000>;
+               };
+       };
+};
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
new file mode 100644 (file)
index 0000000..1101914
--- /dev/null
@@ -0,0 +1,704 @@
+/*
+ * P2020 DS Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+       model = "fsl,P2020";
+       compatible = "fsl,P2020DS";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
+               serial0 = &serial0;
+               serial1 = &serial1;
+               pci0 = &pci0;
+               pci1 = &pci1;
+               pci2 = &pci2;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               PowerPC,P2020@0 {
+                       device_type = "cpu";
+                       reg = <0x0>;
+                       next-level-cache = <&L2>;
+               };
+
+               PowerPC,P2020@1 {
+                       device_type = "cpu";
+                       reg = <0x1>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       memory {
+               device_type = "memory";
+       };
+
+       localbus@ffe05000 {
+               #address-cells = <2>;
+               #size-cells = <1>;
+               compatible = "fsl,elbc", "simple-bus";
+               reg = <0 0xffe05000 0 0x1000>;
+               interrupts = <19 2>;
+               interrupt-parent = <&mpic>;
+
+               ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
+                         0x1 0x0 0x0 0xe0000000 0x08000000
+                         0x2 0x0 0x0 0xffa00000 0x00040000
+                         0x3 0x0 0x0 0xffdf0000 0x00008000
+                         0x4 0x0 0x0 0xffa40000 0x00040000
+                         0x5 0x0 0x0 0xffa80000 0x00040000
+                         0x6 0x0 0x0 0xffac0000 0x00040000>;
+
+               nor@0,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "cfi-flash";
+                       reg = <0x0 0x0 0x8000000>;
+                       bank-width = <2>;
+                       device-width = <1>;
+
+                       ramdisk@0 {
+                               reg = <0x0 0x03000000>;
+                               read-only;
+                       };
+
+                       diagnostic@3000000 {
+                               reg = <0x03000000 0x00e00000>;
+                               read-only;
+                       };
+
+                       dink@3e00000 {
+                               reg = <0x03e00000 0x00200000>;
+                               read-only;
+                       };
+
+                       kernel@4000000 {
+                               reg = <0x04000000 0x00400000>;
+                               read-only;
+                       };
+
+                       jffs2@4400000 {
+                               reg = <0x04400000 0x03b00000>;
+                       };
+
+                       dtb@7f00000 {
+                               reg = <0x07f00000 0x00080000>;
+                               read-only;
+                       };
+
+                       u-boot@7f80000 {
+                               reg = <0x07f80000 0x00080000>;
+                               read-only;
+                       };
+               };
+
+               nand@2,0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,elbc-fcm-nand";
+                       reg = <0x2 0x0 0x40000>;
+
+                       u-boot@0 {
+                               reg = <0x0 0x02000000>;
+                               read-only;
+                       };
+
+                       jffs2@2000000 {
+                               reg = <0x02000000 0x10000000>;
+                       };
+
+                       ramdisk@12000000 {
+                               reg = <0x12000000 0x08000000>;
+                               read-only;
+                       };
+
+                       kernel@1a000000 {
+                               reg = <0x1a000000 0x04000000>;
+                       };
+
+                       dtb@1e000000 {
+                               reg = <0x1e000000 0x01000000>;
+                               read-only;
+                       };
+
+                       empty@1f000000 {
+                               reg = <0x1f000000 0x21000000>;
+                       };
+               };
+
+               nand@4,0 {
+                       compatible = "fsl,elbc-fcm-nand";
+                       reg = <0x4 0x0 0x40000>;
+               };
+
+               nand@5,0 {
+                       compatible = "fsl,elbc-fcm-nand";
+                       reg = <0x5 0x0 0x40000>;
+               };
+
+               nand@6,0 {
+                       compatible = "fsl,elbc-fcm-nand";
+                       reg = <0x6 0x0 0x40000>;
+               };
+       };
+
+       soc@ffe00000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               device_type = "soc";
+               compatible = "fsl,p2020-immr", "simple-bus";
+               ranges = <0x0 0 0xffe00000 0x100000>;
+               bus-frequency = <0>;            // Filled out by uboot.
+
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <12>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,p2020-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               memory-controller@2000 {
+                       compatible = "fsl,p2020-memory-controller";
+                       reg = <0x2000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <18 2>;
+               };
+
+               i2c@3000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <0>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3000 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               i2c@3100 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       cell-index = <1>;
+                       compatible = "fsl-i2c";
+                       reg = <0x3100 0x100>;
+                       interrupts = <43 2>;
+                       interrupt-parent = <&mpic>;
+                       dfsrr;
+               };
+
+               serial0: serial@4500 {
+                       cell-index = <0>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4500 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               serial1: serial@4600 {
+                       cell-index = <1>;
+                       device_type = "serial";
+                       compatible = "ns16550";
+                       reg = <0x4600 0x100>;
+                       clock-frequency = <0>;
+                       interrupts = <42 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               spi@7000 {
+                       compatible = "fsl,espi";
+                       reg = <0x7000 0x1000>;
+                       interrupts = <59 0x2>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               dma@c300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,eloplus-dma";
+                       reg = <0xc300 0x4>;
+                       ranges = <0x0 0xc100 0x200>;
+                       cell-index = <1>;
+                       dma-channel@0 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <76 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <77 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <78 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <79 2>;
+                       };
+               };
+
+               gpio: gpio-controller@f000 {
+                       #gpio-cells = <2>;
+                       compatible = "fsl,mpc8572-gpio";
+                       reg = <0xf000 0x100>;
+                       interrupts = <47 0x2>;
+                       interrupt-parent = <&mpic>;
+                       gpio-controller;
+               };
+
+               L2: l2-cache-controller@20000 {
+                       compatible = "fsl,p2020-l2-cache-controller";
+                       reg = <0x20000 0x1000>;
+                       cache-line-size = <32>; // 32 bytes
+                       cache-size = <0x80000>; // L2, 512k
+                       interrupt-parent = <&mpic>;
+                       interrupts = <16 2>;
+               };
+
+               dma@21300 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "fsl,eloplus-dma";
+                       reg = <0x21300 0x4>;
+                       ranges = <0x0 0x21100 0x200>;
+                       cell-index = <0>;
+                       dma-channel@0 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x0 0x80>;
+                               cell-index = <0>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <20 2>;
+                       };
+                       dma-channel@80 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x80 0x80>;
+                               cell-index = <1>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <21 2>;
+                       };
+                       dma-channel@100 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x100 0x80>;
+                               cell-index = <2>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <22 2>;
+                       };
+                       dma-channel@180 {
+                               compatible = "fsl,eloplus-dma-channel";
+                               reg = <0x180 0x80>;
+                               cell-index = <3>;
+                               interrupt-parent = <&mpic>;
+                               interrupts = <23 2>;
+                       };
+               };
+
+               usb@22000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "fsl-usb2-dr";
+                       reg = <0x22000 0x1000>;
+                       interrupt-parent = <&mpic>;
+                       interrupts = <28 0x2>;
+                       phy_type = "ulpi";
+               };
+
+               enet0: ethernet@24000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <0>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x24000 0x1000>;
+                       ranges = <0x0 0x24000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <29 2 30 2 34 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi0>;
+                       phy-handle = <&phy0>;
+                       phy-connection-type = "rgmii-id";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-mdio";
+                               reg = <0x520 0x20>;
+
+                               phy0: ethernet-phy@0 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <3 1>;
+                                       reg = <0x0>;
+                               };
+                               phy1: ethernet-phy@1 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <3 1>;
+                                       reg = <0x1>;
+                               };
+                               phy2: ethernet-phy@2 {
+                                       interrupt-parent = <&mpic>;
+                                       interrupts = <3 1>;
+                                       reg = <0x2>;
+                               };
+                               tbi0: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               enet1: ethernet@25000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <1>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x25000 0x1000>;
+                       ranges = <0x0 0x25000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <35 2 36 2 40 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi1>;
+                       phy-handle = <&phy1>;
+                       phy-connection-type = "rgmii-id";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi1: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               enet2: ethernet@26000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       cell-index = <2>;
+                       device_type = "network";
+                       model = "eTSEC";
+                       compatible = "gianfar";
+                       reg = <0x26000 0x1000>;
+                       ranges = <0x0 0x26000 0x1000>;
+                       local-mac-address = [ 00 00 00 00 00 00 ];
+                       interrupts = <31 2 32 2 33 2>;
+                       interrupt-parent = <&mpic>;
+                       tbi-handle = <&tbi2>;
+                       phy-handle = <&phy2>;
+                       phy-connection-type = "rgmii-id";
+
+                       mdio@520 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "fsl,gianfar-tbi";
+                               reg = <0x520 0x20>;
+
+                               tbi2: tbi-phy@11 {
+                                       reg = <0x11>;
+                                       device_type = "tbi-phy";
+                               };
+                       };
+               };
+
+               sdhci@2e000 {
+                       compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+                       reg = <0x2e000 0x1000>;
+                       interrupts = <72 0x2>;
+                       interrupt-parent = <&mpic>;
+                       /* Filled in by U-Boot */
+                       clock-frequency = <0>;
+               };
+
+               crypto@30000 {
+                       compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+                                    "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+                       reg = <0x30000 0x10000>;
+                       interrupts = <45 2 58 2>;
+                       interrupt-parent = <&mpic>;
+                       fsl,num-channels = <4>;
+                       fsl,channel-fifo-len = <24>;
+                       fsl,exec-units-mask = <0xbfe>;
+                       fsl,descriptor-types-mask = <0x3ab0ebf>;
+               };
+
+               mpic: pic@40000 {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x40000 0x40000>;
+                       compatible = "chrp,open-pic";
+                       device_type = "open-pic";
+               };
+
+               msi@41600 {
+                       compatible = "fsl,mpic-msi";
+                       reg = <0x41600 0x80>;
+                       msi-available-ranges = <0 0x100>;
+                       interrupts = <
+                               0xe0 0
+                               0xe1 0
+                               0xe2 0
+                               0xe3 0
+                               0xe4 0
+                               0xe5 0
+                               0xe6 0
+                               0xe7 0>;
+                       interrupt-parent = <&mpic>;
+               };
+
+               global-utilities@e0000 {        //global utilities block
+                       compatible = "fsl,p2020-guts";
+                       reg = <0xe0000 0x1000>;
+                       fsl,has-rstcr;
+               };
+       };
+
+       pci0: pcie@ffe08000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xffe08000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <24 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0000 0x0 0x0 0x1 &mpic 0x8 0x1
+                       0000 0x0 0x0 0x2 &mpic 0x9 0x1
+                       0000 0x0 0x0 0x3 &mpic 0xa 0x1
+                       0000 0x0 0x0 0x4 &mpic 0xb 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
+                                 0x0 0x20000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x10000>;
+               };
+       };
+
+       pci1: pcie@ffe09000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xffe09000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                         0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <25 2>;
+               interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+               interrupt-map = <
+
+                       // IDSEL 0x11 func 0 - PCI slot 1
+                       0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x11 func 1 - PCI slot 1
+                       0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x11 func 2 - PCI slot 1
+                       0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x11 func 3 - PCI slot 1
+                       0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x11 func 4 - PCI slot 1
+                       0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x11 func 5 - PCI slot 1
+                       0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x11 func 6 - PCI slot 1
+                       0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x11 func 7 - PCI slot 1
+                       0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
+                       0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
+
+                       // IDSEL 0x1d  Audio
+                       0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+
+                       // IDSEL 0x1e Legacy
+                       0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+                       0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+
+                       // IDSEL 0x1f IDE/SATA
+                       0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+                       0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+                       >;
+
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0xa0000000
+                                 0x2000000 0x0 0xa0000000
+                                 0x0 0x20000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x10000>;
+                       uli1575@0 {
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               #size-cells = <2>;
+                               #address-cells = <3>;
+                               ranges = <0x2000000 0x0 0xa0000000
+                                         0x2000000 0x0 0xa0000000
+                                         0x0 0x20000000
+
+                                         0x1000000 0x0 0x0
+                                         0x1000000 0x0 0x0
+                                         0x0 0x10000>;
+                               isa@1e {
+                                       device_type = "isa";
+                                       #interrupt-cells = <2>;
+                                       #size-cells = <1>;
+                                       #address-cells = <2>;
+                                       reg = <0xf000 0x0 0x0 0x0 0x0>;
+                                       ranges = <0x1 0x0 0x1000000 0x0 0x0
+                                                 0x1000>;
+                                       interrupt-parent = <&i8259>;
+
+                                       i8259: interrupt-controller@20 {
+                                               reg = <0x1 0x20 0x2
+                                                      0x1 0xa0 0x2
+                                                      0x1 0x4d0 0x2>;
+                                               interrupt-controller;
+                                               device_type = "interrupt-controller";
+                                               #address-cells = <0>;
+                                               #interrupt-cells = <2>;
+                                               compatible = "chrp,iic";
+                                               interrupts = <4 1>;
+                                               interrupt-parent = <&mpic>;
+                                       };
+
+                                       i8042@60 {
+                                               #size-cells = <0>;
+                                               #address-cells = <1>;
+                                               reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+                                               interrupts = <1 3 12 3>;
+                                               interrupt-parent =
+                                                       <&i8259>;
+
+                                               keyboard@0 {
+                                                       reg = <0x0>;
+                                                       compatible = "pnpPNP,303";
+                                               };
+
+                                               mouse@1 {
+                                                       reg = <0x1>;
+                                                       compatible = "pnpPNP,f03";
+                                               };
+                                       };
+
+                                       rtc@70 {
+                                               compatible = "pnpPNP,b00";
+                                               reg = <0x1 0x70 0x2>;
+                                       };
+
+                                       gpio@400 {
+                                               reg = <0x1 0x400 0x80>;
+                                       };
+                               };
+                       };
+               };
+
+       };
+
+       pci2: pcie@ffe0a000 {
+               compatible = "fsl,mpc8548-pcie";
+               device_type = "pci";
+               #interrupt-cells = <1>;
+               #size-cells = <2>;
+               #address-cells = <3>;
+               reg = <0 0xffe0a000 0 0x1000>;
+               bus-range = <0 255>;
+               ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+                         0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+               clock-frequency = <33333333>;
+               interrupt-parent = <&mpic>;
+               interrupts = <26 2>;
+               interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+               interrupt-map = <
+                       /* IDSEL 0x0 */
+                       0000 0x0 0x0 0x1 &mpic 0x0 0x1
+                       0000 0x0 0x0 0x2 &mpic 0x1 0x1
+                       0000 0x0 0x0 0x3 &mpic 0x2 0x1
+                       0000 0x0 0x0 0x4 &mpic 0x3 0x1
+                       >;
+               pcie@0 {
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       device_type = "pci";
+                       ranges = <0x2000000 0x0 0xc0000000
+                                 0x2000000 0x0 0xc0000000
+                                 0x0 0x20000000
+
+                                 0x1000000 0x0 0x0
+                                 0x1000000 0x0 0x0
+                                 0x0 0x10000>;
+               };
+       };
+};
index a36dbbc48694749aefc10d74fdda78270bff3245..5fb6f6684b0eda8b724c2b4c2f741f3ba59b020c 100644 (file)
        };
 
        pci0: pci@e0008500 {
-               cell-index = <1>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index b1f1416ac9988d254be577f200fc3ef59cb5abd6..9eefe00ed25358500beb19a58583a2bb3fb98a09 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x00000000 0xe0000000 0x00100000>;
-               reg = <0xe0000000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
                compatible = "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x01 (PCI-X slot) @66MHz */
        };
 
        pci2: pcie@e000a000 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index c4564b81e47305e478aa6b6591118cd4712616f9..239d57a55cf41e48b6d10fc66f40762d4bfcfaf5 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xff700000 0x00100000>;
-               reg = <0xff700000 0x00100000>;
                clock-frequency = <0>;
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8560-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@ff708000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
index e3e914e78caa2e6fdec7f5181e6a2e0a39d97a72..ee5538feb4555fa89a9198d08a5d8181fa054fbc 100644 (file)
                device_type = "soc";
                compatible = "simple-bus";
                ranges = <0x00000000 0xf8000000 0x00100000>;
-               reg = <0xf8000000 0x00001000>;  // CCSRBAR
                bus-frequency = <0>;
 
+               mcm-law@0 {
+                       compatible = "fsl,mcm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               mcm@1000 {
+                       compatible = "fsl,mpc8641-mcm", "fsl,mcm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                i2c@3000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
        };
 
        pci0: pcie@f8008000 {
-               cell-index = <0>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
        };
 
        pci1: pcie@f8009000 {
-               cell-index = <1>;
                compatible = "fsl,mpc8641-pcie";
                device_type = "pci";
                #interrupt-cells = <1>;
index 43cc68bd3192620b90bd3b2e16105263bfffcc73..739dd0da2416fa9f39d76b001ed808e626d1e13b 100644 (file)
                                        };
                                };
 
+                               ndfc@3,0 {
+                                       compatible = "ibm,ndfc";
+                                       reg = <0x00000003 0x00000000 0x00002000>;
+                                       ccr = <0x00001000>;
+                                       bank-settings = <0x80002222>;
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+
+                                       nand {
+                                               #address-cells = <1>;
+                                               #size-cells = <1>;
+
+                                               partition@0 {
+                                                       label = "u-boot";
+                                                       reg = <0x00000000 0x00084000>;
+                                               };
+                                               partition@84000 {
+                                                       label = "user";
+                                                       reg = <0x00000000 0x01f7c000>;
+                                               };
+                                       };
+                               };
                        };
 
                        UART0: serial@ef600300 {
index 7a6ae75a1e573a14afac948038fa469a662b012f..feb4ef6bd14466bd65739306dc4d231170ea873c 100644 (file)
                device_type = "soc";
 
                ranges = <0x00000000 0xe0000000 0x00100000>;
-               reg = <0xe0000000 0x00001000>;  // CCSRBAR 1M
                bus-frequency = <0>;            // Filled in by U-Boot
                compatible = "fsl,mpc8544-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8544-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8544-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
index ea6b15152de39d15e0d3474b23a1771bc6a1f3f0..b670d03fbcd91ba172bb14d14fb8db519aa2fd2c 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0 0xfdf00000 0x100000>;
-               reg = <0xfdf00000 0x1000>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8560-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@fdf08000 {
-               cell-index = <0>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
 
index b6f1fc6eb9600f7ddb72ce3d65eaaf660da74eac..71347537b83e16f08d882547c57a7bdd562aad23 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8540-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8540-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
index fa6a3d54a8a5f44860b4ecda5bc869d398e28898..b30f63753d412582caad06dbddb909e369896a9c 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8541-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8541-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
index 00f7ed7a24552295020fdc632b52527863f38709..61f25e15fd66c36492599a19aadaeff7d26eefb2 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xa0000000 0x100000>;
-               reg = <0xa0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
                compatible = "fsl,mpc8548-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@a0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
        };
 
        pci1: pcie@a000a000 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 (PEX) */
index 673e4a778ac8129753a32bdd449c93cd3038b1e6..025759c7c955cb838d8af6b43909618e2c549901 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x1000>;      // CCSRBAR
                bus-frequency = <0>;
                compatible = "fsl,mpc8548-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <10>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
        };
 
        pci1: pcie@e000a000 {
-               cell-index = <2>;
                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                interrupt-map = <
                        /* IDSEL 0x0 (PEX) */
index 6a99f1eef7ad2402b47e9ed8723121bf36dea151..95e287381836eaf6ce26cb131295a703f50e8a47 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8555-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
index b6c2d71defd3d4eb8d394d8d6900b04268d1cb56..ff70580a8f4cd800b474291b04d64788ed513075 100644 (file)
                #size-cells = <1>;
                device_type = "soc";
                ranges = <0x0 0xe0000000 0x100000>;
-               reg = <0xe0000000 0x200>;
                bus-frequency = <0>;
                compatible = "fsl,mpc8560-immr", "simple-bus";
 
+               ecm-law@0 {
+                       compatible = "fsl,ecm-law";
+                       reg = <0x0 0x1000>;
+                       fsl,num-laws = <8>;
+               };
+
+               ecm@1000 {
+                       compatible = "fsl,mpc8560-ecm", "fsl,ecm";
+                       reg = <0x1000 0x1000>;
+                       interrupts = <17 2>;
+                       interrupt-parent = <&mpic>;
+               };
+
                memory-controller@2000 {
                        compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
        };
 
        pci0: pci@e0008000 {
-               cell-index = <0>;
                #interrupt-cells = <1>;
                #size-cells = <2>;
                #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts
new file mode 100644 (file)
index 0000000..81a8dc2
--- /dev/null
@@ -0,0 +1,465 @@
+/*
+ * Xilinx ML510 Reference Design support
+ *
+ * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
+ * The reference design contains a bug which prevent PCI DMA from working
+ * properly.  A description of the bug is given in the plbv46_pci section. It
+ * needs to be fixed by the user until Xilinx updates their reference design.
+ *
+ * Copyright 2009, Roderick Colenbrander
+ */
+
+/dts-v1/;
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
+       dcr-parent = <&ppc440_0>;
+       DDR2_SDRAM_DIMM0: memory@0 {
+               device_type = "memory";
+               reg = < 0x0 0x20000000 >;
+       } ;
+       alias {
+               ethernet0 = &Hard_Ethernet_MAC;
+               serial0 = &RS232_Uart_1;
+       } ;
+       chosen {
+               bootargs = "console=ttyS0 root=/dev/ram";
+               linux,stdout-path = "/plb@0/serial@83e00000";
+       } ;
+       cpus {
+               #address-cells = <1>;
+               #cpus = <0x1>;
+               #size-cells = <0>;
+               ppc440_0: cpu@0 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       clock-frequency = <300000000>;
+                       compatible = "PowerPC,440", "ibm,ppc440";
+                       d-cache-line-size = <0x20>;
+                       d-cache-size = <0x8000>;
+                       dcr-access-method = "native";
+                       dcr-controller ;
+                       device_type = "cpu";
+                       i-cache-line-size = <0x20>;
+                       i-cache-size = <0x8000>;
+                       model = "PowerPC,440";
+                       reg = <0>;
+                       timebase-frequency = <300000000>;
+                       xlnx,apu-control = <0x2000>;
+                       xlnx,apu-udi-0 = <0x0>;
+                       xlnx,apu-udi-1 = <0x0>;
+                       xlnx,apu-udi-10 = <0x0>;
+                       xlnx,apu-udi-11 = <0x0>;
+                       xlnx,apu-udi-12 = <0x0>;
+                       xlnx,apu-udi-13 = <0x0>;
+                       xlnx,apu-udi-14 = <0x0>;
+                       xlnx,apu-udi-15 = <0x0>;
+                       xlnx,apu-udi-2 = <0x0>;
+                       xlnx,apu-udi-3 = <0x0>;
+                       xlnx,apu-udi-4 = <0x0>;
+                       xlnx,apu-udi-5 = <0x0>;
+                       xlnx,apu-udi-6 = <0x0>;
+                       xlnx,apu-udi-7 = <0x0>;
+                       xlnx,apu-udi-8 = <0x0>;
+                       xlnx,apu-udi-9 = <0x0>;
+                       xlnx,dcr-autolock-enable = <0x1>;
+                       xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
+                       xlnx,dcu-rd-noncache-plb-prio = <0x0>;
+                       xlnx,dcu-rd-touch-plb-prio = <0x0>;
+                       xlnx,dcu-rd-urgent-plb-prio = <0x0>;
+                       xlnx,dcu-wr-flush-plb-prio = <0x0>;
+                       xlnx,dcu-wr-store-plb-prio = <0x0>;
+                       xlnx,dcu-wr-urgent-plb-prio = <0x0>;
+                       xlnx,dma0-control = <0x0>;
+                       xlnx,dma0-plb-prio = <0x0>;
+                       xlnx,dma0-rxchannelctrl = <0x1010000>;
+                       xlnx,dma0-rxirqtimer = <0x3ff>;
+                       xlnx,dma0-txchannelctrl = <0x1010000>;
+                       xlnx,dma0-txirqtimer = <0x3ff>;
+                       xlnx,dma1-control = <0x0>;
+                       xlnx,dma1-plb-prio = <0x0>;
+                       xlnx,dma1-rxchannelctrl = <0x1010000>;
+                       xlnx,dma1-rxirqtimer = <0x3ff>;
+                       xlnx,dma1-txchannelctrl = <0x1010000>;
+                       xlnx,dma1-txirqtimer = <0x3ff>;
+                       xlnx,dma2-control = <0x0>;
+                       xlnx,dma2-plb-prio = <0x0>;
+                       xlnx,dma2-rxchannelctrl = <0x1010000>;
+                       xlnx,dma2-rxirqtimer = <0x3ff>;
+                       xlnx,dma2-txchannelctrl = <0x1010000>;
+                       xlnx,dma2-txirqtimer = <0x3ff>;
+                       xlnx,dma3-control = <0x0>;
+                       xlnx,dma3-plb-prio = <0x0>;
+                       xlnx,dma3-rxchannelctrl = <0x1010000>;
+                       xlnx,dma3-rxirqtimer = <0x3ff>;
+                       xlnx,dma3-txchannelctrl = <0x1010000>;
+                       xlnx,dma3-txirqtimer = <0x3ff>;
+                       xlnx,endian-reset = <0x0>;
+                       xlnx,generate-plb-timespecs = <0x1>;
+                       xlnx,icu-rd-fetch-plb-prio = <0x0>;
+                       xlnx,icu-rd-spec-plb-prio = <0x0>;
+                       xlnx,icu-rd-touch-plb-prio = <0x0>;
+                       xlnx,interconnect-imask = <0xffffffff>;
+                       xlnx,mplb-allow-lock-xfer = <0x1>;
+                       xlnx,mplb-arb-mode = <0x0>;
+                       xlnx,mplb-awidth = <0x20>;
+                       xlnx,mplb-counter = <0x500>;
+                       xlnx,mplb-dwidth = <0x80>;
+                       xlnx,mplb-max-burst = <0x8>;
+                       xlnx,mplb-native-dwidth = <0x80>;
+                       xlnx,mplb-p2p = <0x0>;
+                       xlnx,mplb-prio-dcur = <0x2>;
+                       xlnx,mplb-prio-dcuw = <0x3>;
+                       xlnx,mplb-prio-icu = <0x4>;
+                       xlnx,mplb-prio-splb0 = <0x1>;
+                       xlnx,mplb-prio-splb1 = <0x0>;
+                       xlnx,mplb-read-pipe-enable = <0x1>;
+                       xlnx,mplb-sync-tattribute = <0x0>;
+                       xlnx,mplb-wdog-enable = <0x1>;
+                       xlnx,mplb-write-pipe-enable = <0x1>;
+                       xlnx,mplb-write-post-enable = <0x1>;
+                       xlnx,num-dma = <0x0>;
+                       xlnx,pir = <0xf>;
+                       xlnx,ppc440mc-addr-base = <0x0>;
+                       xlnx,ppc440mc-addr-high = <0x1fffffff>;
+                       xlnx,ppc440mc-arb-mode = <0x0>;
+                       xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
+                       xlnx,ppc440mc-control = <0xf810008f>;
+                       xlnx,ppc440mc-max-burst = <0x8>;
+                       xlnx,ppc440mc-prio-dcur = <0x2>;
+                       xlnx,ppc440mc-prio-dcuw = <0x3>;
+                       xlnx,ppc440mc-prio-icu = <0x4>;
+                       xlnx,ppc440mc-prio-splb0 = <0x1>;
+                       xlnx,ppc440mc-prio-splb1 = <0x0>;
+                       xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
+                       xlnx,ppcdm-asyncmode = <0x0>;
+                       xlnx,ppcds-asyncmode = <0x0>;
+                       xlnx,user-reset = <0x0>;
+               } ;
+       } ;
+       plb_v46_0: plb@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
+               ranges ;
+               FLASH: flash@fc000000 {
+                       bank-width = <2>;
+                       compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
+                       reg = < 0xfc000000 0x2000000 >;
+                       xlnx,family = "virtex5";
+                       xlnx,include-datawidth-matching-0 = <0x1>;
+                       xlnx,include-datawidth-matching-1 = <0x0>;
+                       xlnx,include-datawidth-matching-2 = <0x0>;
+                       xlnx,include-datawidth-matching-3 = <0x0>;
+                       xlnx,include-negedge-ioregs = <0x0>;
+                       xlnx,include-plb-ipif = <0x1>;
+                       xlnx,include-wrbuf = <0x1>;
+                       xlnx,max-mem-width = <0x10>;
+                       xlnx,mch-native-dwidth = <0x20>;
+                       xlnx,mch-plb-clk-period-ps = <0x2710>;
+                       xlnx,mch-splb-awidth = <0x20>;
+                       xlnx,mch0-accessbuf-depth = <0x10>;
+                       xlnx,mch0-protocol = <0x0>;
+                       xlnx,mch0-rddatabuf-depth = <0x10>;
+                       xlnx,mch1-accessbuf-depth = <0x10>;
+                       xlnx,mch1-protocol = <0x0>;
+                       xlnx,mch1-rddatabuf-depth = <0x10>;
+                       xlnx,mch2-accessbuf-depth = <0x10>;
+                       xlnx,mch2-protocol = <0x0>;
+                       xlnx,mch2-rddatabuf-depth = <0x10>;
+                       xlnx,mch3-accessbuf-depth = <0x10>;
+                       xlnx,mch3-protocol = <0x0>;
+                       xlnx,mch3-rddatabuf-depth = <0x10>;
+                       xlnx,mem0-width = <0x10>;
+                       xlnx,mem1-width = <0x20>;
+                       xlnx,mem2-width = <0x20>;
+                       xlnx,mem3-width = <0x20>;
+                       xlnx,num-banks-mem = <0x1>;
+                       xlnx,num-channels = <0x2>;
+                       xlnx,priority-mode = <0x0>;
+                       xlnx,synch-mem-0 = <0x0>;
+                       xlnx,synch-mem-1 = <0x0>;
+                       xlnx,synch-mem-2 = <0x0>;
+                       xlnx,synch-mem-3 = <0x0>;
+                       xlnx,synch-pipedelay-0 = <0x2>;
+                       xlnx,synch-pipedelay-1 = <0x2>;
+                       xlnx,synch-pipedelay-2 = <0x2>;
+                       xlnx,synch-pipedelay-3 = <0x2>;
+                       xlnx,tavdv-ps-mem-0 = <0x1adb0>;
+                       xlnx,tavdv-ps-mem-1 = <0x3a98>;
+                       xlnx,tavdv-ps-mem-2 = <0x3a98>;
+                       xlnx,tavdv-ps-mem-3 = <0x3a98>;
+                       xlnx,tcedv-ps-mem-0 = <0x1adb0>;
+                       xlnx,tcedv-ps-mem-1 = <0x3a98>;
+                       xlnx,tcedv-ps-mem-2 = <0x3a98>;
+                       xlnx,tcedv-ps-mem-3 = <0x3a98>;
+                       xlnx,thzce-ps-mem-0 = <0x88b8>;
+                       xlnx,thzce-ps-mem-1 = <0x1b58>;
+                       xlnx,thzce-ps-mem-2 = <0x1b58>;
+                       xlnx,thzce-ps-mem-3 = <0x1b58>;
+                       xlnx,thzoe-ps-mem-0 = <0x1b58>;
+                       xlnx,thzoe-ps-mem-1 = <0x1b58>;
+                       xlnx,thzoe-ps-mem-2 = <0x1b58>;
+                       xlnx,thzoe-ps-mem-3 = <0x1b58>;
+                       xlnx,tlzwe-ps-mem-0 = <0x88b8>;
+                       xlnx,tlzwe-ps-mem-1 = <0x0>;
+                       xlnx,tlzwe-ps-mem-2 = <0x0>;
+                       xlnx,tlzwe-ps-mem-3 = <0x0>;
+                       xlnx,twc-ps-mem-0 = <0x1adb0>;
+                       xlnx,twc-ps-mem-1 = <0x3a98>;
+                       xlnx,twc-ps-mem-2 = <0x3a98>;
+                       xlnx,twc-ps-mem-3 = <0x3a98>;
+                       xlnx,twp-ps-mem-0 = <0x11170>;
+                       xlnx,twp-ps-mem-1 = <0x2ee0>;
+                       xlnx,twp-ps-mem-2 = <0x2ee0>;
+                       xlnx,twp-ps-mem-3 = <0x2ee0>;
+                       xlnx,xcl0-linesize = <0x4>;
+                       xlnx,xcl0-writexfer = <0x1>;
+                       xlnx,xcl1-linesize = <0x4>;
+                       xlnx,xcl1-writexfer = <0x1>;
+                       xlnx,xcl2-linesize = <0x4>;
+                       xlnx,xcl2-writexfer = <0x1>;
+                       xlnx,xcl3-linesize = <0x4>;
+                       xlnx,xcl3-writexfer = <0x1>;
+               } ;
+               Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "xlnx,compound";
+                       ethernet@81c00000 {
+                               compatible = "xlnx,xps-ll-temac-1.01.b";
+                               device_type = "network";
+                               interrupt-parent = <&xps_intc_0>;
+                               interrupts = < 8 2 >;
+                               llink-connected = <&Hard_Ethernet_MAC_fifo>;
+                               local-mac-address = [ 02 00 00 00 00 00 ];
+                               reg = < 0x81c00000 0x40 >;
+                               xlnx,bus2core-clk-ratio = <0x1>;
+                               xlnx,phy-type = <0x3>;
+                               xlnx,phyaddr = <0x1>;
+                               xlnx,rxcsum = <0x0>;
+                               xlnx,rxfifo = <0x8000>;
+                               xlnx,temac-type = <0x0>;
+                               xlnx,txcsum = <0x0>;
+                               xlnx,txfifo = <0x8000>;
+                       } ;
+               } ;
+               Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
+                       compatible = "xlnx,xps-ll-fifo-1.01.a";
+                       interrupt-parent = <&xps_intc_0>;
+                       interrupts = < 6 2 >;
+                       reg = < 0x81a00000 0x10000 >;
+                       xlnx,family = "virtex5";
+               } ;
+               IIC_EEPROM: i2c@81600000 {
+                       compatible = "xlnx,xps-iic-2.00.a";
+                       interrupt-parent = <&xps_intc_0>;
+                       interrupts = < 9 2 >;
+                       reg = < 0x81600000 0x10000 >;
+                       xlnx,clk-freq = <0x5f5e100>;
+                       xlnx,family = "virtex5";
+                       xlnx,gpo-width = <0x1>;
+                       xlnx,iic-freq = <0x186a0>;
+                       xlnx,scl-inertial-delay = <0x5>;
+                       xlnx,sda-inertial-delay = <0x5>;
+                       xlnx,ten-bit-adr = <0x0>;
+               } ;
+               LCD_OPTIONAL: gpio@81420000 {
+                       compatible = "xlnx,xps-gpio-1.00.a";
+                       reg = < 0x81420000 0x10000 >;
+                       xlnx,all-inputs = <0x0>;
+                       xlnx,all-inputs-2 = <0x0>;
+                       xlnx,dout-default = <0x0>;
+                       xlnx,dout-default-2 = <0x0>;
+                       xlnx,family = "virtex5";
+                       xlnx,gpio-width = <0xb>;
+                       xlnx,interrupt-present = <0x0>;
+                       xlnx,is-bidir = <0x1>;
+                       xlnx,is-bidir-2 = <0x1>;
+                       xlnx,is-dual = <0x0>;
+                       xlnx,tri-default = <0xffffffff>;
+                       xlnx,tri-default-2 = <0xffffffff>;
+               } ;
+               LEDs_4Bit: gpio@81400000 {
+                       compatible = "xlnx,xps-gpio-1.00.a";
+                       reg = < 0x81400000 0x10000 >;
+                       xlnx,all-inputs = <0x0>;
+                       xlnx,all-inputs-2 = <0x0>;
+                       xlnx,dout-default = <0x0>;
+                       xlnx,dout-default-2 = <0x0>;
+                       xlnx,family = "virtex5";
+                       xlnx,gpio-width = <0x4>;
+                       xlnx,interrupt-present = <0x0>;
+                       xlnx,is-bidir = <0x1>;
+                       xlnx,is-bidir-2 = <0x1>;
+                       xlnx,is-dual = <0x0>;
+                       xlnx,tri-default = <0xffffffff>;
+                       xlnx,tri-default-2 = <0xffffffff>;
+               } ;
+               RS232_Uart_1: serial@83e00000 {
+                       clock-frequency = <100000000>;
+                       compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
+                       current-speed = <9600>;
+                       device_type = "serial";
+                       interrupt-parent = <&xps_intc_0>;
+                       interrupts = < 11 2 >;
+                       reg = < 0x83e00000 0x10000 >;
+                       reg-offset = <0x1003>;
+                       reg-shift = <2>;
+                       xlnx,family = "virtex5";
+                       xlnx,has-external-rclk = <0x0>;
+                       xlnx,has-external-xin = <0x0>;
+                       xlnx,is-a-16550 = <0x1>;
+               } ;
+               SPI_EEPROM: xps-spi@feff8000 {
+                       compatible = "xlnx,xps-spi-2.00.b";
+                       interrupt-parent = <&xps_intc_0>;
+                       interrupts = < 10 2 >;
+                       reg = < 0xfeff8000 0x80 >;
+                       xlnx,family = "virtex5";
+                       xlnx,fifo-exist = <0x1>;
+                       xlnx,num-ss-bits = <0x1>;
+                       xlnx,num-transfer-bits = <0x8>;
+                       xlnx,sck-ratio = <0x80>;
+               } ;
+               SysACE_CompactFlash: sysace@83600000 {
+                       compatible = "xlnx,xps-sysace-1.00.a";
+                       interrupt-parent = <&xps_intc_0>;
+                       interrupts = < 7 2 >;
+                       reg = < 0x83600000 0x10000 >;
+                       xlnx,family = "virtex5";
+                       xlnx,mem-width = <0x10>;
+               } ;
+               plbv46_pci_0: plbv46-pci@85e00000 {
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       compatible = "xlnx,plbv46-pci-1.03.a";
+                       device_type = "pci";
+                       reg = < 0x85e00000 0x10000 >;
+
+                       /*
+                        * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
+                        * 0 which means that a read/write to the memory mapped
+                        * i/o region (which starts at 0xa0000000) for pci
+                        * bar 0 on the plb side translates to 0.
+                        * It is important to set this value to 0xa0000000, so
+                        * that inbound and outbound pci transactions work
+                        * properly including DMA.
+                        */
+                       ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
+                                 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
+
+                       #interrupt-cells = <1>;
+                       interrupt-parent = <&xps_intc_0>;
+                       interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                       interrupt-map = <
+                               /* IRQ mapping for pci slots and ALI M1533
+                                * periperhals. In total there are 5 interrupt
+                                * lines connected to a xps_intc controller.
+                                * Four of them are PCI IRQ A, B, C, D and
+                                * which correspond to respectively xpx_intc
+                                * 5, 4, 3 and 2.  The fifth interrupt line is
+                                * connected to the south bridge and this one
+                                * uses irq 1 and is active high instead of
+                                * active low.
+                                *
+                                * The M1533 contains various peripherals
+                                * including AC97 audio, a modem, USB, IDE and
+                                * some power management stuff. The modem
+                                * isn't connected on the ML510 and the power
+                                * management core also isn't used.
+                                */
+
+                               /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
+                               0x3000 0 0 1 &xps_intc_0 3 2
+                               0x3000 0 0 2 &xps_intc_0 2 2
+                               0x3000 0 0 3 &xps_intc_0 5 2
+                               0x3000 0 0 4 &xps_intc_0 4 2
+
+                               /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
+                               /*
+                               0x11800 0 0 1 &xps_intc_0 5 0 2
+                               0x11800 0 0 2 &xps_intc_0 4 0 2
+                               0x11800 0 0 3 &xps_intc_0 3 0 2
+                               0x11800 0 0 4 &xps_intc_0 2 0 2
+                               */
+
+                               /* According to the datasheet + schematic
+                                * ABCD [FPGA] of slot 5 is mapped to DABC.
+                                * Testing showed that at least A maps to B,
+                                * the mapping of the other pins is a guess
+                                * and for that reason the lines have been
+                                * commented out.
+                                */
+                               /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
+                               0x2800 0 0 1 &xps_intc_0 4 2
+                               /*
+                               0x2800 0 0 2 &xps_intc_0 3 2
+                               0x2800 0 0 3 &xps_intc_0 2 2
+                               0x2800 0 0 4 &xps_intc_0 5 2
+                               */
+
+                               /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
+                               /*
+                               0x11000 0 0 1 &xps_intc_0 4 0 2
+                               0x11000 0 0 2 &xps_intc_0 3 0 2
+                               0x11000 0 0 3 &xps_intc_0 2 0 2
+                               0x11000 0 0 4 &xps_intc_0 5 0 2
+                               */
+
+                               /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
+                               0x0800 0 0 1 &i8259 7 2
+
+                               /* IDSEL 0x1b / dev=11, bus=0 / IDE */
+                               0x5800 0 0 1 &i8259 14 2
+
+                               /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
+                               0x7800 0 0 1 &i8259 7 2
+                       >;
+                       ali_m1533 {
+                               #size-cells = <1>;
+                               #address-cells = <2>;
+                               i8259: interrupt-controller@20 {
+                                       reg = <1 0x20 2
+                                                       1 0xa0 2
+                                                       1 0x4d0 2>;
+                                       interrupt-controller;
+                                       device_type = "interrupt-controller";
+                                       #address-cells = <0>;
+                                       #interrupt-cells = <2>;
+                                       compatible = "chrp,iic";
+
+                                       /* south bridge irq is active high */
+                                       interrupts = <1 3>;
+                                       interrupt-parent = <&xps_intc_0>;
+                               };
+                       };
+               } ;
+               xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
+                       compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
+                       reg = < 0xffff0000 0x10000 >;
+                       xlnx,family = "virtex5";
+               } ;
+               xps_intc_0: interrupt-controller@81800000 {
+                       #interrupt-cells = <0x2>;
+                       compatible = "xlnx,xps-intc-1.00.a";
+                       interrupt-controller ;
+                       reg = < 0x81800000 0x10000 >;
+                       xlnx,num-intr-inputs = <0xc>;
+               } ;
+               xps_tft_0: tft@86e00000 {
+                       compatible = "xlnx,xps-tft-1.00.a";
+                       reg = < 0x86e00000 0x10000 >;
+                       xlnx,dcr-splb-slave-if = <0x1>;
+                       xlnx,default-tft-base-addr = <0x0>;
+                       xlnx,family = "virtex5";
+                       xlnx,i2c-slave-addr = <0x76>;
+                       xlnx,mplb-awidth = <0x20>;
+                       xlnx,mplb-dwidth = <0x80>;
+                       xlnx,mplb-native-dwidth = <0x40>;
+                       xlnx,mplb-smallest-slave = <0x20>;
+                       xlnx,tft-interface = <0x1>;
+               } ;
+       } ;
+}  ;
index 7e183ff9a31797e5072b940b8298d626610d6b5f..01bfb56bbe802a96d2c4a965df1651483d5d8ae6 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for PIKA Warp
  *
- * Copyright (c) 2008 PIKA Technologies
+ * Copyright (c) 2008-2009 PIKA Technologies
  *   Sean MacLennan <smaclennan@pikatech.com>
  *
  * This file is licensed under the terms of the GNU General Public
 
                                        partition@0 {
                                                label = "splash";
-                                               reg = <0x00000000 0x00020000>;
+                                               reg = <0x00000000 0x00010000>;
                                        };
                                        partition@300000 {
                                                label = "fpga";
                        };
 
                        GPIO0: gpio@ef600b00 {
-                               compatible = "ibm,gpio-440ep";
+                               compatible = "ibm,ppc4xx-gpio";
                                reg = <0xef600b00 0x00000048>;
                                #gpio-cells = <2>;
                                gpio-controller;
                        };
 
                        GPIO1: gpio@ef600c00 {
-                               compatible = "ibm,gpio-440ep";
+                               compatible = "ibm,ppc4xx-gpio";
                                reg = <0xef600c00 0x00000048>;
                                #gpio-cells = <2>;
                                gpio-controller;
+                       };
 
-                               led@31 {
-                                       compatible = "linux,gpio-led";
-                                       linux,name = ":green:";
-                                       gpios = <&GPIO1 31 0>;
-                               };              
-       
-                               led@30 {        
-                                       compatible = "linux,gpio-led";
-                                       linux,name = ":red:";
-                                       gpios = <&GPIO1 30 0>;
+                       power-leds {
+                               compatible = "gpio-leds";
+                               green {
+                                       gpios = <&GPIO1 0 0>;
+                                       default-state = "on";
+                               };
+                               red {
+                                       gpios = <&GPIO1 1 0>;
                                };
                        };
 
index a32ec8d323a05594a4fdbdb5c4de7ba054446720..173a5bb77ca1ab86ce7a6cd3cabd57ec46acbf11 100644 (file)
@@ -252,7 +252,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
index 4e9d85f39da074df3a2f93540a0451f345ad9829..e9b8495cde0cd4a5ad6861a5770712a569557394 100644 (file)
@@ -254,7 +254,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCCARD is not set
index 9917a09bad3ae3ce07d99799f853b1df14f5e745..865725effe93bdb4df4d4cc3fa5ed2544989b66e 100644 (file)
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc2
-# Tue Jan 20 08:17:52 2009
+# Linux kernel version: 2.6.30-rc7
+# Wed Jun  3 10:18:16 2009
 #
 # CONFIG_PPC64 is not set
 
@@ -27,6 +27,7 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -49,10 +50,12 @@ CONFIG_PPC_UDBG_16550=y
 # CONFIG_GENERIC_TBSYNC is not set
 CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
 # CONFIG_DEFAULT_UIMAGE is not set
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_DCR_MMIO is not set
 CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
@@ -67,9 +70,19 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_GROUP_SCHED=y
@@ -84,22 +97,24 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_STRIP_GENERATED=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -109,10 +124,12 @@ CONFIG_AIO=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
@@ -120,6 +137,7 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -132,7 +150,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
 CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -148,11 +165,6 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_FREEZER is not set
 CONFIG_PPC4xx_PCI_EXPRESS=y
 
@@ -170,7 +182,7 @@ CONFIG_KILAUEA=y
 # CONFIG_MAKALU is not set
 # CONFIG_WALNUT is not set
 # CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set
-# CONFIG_PPC40x_SIMPLE is not set
+CONFIG_PPC40x_SIMPLE=y
 CONFIG_405EX=y
 # CONFIG_IPIC is not set
 # CONFIG_MPIC is not set
@@ -228,9 +240,12 @@ CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
 CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
@@ -252,9 +267,10 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCIEPORTBUS is not set
 CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HAS_RAPIDIO is not set
@@ -272,14 +288,12 @@ CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_TASK_SIZE=0xc0000000
-CONFIG_CONSISTENT_START=0xff100000
 CONFIG_CONSISTENT_SIZE=0x00200000
 CONFIG_NET=y
 
 #
 # Networking options
 #
-CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -329,6 +343,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -341,7 +356,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
@@ -445,7 +459,6 @@ CONFIG_MTD_PHYSMAP_OF=y
 # LPDDR flash memory drivers
 #
 # CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_QINFO_PROBE is not set
 
 #
 # UBI - Unsorted block images
@@ -498,6 +511,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_I2O is not set
 # CONFIG_MACINTOSH_DRIVERS is not set
 CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -512,6 +526,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 CONFIG_IBM_NEW_EMAC=y
@@