Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 15 Jun 2009 16:40:05 +0000 (09:40 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 15 Jun 2009 16:40:05 +0000 (09:40 -0700)
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1244 commits)
  pkt_sched: Rename PSCHED_US2NS and PSCHED_NS2US
  ipv4: Fix fib_trie rebalancing
  Bluetooth: Fix issue with uninitialized nsh.type in DTL-1 driver
  Bluetooth: Fix Kconfig issue with RFKILL integration
  PIM-SM: namespace changes
  ipv4: update ARPD help text
  net: use a deferred timer in rt_check_expire
  ieee802154: fix kconfig bool/tristate muckup
  bonding: initialization rework
  bonding: use is_zero_ether_addr
  bonding: network device names are case sensative
  bonding: elminate bad refcount code
  bonding: fix style issues
  bonding: fix destructor
  bonding: remove bonding read/write semaphore
  bonding: initialize before registration
  bonding: bond_create always called with default parameters
  x_tables: Convert printk to pr_err
  netfilter: conntrack: optional reliable conntrack event delivery
  list_nulls: add hlist_nulls_add_head and hlist_nulls_del
  ...

1  2 
arch/powerpc/include/asm/qe.h
drivers/net/ucc_geth.c
drivers/net/ucc_geth.h
drivers/of/base.c
include/linux/pci_ids.h

index e0faf332c9c95c71774a7aefdb92df6462feb6ff,4459d20dc76a95d31e5c61b7bad34535c9314304..157c5ca581c8208b245c153e62f5804137ceda05
@@@ -22,7 -22,7 +22,7 @@@
  #include <asm/cpm.h>
  #include <asm/immap_qe.h>
  
 -#define QE_NUM_OF_SNUM        28
 +#define QE_NUM_OF_SNUM        256     /* There are 256 serial number in QE */
  #define QE_NUM_OF_BRGS        16
  #define QE_NUM_OF_PORTS       1024
  
@@@ -152,9 -152,6 +152,9 @@@ unsigned int qe_get_brg_clk(void)
  int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
  int qe_get_snum(void);
  void qe_put_snum(u8 snum);
 +unsigned int qe_get_num_of_risc(void);
 +unsigned int qe_get_num_of_snums(void);
 +
  /* we actually use cpm_muram implementation, define this for convenience */
  #define qe_muram_init cpm_muram_init
  #define qe_muram_alloc cpm_muram_alloc
@@@ -234,16 -231,12 +234,16 @@@ struct qe_bd 
  #define QE_ALIGNMENT_OF_PRAM  64
  
  /* RISC allocation */
 -enum qe_risc_allocation {
 -      QE_RISC_ALLOCATION_RISC1 = 1,   /* RISC 1 */
 -      QE_RISC_ALLOCATION_RISC2 = 2,   /* RISC 2 */
 -      QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3  /* Dynamically choose
 -                                                 RISC 1 or RISC 2 */
 -};
 +#define QE_RISC_ALLOCATION_RISC1      0x1  /* RISC 1 */
 +#define QE_RISC_ALLOCATION_RISC2      0x2  /* RISC 2 */
 +#define QE_RISC_ALLOCATION_RISC3      0x4  /* RISC 3 */
 +#define QE_RISC_ALLOCATION_RISC4      0x8  /* RISC 4 */
 +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2    (QE_RISC_ALLOCATION_RISC1 | \
 +                                               QE_RISC_ALLOCATION_RISC2)
 +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
 +                                       QE_RISC_ALLOCATION_RISC2 | \
 +                                       QE_RISC_ALLOCATION_RISC3 | \
 +                                       QE_RISC_ALLOCATION_RISC4)
  
  /* QE extended filtering Table Lookup Key Size */
  enum qe_fltr_tbl_lookup_key_size {
@@@ -675,6 -668,8 +675,8 @@@ struct ucc_slow_pram 
  #define UCC_GETH_UPSMR_RMM      0x00001000
  #define UCC_GETH_UPSMR_CAM      0x00000400
  #define UCC_GETH_UPSMR_BRO      0x00000200
+ #define UCC_GETH_UPSMR_SMM    0x00000080
+ #define UCC_GETH_UPSMR_SGMM   0x00000020
  
  /* UCC Transmit On Demand Register (UTODR) */
  #define UCC_SLOW_TOD  0x8000
diff --combined drivers/net/ucc_geth.c
index 9dd16c9b1a10a1c9cd29f36750a3faca359ab14d,fd6140bd9aae581609dd245b6f706910a6a15777..e2f2e91cfdd2f523094e94ad79c95e96f3466f75
@@@ -1,5 -1,5 +1,5 @@@
  /*
-  * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
+  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
   *
   * Author: Shlomi Gridish <gridish@freescale.com>
   *       Li Yang <leoli@freescale.com>
@@@ -27,6 -27,7 +27,7 @@@
  #include <linux/mii.h>
  #include <linux/phy.h>
  #include <linux/workqueue.h>
+ #include <linux/of_mdio.h>
  #include <linux/of_platform.h>
  
  #include <asm/uaccess.h>
@@@ -64,6 -65,8 +65,8 @@@
  
  static DEFINE_SPINLOCK(ugeth_lock);
  
+ static void uec_configure_serdes(struct net_device *dev);
  static struct {
        u32 msg_enable;
  } debug = { -1 };
@@@ -270,7 -273,7 +273,7 @@@ static int fill_init_enet_entries(struc
                                  u8 num_entries,
                                  u32 thread_size,
                                  u32 thread_alignment,
 -                                enum qe_risc_allocation risc,
 +                                unsigned int risc,
                                  int skip_page_for_first_entry)
  {
        u32 init_enet_offset;
  static int return_init_enet_entries(struct ucc_geth_private *ugeth,
                                    u32 *p_start,
                                    u8 num_entries,
 -                                  enum qe_risc_allocation risc,
 +                                  unsigned int risc,
                                    int skip_page_for_first_entry)
  {
        u32 init_enet_offset;
@@@ -342,7 -345,7 +345,7 @@@ static int dump_init_enet_entries(struc
                                  u32 __iomem *p_start,
                                  u8 num_entries,
                                  u32 thread_size,
 -                                enum qe_risc_allocation risc,
 +                                unsigned int risc,
                                  int skip_page_for_first_entry)
  {
        u32 init_enet_offset;
@@@ -1409,6 -1412,9 +1412,9 @@@ static int adjust_enet_interface(struc
            (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
                upsmr |= UCC_GETH_UPSMR_TBIM;
        }
+       if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
+               upsmr |= UCC_GETH_UPSMR_SGMM;
        out_be32(&uf_regs->upsmr, upsmr);
  
        /* Disable autonegotiation in tbi mode, because by default it
@@@ -1543,14 -1549,19 +1549,19 @@@ static int init_phy(struct net_device *
        priv->oldspeed = 0;
        priv->oldduplex = -1;
  
-       phydev = phy_connect(dev, ug_info->phy_bus_id, &adjust_link, 0,
-                            priv->phy_interface);
+       if (!ug_info->phy_node)
+               return 0;
  
-       if (IS_ERR(phydev)) {
+       phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
+                               priv->phy_interface);
+       if (!phydev) {
                printk("%s: Could not attach to PHY\n", dev->name);
-               return PTR_ERR(phydev);
+               return -ENODEV;
        }
  
+       if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
+               uec_configure_serdes(dev);
        phydev->supported &= (ADVERTISED_10baseT_Half |
                                 ADVERTISED_10baseT_Full |
                                 ADVERTISED_100baseT_Half |
        return 0;
  }
  
+ /* Initialize TBI PHY interface for communicating with the
+  * SERDES lynx PHY on the chip.  We communicate with this PHY
+  * through the MDIO bus on each controller, treating it as a
+  * "normal" PHY at the address found in the UTBIPA register.  We assume
+  * that the UTBIPA register is valid.  Either the MDIO bus code will set
+  * it to a value that doesn't conflict with other PHYs on the bus, or the
+  * value doesn't matter, as there are no other PHYs on the bus.
+  */
+ static void uec_configure_serdes(struct net_device *dev)
+ {
+       struct ucc_geth_private *ugeth = netdev_priv(dev);
+       if (!ugeth->tbiphy) {
+               printk(KERN_WARNING "SGMII mode requires that the device "
+                       "tree specify a tbi-handle\n");
+       return;
+       }
+       /*
+        * If the link is already up, we must already be ok, and don't need to
+        * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
+        * everything for us?  Resetting it takes the link down and requires
+        * several seconds for it to come back.
+        */
+       if (phy_read(ugeth->tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
+               return;
  
+       /* Single clk mode, mii mode off(for serdes communication) */
+       phy_write(ugeth->tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
+       phy_write(ugeth->tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
+       phy_write(ugeth->tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
+ }
  
  static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
  {
@@@ -2135,14 -2180,6 +2180,14 @@@ static int ucc_struct_init(struct ucc_g
                return -ENOMEM;
        }
  
 +      /* read the number of risc engines, update the riscTx and riscRx
 +       * if there are 4 riscs in QE
 +       */
 +      if (qe_get_num_of_risc() == 4) {
 +              ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
 +              ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
 +      }
 +
        ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
        if (!ugeth->ug_regs) {
                if (netif_msg_probe(ugeth))
@@@ -3225,7 -3262,7 +3270,7 @@@ static int ucc_geth_tx(struct net_devic
                dev->stats.tx_packets++;
  
                /* Free the sk buffer associated with this TxBD */
-               dev_kfree_skb_irq(ugeth->
+               dev_kfree_skb(ugeth->
                                  tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
                ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
                ugeth->skb_dirtytx[txQ] =
@@@ -3259,9 -3296,15 +3304,15 @@@ static int ucc_geth_poll(struct napi_st
        for (i = 0; i < ug_info->numQueuesRx; i++)
                howmany += ucc_geth_rx(ugeth, i, budget - howmany);
  
+       /* Tx event processing */
+       spin_lock(&ugeth->lock);
+       for (i = 0; i < ug_info->numQueuesTx; i++)
+               ucc_geth_tx(ugeth->ndev, i);
+       spin_unlock(&ugeth->lock);
        if (howmany < budget) {
                napi_complete(napi);
-               setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS);
+               setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
        }
  
        return howmany;
@@@ -3275,8 -3318,6 +3326,6 @@@ static irqreturn_t ucc_geth_irq_handler
        struct ucc_geth_info *ug_info;
        register u32 ucce;
        register u32 uccm;
-       register u32 tx_mask;
-       u8 i;
  
        ugeth_vdbg("%s: IN", __func__);
  
        out_be32(uccf->p_ucce, ucce);
  
        /* check for receive events that require processing */
-       if (ucce & UCCE_RX_EVENTS) {
+       if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
                if (napi_schedule_prep(&ugeth->napi)) {
-                       uccm &= ~UCCE_RX_EVENTS;
+                       uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
                        out_be32(uccf->p_uccm, uccm);
                        __napi_schedule(&ugeth->napi);
                }
        }
  
-       /* Tx event processing */
-       if (ucce & UCCE_TX_EVENTS) {
-               spin_lock(&ugeth->lock);
-               tx_mask = UCC_GETH_UCCE_TXB0;
-               for (i = 0; i < ug_info->numQueuesTx; i++) {
-                       if (ucce & tx_mask)
-                               ucc_geth_tx(dev, i);
-                       ucce &= ~tx_mask;
-                       tx_mask <<= 1;
-               }
-               spin_unlock(&ugeth->lock);
-       }
        /* Errors and other events */
        if (ucce & UCCE_OTHER) {
                if (ucce & UCC_GETH_UCCE_BSY)
@@@ -3339,6 -3367,37 +3375,37 @@@ static void ucc_netpoll(struct net_devi
  }
  #endif /* CONFIG_NET_POLL_CONTROLLER */
  
+ static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
+ {
+       struct ucc_geth_private *ugeth = netdev_priv(dev);
+       struct sockaddr *addr = p;
+       if (!is_valid_ether_addr(addr->sa_data))
+               return -EADDRNOTAVAIL;
+       memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+       /*
+        * If device is not running, we will set mac addr register
+        * when opening the device.
+        */
+       if (!netif_running(dev))
+               return 0;
+       spin_lock_irq(&ugeth->lock);
+       init_mac_station_addr_regs(dev->dev_addr[0],
+                                  dev->dev_addr[1],
+                                  dev->dev_addr[2],
+                                  dev->dev_addr[3],
+                                  dev->dev_addr[4],
+                                  dev->dev_addr[5],
+                                  &ugeth->ug_regs->macstnaddr1,
+                                  &ugeth->ug_regs->macstnaddr2);
+       spin_unlock_irq(&ugeth->lock);
+       return 0;
+ }
  /* Called when something needs to use the ethernet device */
  /* Returns 0 for success. */
  static int ucc_geth_open(struct net_device *dev)
@@@ -3506,6 -3565,8 +3573,8 @@@ static phy_interface_t to_phy_interface
                return PHY_INTERFACE_MODE_RGMII_RXID;
        if (strcasecmp(phy_connection_type, "rtbi") == 0)
                return PHY_INTERFACE_MODE_RTBI;
+       if (strcasecmp(phy_connection_type, "sgmii") == 0)
+               return PHY_INTERFACE_MODE_SGMII;
  
        return PHY_INTERFACE_MODE_MII;
  }
@@@ -3515,7 -3576,7 +3584,7 @@@ static const struct net_device_ops ucc_
        .ndo_stop               = ucc_geth_close,
        .ndo_start_xmit         = ucc_geth_start_xmit,
        .ndo_validate_addr      = eth_validate_addr,
-       .ndo_set_mac_address    = eth_mac_addr,
+       .ndo_set_mac_address    = ucc_geth_set_mac_addr,
        .ndo_change_mtu         = eth_change_mtu,
        .ndo_set_multicast_list = ucc_geth_set_multi,
        .ndo_tx_timeout         = ucc_geth_timeout,
@@@ -3528,14 -3589,12 +3597,12 @@@ static int ucc_geth_probe(struct of_dev
  {
        struct device *device = &ofdev->dev;
        struct device_node *np = ofdev->node;
-       struct device_node *mdio;
        struct net_device *dev = NULL;
        struct ucc_geth_private *ugeth = NULL;
        struct ucc_geth_info *ug_info;
        struct resource res;
        struct device_node *phy;
        int err, ucc_num, max_speed = 0;
-       const phandle *ph;
        const u32 *fixed_link;
        const unsigned int *prop;
        const char *sprop;
                PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
                PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
                PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
+               PHY_INTERFACE_MODE_SGMII,
        };
  
        ugeth_vdbg("%s: IN", __func__);
        ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
        fixed_link = of_get_property(np, "fixed-link", NULL);
        if (fixed_link) {
-               snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id),
-                        PHY_ID_FMT, "0", fixed_link[0]);
                phy = NULL;
        } else {
-               char bus_name[MII_BUS_ID_SIZE];
-               ph = of_get_property(np, "phy-handle", NULL);
-               phy = of_find_node_by_phandle(*ph);
+               phy = of_parse_phandle(np, "phy-handle", 0);
                if (phy == NULL)
                        return -ENODEV;
-               /* set the PHY address */
-               prop = of_get_property(phy, "reg", NULL);
-               if (prop == NULL)
-                       return -1;
-               /* Set the bus id */
-               mdio = of_get_parent(phy);
-               if (mdio == NULL)
-                       return -ENODEV;
-               err = of_address_to_resource(mdio, 0, &res);
-               if (err) {
-                       of_node_put(mdio);
-                       return err;
-               }
-               fsl_pq_mdio_bus_name(bus_name, mdio);
-               of_node_put(mdio);
-               snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id),
-                       "%s:%02x", bus_name, *prop);
        }
+       ug_info->phy_node = phy;
  
        /* get the phy interface type, or default to MII */
        prop = of_get_property(np, "phy-connection-type", NULL);
                case PHY_INTERFACE_MODE_RGMII_TXID:
                case PHY_INTERFACE_MODE_TBI:
                case PHY_INTERFACE_MODE_RTBI:
+               case PHY_INTERFACE_MODE_SGMII:
                        max_speed = SPEED_1000;
                        break;
                default:
                ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
                ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
                ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
 -              ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
 +
 +              /* If QE's snum number is 46 which means we need to support
 +               * 4 UECs at 1000Base-T simultaneously, we need to allocate
 +               * more Threads to Rx.
 +               */
 +              if (qe_get_num_of_snums() == 46)
 +                      ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
 +              else
 +                      ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
        }
  
        if (netif_msg_probe(&debug))
        dev->netdev_ops = &ucc_geth_netdev_ops;
        dev->watchdog_timeo = TX_TIMEOUT;
        INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
-       netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, UCC_GETH_DEV_WEIGHT);
+       netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
        dev->mtu = 1500;
  
        ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
        ugeth->ndev = dev;
        ugeth->node = np;
  
+       /* Find the TBI PHY.  If it's not there, we don't support SGMII */
+       ph = of_get_property(np, "tbi-handle", NULL);
+       if (ph) {
+               struct device_node *tbi = of_find_node_by_phandle(*ph);
+               struct of_device *ofdev;
+               struct mii_bus *bus;
+               const unsigned int *id;
+               if (!tbi)
+                       return 0;
+               mdio = of_get_parent(tbi);
+               if (!mdio)
+                       return 0;
+               ofdev = of_find_device_by_node(mdio);
+               of_node_put(mdio);
+               id = of_get_property(tbi, "reg", NULL);
+               if (!id)
+                       return 0;
+               of_node_put(tbi);
+               bus = dev_get_drvdata(&ofdev->dev);
+               if (!bus)
+                       return 0;
+               ugeth->tbiphy = bus->phy_map[*id];
+       }
        return 0;
  }
  
diff --combined drivers/net/ucc_geth.h
index 46bb1d233597c75505001b4fde3f819dc2b29d79,deb962bb68efb135b20e54486cd43252cc9f62f8..5beba4c145325bde47b553dfad20f59f6d256069
@@@ -1,5 -1,5 +1,5 @@@
  /*
-  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+  * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
   *
   * Author: Shlomi Gridish <gridish@freescale.com>
   *
@@@ -193,6 -193,31 +193,31 @@@ struct ucc_geth 
  #define       ENET_TBI_MII_JD         0x10    /* Jitter diagnostics */
  #define       ENET_TBI_MII_TBICON     0x11    /* TBI control */
  
+ /* TBI MDIO register bit fields*/
+ #define TBISR_LSTATUS          0x0004
+ #define TBICON_CLK_SELECT       0x0020
+ #define TBIANA_ASYMMETRIC_PAUSE 0x0100
+ #define TBIANA_SYMMETRIC_PAUSE  0x0080
+ #define TBIANA_HALF_DUPLEX      0x0040
+ #define TBIANA_FULL_DUPLEX      0x0020
+ #define TBICR_PHY_RESET         0x8000
+ #define TBICR_ANEG_ENABLE       0x1000
+ #define TBICR_RESTART_ANEG      0x0200
+ #define TBICR_FULL_DUPLEX       0x0100
+ #define TBICR_SPEED1_SET        0x0040
+ #define TBIANA_SETTINGS ( \
+               TBIANA_ASYMMETRIC_PAUSE \
+               | TBIANA_SYMMETRIC_PAUSE \
+               | TBIANA_FULL_DUPLEX \
+               )
+ #define TBICR_SETTINGS ( \
+               TBICR_PHY_RESET \
+               | TBICR_ANEG_ENABLE \
+               | TBICR_FULL_DUPLEX \
+               | TBICR_SPEED1_SET \
+               )
  /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
  #define MACCFG1_FLOW_RX                         0x00000020    /* Flow Control
                                                                   Rx */
@@@ -852,7 -877,6 +877,6 @@@ struct ucc_geth_hardware_statistics 
  /* Driver definitions */
  #define TX_BD_RING_LEN                          0x10
  #define RX_BD_RING_LEN                          0x10
- #define UCC_GETH_DEV_WEIGHT                     TX_BD_RING_LEN
  
  #define TX_RING_MOD_MASK(size)                  (size-1)
  #define RX_RING_MOD_MASK(size)                  (size-1)
@@@ -1100,7 -1124,7 +1124,7 @@@ struct ucc_geth_info 
        u32 eventRegMask;
        u16 pausePeriod;
        u16 extensionField;
-       char phy_bus_id[BUS_ID_SIZE];
+       struct device_node *phy_node;
        u8 weightfactor[NUM_TX_QUEUES];
        u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
        u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
        enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
        enum ucc_geth_num_of_threads numThreadsTx;
        enum ucc_geth_num_of_threads numThreadsRx;
 -      enum qe_risc_allocation riscTx;
 -      enum qe_risc_allocation riscRx;
 +      unsigned int riscTx;
 +      unsigned int riscRx;
  };
  
  /* structure representing UCC GETH */
@@@ -1189,6 -1213,7 +1213,7 @@@ struct ucc_geth_private 
  
        struct ugeth_mii_info *mii_info;
        struct phy_device *phydev;
+       struct phy_device *tbiphy;
        phy_interface_t phy_interface;
        int max_speed;
        uint32_t msg_enable;
diff --combined drivers/of/base.c
index 391f91c0bf55d54d3d696270f1e4419b196fb6ba,ddf224d456b2602efeaa9cdefebf72300f9bdf13..69f85c07d17fc24718861b41618c6a8c0c493183
@@@ -447,7 -447,6 +447,7 @@@ struct of_modalias_table 
  static struct of_modalias_table of_modalias_table[] = {
        { "fsl,mcu-mpc8349emitx", "mcu-mpc8349emitx" },
        { "mmc-spi-slot", "mmc_spi" },
 +      { "stm,m25p40", "m25p80" },
  };
  
  /**
@@@ -495,6 -494,30 +495,30 @@@ int of_modalias_node(struct device_nod
  }
  EXPORT_SYMBOL_GPL(of_modalias_node);
  
+ /**
+  * of_parse_phandle - Resolve a phandle property to a device_node pointer
+  * @np: Pointer to device node holding phandle property
+  * @phandle_name: Name of property holding a phandle value
+  * @index: For properties holding a table of phandles, this is the index into
+  *         the table
+  *
+  * Returns the device_node pointer with refcount incremented.  Use
+  * of_node_put() on it when done.
+  */
+ struct device_node *
+ of_parse_phandle(struct device_node *np, const char *phandle_name, int index)
+ {
+       const phandle *phandle;
+       int size;
+       phandle = of_get_property(np, phandle_name, &size);
+       if ((!phandle) || (size < sizeof(*phandle) * (index + 1)))
+               return NULL;
+       return of_find_node_by_phandle(phandle[index]);
+ }
+ EXPORT_SYMBOL(of_parse_phandle);
  /**
   * of_parse_phandles_with_args - Find a node pointed by phandle in a list
   * @np:               pointer to a device tree node containing a list
diff --combined include/linux/pci_ids.h
index a3df4a2bba6333f7853f971516310d3e7dfe1892,3435c1f3effa3450de05c7eab57a7896d9586497..aa01d38c9971a745feec8bb70b0fa93392dcc08e
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS       0x0034
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE 0x0035
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA        0x0036
- #define PCI_DEVICE_ID_NVIDIA_NVENET_10                0x0037
- #define PCI_DEVICE_ID_NVIDIA_NVENET_11                0x0038
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2       0x003e
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800       0x0041
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE 0x0053
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA        0x0054
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2       0x0055
- #define PCI_DEVICE_ID_NVIDIA_NVENET_8         0x0056
- #define PCI_DEVICE_ID_NVIDIA_NVENET_9         0x0057
  #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO      0x0059
  #define PCI_DEVICE_ID_NVIDIA_CK804_PCIE               0x005d
  #define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS    0x0064
  #define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE      0x0065
- #define PCI_DEVICE_ID_NVIDIA_NVENET_2         0x0066
  #define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM               0x0069
  #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO               0x006a
  #define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS   0x0084
  #define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE     0x0085
- #define PCI_DEVICE_ID_NVIDIA_NVENET_4         0x0086
  #define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM      0x0089
  #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO                0x008a
- #define PCI_DEVICE_ID_NVIDIA_NVENET_5         0x008c
  #define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA    0x008e
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT   0x0090
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX 0x0091
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3          0x00d1
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS    0x00d4
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE      0x00d5
- #define PCI_DEVICE_ID_NVIDIA_NVENET_3         0x00d6
  #define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM               0x00d9
  #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO               0x00da
- #define PCI_DEVICE_ID_NVIDIA_NVENET_7         0x00df
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3S         0x00e1
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA    0x00e3
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS   0x00e4
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE     0x00e5
- #define PCI_DEVICE_ID_NVIDIA_NVENET_6         0x00e6
  #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO               0x00ea
  #define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2   0x00ee
  #define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS     0x01b4
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE               0x01bc
  #define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM               0x01c1
- #define PCI_DEVICE_ID_NVIDIA_NVENET_1         0x01c3
  #define PCI_DEVICE_ID_NVIDIA_NFORCE2          0x01e0
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3         0x0200
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1               0x0201
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE 0x036E
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA        0x037E
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2       0x037F
- #define PCI_DEVICE_ID_NVIDIA_NVENET_12                0x0268
- #define PCI_DEVICE_ID_NVIDIA_NVENET_13                0x0269
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
  #define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
  #define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
- #define PCI_DEVICE_ID_NVIDIA_NVENET_14              0x0372
  #define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
- #define PCI_DEVICE_ID_NVIDIA_NVENET_16              0x03E5
- #define PCI_DEVICE_ID_NVIDIA_NVENET_17              0x03E6
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA      0x03E7
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS           0x03EB
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE       0x03EC
- #define PCI_DEVICE_ID_NVIDIA_NVENET_18              0x03EE
- #define PCI_DEVICE_ID_NVIDIA_NVENET_19              0x03EF
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2     0x03F6
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3     0x03F7
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS           0x0446
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE     0x0448
- #define PCI_DEVICE_ID_NVIDIA_NVENET_20              0x0450
- #define PCI_DEVICE_ID_NVIDIA_NVENET_21              0x0451
- #define PCI_DEVICE_ID_NVIDIA_NVENET_22              0x0452
- #define PCI_DEVICE_ID_NVIDIA_NVENET_23              0x0453
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS     0x0542
- #define PCI_DEVICE_ID_NVIDIA_NVENET_24              0x054C
- #define PCI_DEVICE_ID_NVIDIA_NVENET_25              0x054D
- #define PCI_DEVICE_ID_NVIDIA_NVENET_26              0x054E
- #define PCI_DEVICE_ID_NVIDIA_NVENET_27              0x054F
- #define PCI_DEVICE_ID_NVIDIA_NVENET_28              0x07DC
- #define PCI_DEVICE_ID_NVIDIA_NVENET_29              0x07DD
- #define PCI_DEVICE_ID_NVIDIA_NVENET_30              0x07DE
- #define PCI_DEVICE_ID_NVIDIA_NVENET_31              0x07DF
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE       0x0560
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE       0x056C
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS    0x0752
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE       0x0759
- #define PCI_DEVICE_ID_NVIDIA_NVENET_32              0x0760
- #define PCI_DEVICE_ID_NVIDIA_NVENET_33              0x0761
- #define PCI_DEVICE_ID_NVIDIA_NVENET_34              0x0762
- #define PCI_DEVICE_ID_NVIDIA_NVENET_35              0x0763
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS     0x07D8
  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS     0x0AA2
- #define PCI_DEVICE_ID_NVIDIA_NVENET_36              0x0AB0
- #define PCI_DEVICE_ID_NVIDIA_NVENET_37              0x0AB1
- #define PCI_DEVICE_ID_NVIDIA_NVENET_38              0x0AB2
- #define PCI_DEVICE_ID_NVIDIA_NVENET_39              0x0AB3
  
  #define PCI_VENDOR_ID_IMS             0x10e0
  #define PCI_DEVICE_ID_IMS_TT128               0x9128
  #define PCI_SUBDEVICE_ID_CCD_SWYX4S   0xB540
  #define PCI_SUBDEVICE_ID_CCD_JH4S20   0xB550
  #define PCI_SUBDEVICE_ID_CCD_IOB8ST_1 0xB552
+ #define PCI_SUBDEVICE_ID_CCD_JHSE1    0xB553
+ #define PCI_SUBDEVICE_ID_CCD_JH8S     0xB55B
  #define PCI_SUBDEVICE_ID_CCD_BN4S     0xB560
  #define PCI_SUBDEVICE_ID_CCD_BN8S     0xB562
  #define PCI_SUBDEVICE_ID_CCD_BNE1     0xB563
  #define PCI_DEVICE_ID_MPC8547E                0x0018
  #define PCI_DEVICE_ID_MPC8545E                0x0019
  #define PCI_DEVICE_ID_MPC8545         0x001a
 +#define PCI_DEVICE_ID_MPC8569E                0x0061
 +#define PCI_DEVICE_ID_MPC8569         0x0060
  #define PCI_DEVICE_ID_MPC8568E                0x0020
  #define PCI_DEVICE_ID_MPC8568         0x0021
  #define PCI_DEVICE_ID_MPC8567E                0x0022
  #define PCI_DEVICE_ID_MPC8572         0x0041
  #define PCI_DEVICE_ID_MPC8536E                0x0050
  #define PCI_DEVICE_ID_MPC8536         0x0051
 +#define PCI_DEVICE_ID_P2020E          0x0070
 +#define PCI_DEVICE_ID_P2020           0x0071
  #define PCI_DEVICE_ID_MPC8641         0x7010
  #define PCI_DEVICE_ID_MPC8641D                0x7011
  #define PCI_DEVICE_ID_MPC8610         0x7018
  
  #define PCI_VENDOR_ID_QMI             0x1a32
  
+ #define PCI_VENDOR_ID_AZWAVE          0x1a3b
  #define PCI_VENDOR_ID_TEKRAM          0x1de1
  #define PCI_DEVICE_ID_TEKRAM_DC290    0xdc29