x86: coding style fixes to arch/x86/kernel/cpu/mcheck/p6.c

Before:
   total: 16 errors, 13 warnings, 122 lines checked
After:
   total: 0 errors, 0 warnings, 122 lines checked

No code changed:

arch/x86/kernel/cpu/mcheck/p6.o:

   text	   data	    bss	    dec	    hex	filename
   1082	      0	      8	   1090	    442	p6.o.before
   1082	      0	      8	   1090	    442	p6.o.after

md5:
   4e283fbc1b68240f1724d9725007d379  p6.o.before.asm
   4e283fbc1b68240f1724d9725007d379  p6.o.after.asm

Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/cpu/mcheck/p6.c b/arch/x86/kernel/cpu/mcheck/p6.c
index 74342604d30e1d3d6eb98567103d63b046f6a8f2..62efc9c2b3af480e12eac82cd8881553b1b8b98a 100644 (file)
--- a/arch/x86/kernel/cpu/mcheck/p6.c
+++ b/arch/x86/kernel/cpu/mcheck/p6.c
@@ -9,23 +9,23 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 

-#include <asm/processor.h> 
+#include <asm/processor.h>

 #include <asm/system.h>
 #include <asm/msr.h>
 
 #include "mce.h"
 
 /* Machine Check Handler For PII/PIII */
 #include <asm/system.h>
 #include <asm/msr.h>
 
 #include "mce.h"
 
 /* Machine Check Handler For PII/PIII */

-static void intel_machine_check(struct pt_regs * regs, long error_code)
+static void intel_machine_check(struct pt_regs *regs, long error_code)

 {
 {

-       int recover=1;
+       int recover = 1;

        u32 alow, ahigh, high, low;
        u32 mcgstl, mcgsth;
        int i;
 
        u32 alow, ahigh, high, low;
        u32 mcgstl, mcgsth;
        int i;
 

-       rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+       rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);

        if (mcgstl & (1<<0))    /* Recoverable ? */
        if (mcgstl & (1<<0))    /* Recoverable ? */

-               recover=0;
+               recover = 0;

 
        printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
                smp_processor_id(), mcgsth, mcgstl);
 
        printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
                smp_processor_id(), mcgsth, mcgstl);


@@ -55,30 +55,30 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
        }
 
        if (recover & 2)
        }
 
        if (recover & 2)

-               panic ("CPU context corrupt");
+               panic("CPU context corrupt");

        if (recover & 1)
        if (recover & 1)

-               panic ("Unable to continue");
+               panic("Unable to continue");

 
 

-       printk (KERN_EMERG "Attempting to continue.\n");
-       /* 
-        * Do not clear the MSR_IA32_MCi_STATUS if the error is not 
+       printk(KERN_EMERG "Attempting to continue.\n");
+       /*
+        * Do not clear the MSR_IA32_MCi_STATUS if the error is not

         * recoverable/continuable.This will allow BIOS to look at the MSRs
         * for errors if the OS could not log the error.
         */
         * recoverable/continuable.This will allow BIOS to look at the MSRs
         * for errors if the OS could not log the error.
         */

-       for (i=0; i<nr_mce_banks; i++) {
+       for (i = 0; i < nr_mce_banks; i++) {

                unsigned int msr;
                msr = MSR_IA32_MC0_STATUS+i*4;
                unsigned int msr;
                msr = MSR_IA32_MC0_STATUS+i*4;

-               rdmsr (msr,low, high);
+               rdmsr(msr, low, high);

                if (high & (1<<31)) {
                        /* Clear it */
                if (high & (1<<31)) {
                        /* Clear it */

-                       wrmsr (msr, 0UL, 0UL);
+                       wrmsr(msr, 0UL, 0UL);

                        /* Serialize */
                        wmb();
                        add_taint(TAINT_MACHINE_CHECK);
                }
        }
        mcgstl &= ~(1<<2);
                        /* Serialize */
                        wmb();
                        add_taint(TAINT_MACHINE_CHECK);
                }
        }
        mcgstl &= ~(1<<2);

-       wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+       wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);

 }
 
 /* Set up machine check reporting for processors with Intel style MCE */
 }
 
 /* Set up machine check reporting for processors with Intel style MCE */


@@ -86,21 +86,21 @@ void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
 {
        u32 l, h;
        int i;
 {
        u32 l, h;
        int i;

-       
+

        /* Check for MCE support */
        if (!cpu_has(c, X86_FEATURE_MCE))
                return;
 
        /* Check for PPro style MCA */
        /* Check for MCE support */
        if (!cpu_has(c, X86_FEATURE_MCE))
                return;
 
        /* Check for PPro style MCA */

-       if (!cpu_has(c, X86_FEATURE_MCA))
+       if (!cpu_has(c, X86_FEATURE_MCA))

                return;
 
        /* Ok machine check is available */
        machine_check_vector = intel_machine_check;
        wmb();
 
                return;
 
        /* Ok machine check is available */
        machine_check_vector = intel_machine_check;
        wmb();
 

-       printk (KERN_INFO "Intel machine check architecture supported.\n");
-       rdmsr (MSR_IA32_MCG_CAP, l, h);
+       printk(KERN_INFO "Intel machine check architecture supported.\n");
+       rdmsr(MSR_IA32_MCG_CAP, l, h);

        if (l & (1<<8)) /* Control register present ? */
                wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
        nr_mce_banks = l & 0xff;
        if (l & (1<<8)) /* Control register present ? */
                wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
        nr_mce_banks = l & 0xff;


@@ -110,13 +110,13 @@ void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
         * - MC0_CTL should not be written
         * - Status registers on all banks should be cleared on reset
         */
         * - MC0_CTL should not be written
         * - Status registers on all banks should be cleared on reset
         */

-       for (i=1; i<nr_mce_banks; i++)
-               wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+       for (i = 1; i < nr_mce_banks; i++)
+               wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);

 
 

-       for (i=0; i<nr_mce_banks; i++)
-               wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+       for (i = 0; i < nr_mce_banks; i++)
+               wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);

 
 

-       set_in_cr4 (X86_CR4_MCE);
-       printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+       set_in_cr4(X86_CR4_MCE);
+       printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",

                smp_processor_id());
 }
                smp_processor_id());
 }