Revert "net/mlx5: Add MPCNT register infrastructure"

This reverts commit 7f503169cabd70c1f13b9279c50eca7dfb9a7d51.

Fixes: 7f503169cabd ("net/mlx5: Add MPCNT register infrastructure")
Signed-off-by: Gal Pressman <galp@mellanox.com>
Reported-by: Jesper Dangaard Brouer <brouer@redhat.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 9f489365b3d39c2400fd2fd19099ca98803396d7..52b437431c6a642b04d33da532cfcd722c69fa0f 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1071,11 +1071,6 @@ enum {
        MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
 };
 
        MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
 };
 

-enum {
-       MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP       = 0x0,
-       MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
-};
-

 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
 {
        if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
 {
        if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)

diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 0ae55361e674be4c08ffa33c3c69573eee7bf99b..735b36335f297e8babe3f1d2089acd11a735bc43 100644 (file)
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -123,7 +123,6 @@ enum {
        MLX5_REG_HOST_ENDIANNESS = 0x7004,
        MLX5_REG_MCIA            = 0x9014,
        MLX5_REG_MLCR            = 0x902b,
        MLX5_REG_HOST_ENDIANNESS = 0x7004,
        MLX5_REG_MCIA            = 0x9014,
        MLX5_REG_MLCR            = 0x902b,

-       MLX5_REG_MPCNT           = 0x9051,

 };
 
 enum mlx5_dcbx_oper_mode {
 };
 
 enum mlx5_dcbx_oper_mode {

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 57bec544e20a81070d999fc59253d0774a4c6c3b..a852e9db6f0d5ec809cfc0e5245d1ee3fff7c36b 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1757,80 +1757,6 @@ struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
        u8         reserved_at_4c0[0x300];
 };
 
        u8         reserved_at_4c0[0x300];
 };
 

-struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
-       u8         life_time_counter_high[0x20];
-
-       u8         life_time_counter_low[0x20];
-
-       u8         rx_errors[0x20];
-
-       u8         tx_errors[0x20];
-
-       u8         l0_to_recovery_eieos[0x20];
-
-       u8         l0_to_recovery_ts[0x20];
-
-       u8         l0_to_recovery_framing[0x20];
-
-       u8         l0_to_recovery_retrain[0x20];
-
-       u8         crc_error_dllp[0x20];
-
-       u8         crc_error_tlp[0x20];
-
-       u8         reserved_at_140[0x680];
-};
-
-struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits {
-       u8         life_time_counter_high[0x20];
-
-       u8         life_time_counter_low[0x20];
-
-       u8         time_to_boot_image_start[0x20];
-
-       u8         time_to_link_image[0x20];
-
-       u8         calibration_time[0x20];
-
-       u8         time_to_first_perst[0x20];
-
-       u8         time_to_detect_state[0x20];
-
-       u8         time_to_l0[0x20];
-
-       u8         time_to_crs_en[0x20];
-
-       u8         time_to_plastic_image_start[0x20];
-
-       u8         time_to_iron_image_start[0x20];
-
-       u8         perst_handler[0x20];
-
-       u8         times_in_l1[0x20];
-
-       u8         times_in_l23[0x20];
-
-       u8         dl_down[0x20];
-
-       u8         config_cycle1usec[0x20];
-
-       u8         config_cycle2to7usec[0x20];
-
-       u8         config_cycle_8to15usec[0x20];
-
-       u8         config_cycle_16_to_63usec[0x20];
-
-       u8         config_cycle_64usec[0x20];
-
-       u8         correctable_err_msg_sent[0x20];
-
-       u8         non_fatal_err_msg_sent[0x20];
-
-       u8         fatal_err_msg_sent[0x20];
-
-       u8         reserved_at_2e0[0x4e0];
-};
-

 struct mlx5_ifc_cmd_inter_comp_event_bits {
        u8         command_completion_vector[0x20];
 
 struct mlx5_ifc_cmd_inter_comp_event_bits {
        u8         command_completion_vector[0x20];
 


@@ -2995,12 +2921,6 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
        u8         reserved_at_0[0x7c0];
 };
 
        u8         reserved_at_0[0x7c0];
 };
 

-union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
-       struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
-       struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits pcie_tas_cntrs_grp_data_layout;
-       u8         reserved_at_0[0x7c0];
-};
-

 union mlx5_ifc_event_auto_bits {
        struct mlx5_ifc_comp_event_bits comp_event;
        struct mlx5_ifc_dct_events_bits dct_events;
 union mlx5_ifc_event_auto_bits {
        struct mlx5_ifc_comp_event_bits comp_event;
        struct mlx5_ifc_dct_events_bits dct_events;


@@ -7320,18 +7240,6 @@ struct mlx5_ifc_ppcnt_reg_bits {
        union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
 };
 
        union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
 };
 

-struct mlx5_ifc_mpcnt_reg_bits {
-       u8         reserved_at_0[0x8];
-       u8         pcie_index[0x8];
-       u8         reserved_at_10[0xa];
-       u8         grp[0x6];
-
-       u8         clr[0x1];
-       u8         reserved_at_21[0x1f];
-
-       union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
-};
-

 struct mlx5_ifc_ppad_reg_bits {
        u8         reserved_at_0[0x3];
        u8         single_mac[0x1];
 struct mlx5_ifc_ppad_reg_bits {
        u8         reserved_at_0[0x3];
        u8         single_mac[0x1];


@@ -7937,7 +7845,6 @@ union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
        struct mlx5_ifc_ppad_reg_bits ppad_reg;
        struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
        struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
        struct mlx5_ifc_ppad_reg_bits ppad_reg;
        struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;

-       struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;

        struct mlx5_ifc_pplm_reg_bits pplm_reg;
        struct mlx5_ifc_pplr_reg_bits pplr_reg;
        struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
        struct mlx5_ifc_pplm_reg_bits pplm_reg;
        struct mlx5_ifc_pplr_reg_bits pplr_reg;
        struct mlx5_ifc_ppsc_reg_bits ppsc_reg;