CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+ CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
+ /* fake hclk clock */
+ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
{ .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true },
{ .gpio = TEGRA_GPIO_POWERKEY, .enable = true },
{ .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true },
+ { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
+ { .gpio = TEGRA_GPIO_USB1, .enable = true },
};
- void __init seaboard_pinmux_init(void)
+ static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
+ {
+ int i, j;
+ struct tegra_pingroup_config *new_pingroup, *base_pingroup;
+
+ /* Update base seaboard pinmux table with secondary board
+ * specific pinmux table table.
+ */
+ for (i = 0; i < size; i++) {
+ new_pingroup = &newtbl[i];
+ for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
+ base_pingroup = &seaboard_pinmux[j];
+ if (new_pingroup->pingroup == base_pingroup->pingroup) {
+ *base_pingroup = *new_pingroup;
+ break;
+ }
+ }
+ }
+ }
+
+ void __init seaboard_common_pinmux_init(void)
{
+ platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
+
tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
#include <mach/iomap.h>
#include <mach/dma.h>
#include <mach/usb_phy.h>
+
#include "gpio-names.h"
+#include "devices.h"
+ static struct resource gpio_resource[] = {
+ [0] = {
+ .start = TEGRA_GPIO_BASE,
+ .end = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_GPIO1,
+ .end = INT_GPIO1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = INT_GPIO2,
+ .end = INT_GPIO2,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = INT_GPIO3,
+ .end = INT_GPIO3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [4] = {
+ .start = INT_GPIO4,
+ .end = INT_GPIO4,
+ .flags = IORESOURCE_IRQ,
+ },
+ [5] = {
+ .start = INT_GPIO5,
+ .end = INT_GPIO5,
+ .flags = IORESOURCE_IRQ,
+ },
+ [6] = {
+ .start = INT_GPIO6,
+ .end = INT_GPIO6,
+ .flags = IORESOURCE_IRQ,
+ },
+ [7] = {
+ .start = INT_GPIO7,
+ .end = INT_GPIO7,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device tegra_gpio_device = {
+ .name = "tegra-gpio",
+ .id = -1,
+ .resource = gpio_resource,
+ .num_resources = ARRAY_SIZE(gpio_resource),
+ };
+
+ static struct resource pinmux_resource[] = {
+ [0] = {
+ /* Tri-state registers */
+ .start = TEGRA_APB_MISC_BASE + 0x14,
+ .end = TEGRA_APB_MISC_BASE + 0x20 + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ /* Mux registers */
+ .start = TEGRA_APB_MISC_BASE + 0x80,
+ .end = TEGRA_APB_MISC_BASE + 0x9c + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ /* Pull-up/down registers */
+ .start = TEGRA_APB_MISC_BASE + 0xa0,
+ .end = TEGRA_APB_MISC_BASE + 0xb0 + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ [3] = {
+ /* Pad control registers */
+ .start = TEGRA_APB_MISC_BASE + 0x868,
+ .end = TEGRA_APB_MISC_BASE + 0x90c + 3,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ struct platform_device tegra_pinmux_device = {
+ .name = "tegra-pinmux",
+ .id = -1,
+ .resource = pinmux_resource,
+ .num_resources = ARRAY_SIZE(pinmux_resource),
+ };
+
static struct resource i2c_resource1[] = {
[0] = {
.start = INT_I2C,
help
This enables support for systems based on the Freescale i.MX3 family
- config ARCH_MX503
- bool "i.MX50 + i.MX53"
- select ARCH_MX50_SUPPORTED
- select ARCH_MX53_SUPPORTED
+ config ARCH_MX5
+ bool "i.MX50, i.MX51, i.MX53"
+ select AUTO_ZRELADDR
+ select ARM_PATCH_PHYS_VIRT
help
- This enables support for machines using Freescale's i.MX50 and i.MX51
+ This enables support for machines using Freescale's i.MX50 and i.MX53
processors.
- config ARCH_MX51
- bool "i.MX51"
- select ARCH_MX51_SUPPORTED
- help
- This enables support for systems based on the Freescale i.MX51 family
-
endchoice
source "arch/arm/mach-imx/Kconfig"
git.samba.org / sfrench / cifs-2.6.git / commitdiff