Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
authorLinus Torvalds <torvalds@linux-foundation.org>
Wed, 25 Feb 2009 23:16:18 +0000 (15:16 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Wed, 25 Feb 2009 23:16:18 +0000 (15:16 -0800)
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6:
  ALSA: emu10k1 - Fix digital/analog switch on audigy2 ZS
  ALSA: hda - Quirk for Acer Aspire 6530G
  ALSA: hda - add another MacBook Pro 3,1 SSID
  ALSA: fix excessive background noise introduced by OSS emulation rate shrink
  ALSA: aw2: do not grab every saa7146 based device
  ALSA: hda - Fix parse of init_verbs sysfs entry
  ALSA: pcxhr.h replace signed one-bit bitfields

100 files changed:
Documentation/kernel-parameters.txt
arch/arm/mach-rpc/riscpc.c
arch/ia64/Kconfig
arch/ia64/kernel/iosapic.c
arch/ia64/kernel/unwind.c
arch/sparc/kernel/chmc.c
crypto/ahash.c
drivers/ata/pata_amd.c
drivers/ata/pata_it821x.c
drivers/ata/pata_legacy.c
drivers/ata/sata_mv.c
drivers/atm/lanai.c
drivers/gpu/drm/drm_crtc_helper.c
drivers/gpu/drm/drm_edid.c
drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_display.c
drivers/i2c/busses/i2c-acorn.c
drivers/i2c/busses/i2c-amd8111.c
drivers/i2c/busses/i2c-ixp2000.c
drivers/i2c/busses/i2c-pxa.c
drivers/i2c/busses/scx200_i2c.c
drivers/i2c/i2c-core.c
drivers/i2c/i2c-dev.c
drivers/ide/Kconfig
drivers/ide/amd74xx.c
drivers/ide/atiixp.c
drivers/ide/ide-cd.c
drivers/ide/ide-cd.h
drivers/ide/ide-gd.c
drivers/ide/ide-gd.h
drivers/ide/ide-tape.c
drivers/ide/ide.c
drivers/ide/it821x.c
drivers/ieee1394/dma.h
drivers/ieee1394/ieee1394_core.c
drivers/ieee1394/ieee1394_transactions.c
drivers/ieee1394/ieee1394_transactions.h
drivers/ieee1394/iso.h
drivers/ieee1394/nodemgr.c
drivers/ieee1394/nodemgr.h
drivers/isdn/sc/shmem.c
drivers/md/raid1.c
drivers/md/raid10.c
drivers/media/dvb/Kconfig
drivers/media/dvb/Makefile
drivers/media/dvb/firewire/Kconfig [new file with mode: 0644]
drivers/media/dvb/firewire/Makefile [new file with mode: 0644]
drivers/media/dvb/firewire/firedtv-1394.c [new file with mode: 0644]
drivers/media/dvb/firewire/firedtv-avc.c [new file with mode: 0644]
drivers/media/dvb/firewire/firedtv-ci.c [new file with mode: 0644]
drivers/media/dvb/firewire/firedtv-dvb.c [new file with mode: 0644]
drivers/media/dvb/firewire/firedtv-fe.c [new file with mode: 0644]
drivers/media/dvb/firewire/firedtv-rc.c [new file with mode: 0644]
drivers/media/dvb/firewire/firedtv.h [new file with mode: 0644]
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/atl1c/Makefile [new file with mode: 0644]
drivers/net/atl1c/atl1c.h [new file with mode: 0644]
drivers/net/atl1c/atl1c_ethtool.c [new file with mode: 0644]
drivers/net/atl1c/atl1c_hw.c [new file with mode: 0644]
drivers/net/atl1c/atl1c_hw.h [new file with mode: 0644]
drivers/net/atl1c/atl1c_main.c [new file with mode: 0644]
drivers/net/cxgb3/cxgb3_main.c
drivers/net/cxgb3/t3_hw.c
drivers/net/forcedeth.c
drivers/net/mv643xx_eth.c
drivers/net/smsc911x.c
drivers/net/smsc9420.c
drivers/net/smsc9420.h
drivers/net/sundance.c
drivers/net/sungem.c
drivers/net/sunlance.c
drivers/net/tg3.c
drivers/net/veth.c
drivers/net/wimax/i2400m/i2400m.h
drivers/net/wireless/iwlwifi/iwl-tx.c
drivers/pci/dmar.c
drivers/pci/intr_remapping.c
fs/ext4/ialloc.c
fs/ext4/inode.c
fs/proc/inode.c
fs/proc/page.c
include/drm/drm_crtc_helper.h
include/drm/drm_edid.h
include/linux/i2c-dev.h
include/linux/i2c.h
include/linux/ide.h
include/linux/if_vlan.h
include/linux/intel-iommu.h
include/linux/skbuff.h
include/net/sock.h
mm/shmem.c
net/core/net_namespace.c
net/core/skbuff.c
net/core/sock.c
net/ipv4/tcp_output.c

index 319785b6dcb1d024892bca7f9eb6c8195d8bcf11..0ed3234125e39e3ee76608da77db7753d3e003ca 100644 (file)
@@ -868,8 +868,10 @@ and is between 256 and 4096 characters. It is defined in the file
        icn=            [HW,ISDN]
                        Format: <io>[,<membase>[,<icn_id>[,<icn_id2>]]]
 
-       ide=            [HW] (E)IDE subsystem
-                       Format: ide=nodma or ide=doubler
+       ide-core.nodma= [HW] (E)IDE subsystem
+                       Format: =0.0 to prevent dma on hda, =0.1 hdb =1.0 hdc
+                       .vlb_clock .pci_clock .noflush .noprobe .nowerr .cdrom
+                       .chs .ignore_cable are additional options
                        See Documentation/ide/ide.txt.
 
        idebus=         [HW] (E)IDE subsystem - VLB/PCI bus speed
index e88d417736af1225cdadca8825ff43e000958712..c7fc01e9d1f64bd9c5be760475f7d9537e497312 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/serial_8250.h>
 #include <linux/ata_platform.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 
 #include <asm/elf.h>
 #include <asm/mach-types.h>
@@ -201,8 +202,13 @@ static struct platform_device *devs[] __initdata = {
        &pata_device,
 };
 
+static struct i2c_board_info i2c_rtc = {
+       I2C_BOARD_INFO("pcf8583", 0x50)
+};
+
 static int __init rpc_init(void)
 {
+       i2c_register_board_info(0, &i2c_rtc, 1);
        return platform_add_devices(devs, ARRAY_SIZE(devs));
 }
 
index 4eb45c0124986279a35d33731a71fcdaf72d53aa..153e727a6e8ecffb23e70bdc39ef3314b34c0aae 100644 (file)
@@ -638,6 +638,17 @@ config DMAR
          and include PCI device scope covered by these DMA
          remapping devices.
 
+config DMAR_DEFAULT_ON
+       def_bool y
+       prompt "Enable DMA Remapping Devices by default"
+       depends on DMAR
+       help
+         Selecting this option will enable a DMAR device at boot time if
+         one is found. If this option is not selected, DMAR support can
+         be enabled by passing intel_iommu=on to the kernel. It is
+         recommended you say N here while the DMAR code remains
+         experimental.
+
 endmenu
 
 endif
index 5cfd3d91001aed8043764c88778d2df3e91681cf..e13125058bedb03eb56d2ab291d7c3e3628c9c25 100644 (file)
@@ -507,7 +507,7 @@ static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
        if (trigger == IOSAPIC_EDGE)
                return -EINVAL;
 
-       for (i = 0; i <= NR_IRQS; i++) {
+       for (i = 0; i < NR_IRQS; i++) {
                info = &iosapic_intr_info[i];
                if (info->trigger == trigger && info->polarity == pol &&
                    (info->dmode == IOSAPIC_FIXED ||
index 67810b77d998768199b3978d288130968e837865..b6c0e63a0bf61535386fff325adaf5f3e40e2932 100644 (file)
@@ -2149,7 +2149,7 @@ unw_remove_unwind_table (void *handle)
 
        /* next, remove hash table entries for this table */
 
-       for (index = 0; index <= UNW_HASH_SIZE; ++index) {
+       for (index = 0; index < UNW_HASH_SIZE; ++index) {
                tmp = unw.cache + unw.hash[index];
                if (unw.hash[index] >= UNW_CACHE_SIZE
                    || tmp->ip < table->start || tmp->ip >= table->end)
index 3b9f4d6e14a9d3119a939e7b5edfc3aec30c554b..e1a9598e2a4db8b0c0cc36aca1c7ac5addb1dbc5 100644 (file)
@@ -306,6 +306,7 @@ static int jbusmc_print_dimm(int syndrome_code,
                buf[1] = '?';
                buf[2] = '?';
                buf[3] = '\0';
+               return 0;
        }
        p = dp->controller;
        prop = &p->layout;
index ba5292d69ebd206cdbf9961e130cf089dc584dd2..b2d1ee32cfe829c774071367b5e40a9d5553dc3f 100644 (file)
@@ -214,7 +214,7 @@ static void crypto_ahash_show(struct seq_file *m, struct crypto_alg *alg)
        seq_printf(m, "async        : %s\n", alg->cra_flags & CRYPTO_ALG_ASYNC ?
                                             "yes" : "no");
        seq_printf(m, "blocksize    : %u\n", alg->cra_blocksize);
-       seq_printf(m, "digestsize   : %u\n", alg->cra_hash.digestsize);
+       seq_printf(m, "digestsize   : %u\n", alg->cra_ahash.digestsize);
 }
 
 const struct crypto_type crypto_ahash_type = {
index 63719ab9ea4448839d64d81faa187250ef21637d..115b1cd6dcf55c32afbe5ec2ab348b3f438db34f 100644 (file)
@@ -24,7 +24,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME "pata_amd"
-#define DRV_VERSION "0.3.11"
+#define DRV_VERSION "0.4.1"
 
 /**
  *     timing_setup            -       shared timing computation and load
@@ -145,6 +145,13 @@ static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
        return ata_sff_prereset(link, deadline);
 }
 
+/**
+ *     amd_cable_detect        -       report cable type
+ *     @ap: port
+ *
+ *     AMD controller/BIOS setups record the cable type in word 0x42
+ */
+
 static int amd_cable_detect(struct ata_port *ap)
 {
        static const u32 bitmask[2] = {0x03, 0x0C};
@@ -157,6 +164,40 @@ static int amd_cable_detect(struct ata_port *ap)
        return ATA_CBL_PATA40;
 }
 
+/**
+ *     amd_fifo_setup          -       set the PIO FIFO for ATA/ATAPI
+ *     @ap: ATA interface
+ *     @adev: ATA device
+ *
+ *     Set the PCI fifo for this device according to the devices present
+ *     on the bus at this point in time. We need to turn the post write buffer
+ *     off for ATAPI devices as we may need to issue a word sized write to the
+ *     device as the final I/O
+ */
+
+static void amd_fifo_setup(struct ata_port *ap)
+{
+       struct ata_device *adev;
+       struct pci_dev *pdev = to_pci_dev(ap->host->dev);
+       static const u8 fifobit[2] = { 0xC0, 0x30};
+       u8 fifo = fifobit[ap->port_no];
+       u8 r;
+
+
+       ata_for_each_dev(adev, &ap->link, ENABLED) {
+               if (adev->class == ATA_DEV_ATAPI)
+                       fifo = 0;
+       }
+       if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
+               fifo = 0;
+
+       /* On the later chips the read prefetch bits become no-op bits */
+       pci_read_config_byte(pdev, 0x41, &r);
+       r &= ~fifobit[ap->port_no];
+       r |= fifo;
+       pci_write_config_byte(pdev, 0x41, r);
+}
+
 /**
  *     amd33_set_piomode       -       set initial PIO mode data
  *     @ap: ATA interface
@@ -167,21 +208,25 @@ static int amd_cable_detect(struct ata_port *ap)
 
 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
+       amd_fifo_setup(ap);
        timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
 }
 
 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
+       amd_fifo_setup(ap);
        timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
 }
 
 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
+       amd_fifo_setup(ap);
        timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
 }
 
 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
 {
+       amd_fifo_setup(ap);
        timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
 }
 
@@ -397,6 +442,16 @@ static struct ata_port_operations nv133_port_ops = {
        .set_dmamode    = nv133_set_dmamode,
 };
 
+static void amd_clear_fifo(struct pci_dev *pdev)
+{
+       u8 fifo;
+       /* Disable the FIFO, the FIFO logic will re-enable it as
+          appropriate */
+       pci_read_config_byte(pdev, 0x41, &fifo);
+       fifo &= 0x0F;
+       pci_write_config_byte(pdev, 0x41, fifo);
+}
+
 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 {
        static const struct ata_port_info info[10] = {
@@ -503,14 +558,8 @@ static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 
        if (type < 3)
                ata_pci_bmdma_clear_simplex(pdev);
-
-       /* Check for AMD7411 */
-       if (type == 3)
-               /* FIFO is broken */
-               pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
-       else
-               pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
-
+       if (pdev->vendor == PCI_VENDOR_ID_AMD)
+               amd_clear_fifo(pdev);
        /* Cable detection on Nvidia chips doesn't work too well,
         * cache BIOS programmed UDMA mode.
         */
@@ -536,18 +585,11 @@ static int amd_reinit_one(struct pci_dev *pdev)
                return rc;
 
        if (pdev->vendor == PCI_VENDOR_ID_AMD) {
-               u8 fifo;
-               pci_read_config_byte(pdev, 0x41, &fifo);
-               if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
-                       /* FIFO is broken */
-                       pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
-               else
-                       pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
+               amd_clear_fifo(pdev);
                if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
                    pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
                        ata_pci_bmdma_clear_simplex(pdev);
        }
-
        ata_host_resume(host);
        return 0;
 }
index f1bb2f9fecbf347b50bb5d76253b6c6bb67e31b9..b05b86a912c5ddb7f7ae14a20bd15af76e61da54 100644 (file)
@@ -557,6 +557,9 @@ static unsigned int it821x_read_id(struct ata_device *adev,
                id[83] |= 0x4400;       /* Word 83 is valid and LBA48 */
                id[86] |= 0x0400;       /* LBA48 on */
                id[ATA_ID_MAJOR_VER] |= 0x1F;
+               /* Clear the serial number because it's different each boot
+                  which breaks validation on resume */
+               memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN);
        }
        return err_mask;
 }
index 6c1d778b63a9cd58a06dc4772fcfc15f8350d428..e3bc1b436284bfa42ac977fe372c98340df24b2d 100644 (file)
@@ -283,9 +283,10 @@ static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
                        unsigned char *buf, unsigned int buflen, int rw)
 {
-       if (ata_id_has_dword_io(dev->id)) {
+       int slop = buflen & 3;
+       /* 32bit I/O capable *and* we need to write a whole number of dwords */
+       if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)) {
                struct ata_port *ap = dev->link->ap;
-               int slop = buflen & 3;
                unsigned long flags;
 
                local_irq_save(flags);
@@ -735,7 +736,7 @@ static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
        struct ata_port *ap = adev->link->ap;
        int slop = buflen & 3;
 
-       if (ata_id_has_dword_io(adev->id)) {
+       if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)) {
                if (rw == WRITE)
                        iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
                else
index 4ae1a4138b47078072bedf2e889338e6bd8a0cb2..7007edd2d4517fed1a5b75773622cae9da003e44 100644 (file)
@@ -3114,19 +3114,17 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
                writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
        }
 
-       if (!IS_SOC(hpriv)) {
-               /* Clear any currently outstanding host interrupt conditions */
-               writelfl(0, mmio + hpriv->irq_cause_ofs);
+       /* Clear any currently outstanding host interrupt conditions */
+       writelfl(0, mmio + hpriv->irq_cause_ofs);
 
-               /* and unmask interrupt generation for host regs */
-               writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
+       /* and unmask interrupt generation for host regs */
+       writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
 
-               /*
-                * enable only global host interrupts for now.
-                * The per-port interrupts get done later as ports are set up.
-                */
-               mv_set_main_irq_mask(host, 0, PCI_ERR);
-       }
+       /*
+        * enable only global host interrupts for now.
+        * The per-port interrupts get done later as ports are set up.
+        */
+       mv_set_main_irq_mask(host, 0, PCI_ERR);
 done:
        return rc;
 }
index 144a49f152207402c044caca1c0c8dde47f10747..8733a2ea04c2b39a02fede69c6e4dbd69035cd3a 100644 (file)
@@ -901,7 +901,7 @@ static int __devinit eeprom_read(struct lanai_dev *lanai)
                clock_l(); udelay(5);
                for (i = 128; i != 0; i >>= 1) {   /* write command out */
                        tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
-                           (data & i) ? CONFIG1_PROMDATA : 0;
+                           ((data & i) ? CONFIG1_PROMDATA : 0);
                        if (lanai->conf1 != tmp) {
                                set_config1(tmp);
                                udelay(5);      /* Let new data settle */
index 733028b4d45e413e9d1689cd73a5fdec0618a982..1c3a8c5571408a6f0a698a53b58f93f6f471a9a9 100644 (file)
@@ -452,6 +452,59 @@ static void drm_setup_crtcs(struct drm_device *dev)
        kfree(modes);
        kfree(enabled);
 }
+
+/**
+ * drm_encoder_crtc_ok - can a given crtc drive a given encoder?
+ * @encoder: encoder to test
+ * @crtc: crtc to test
+ *
+ * Return false if @encoder can't be driven by @crtc, true otherwise.
+ */
+static bool drm_encoder_crtc_ok(struct drm_encoder *encoder,
+                               struct drm_crtc *crtc)
+{
+       struct drm_device *dev;
+       struct drm_crtc *tmp;
+       int crtc_mask = 1;
+
+       WARN(!crtc, "checking null crtc?");
+
+       dev = crtc->dev;
+
+       list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
+               if (tmp == crtc)
+                       break;
+               crtc_mask <<= 1;
+       }
+
+       if (encoder->possible_crtcs & crtc_mask)
+               return true;
+       return false;
+}
+
+/*
+ * Check the CRTC we're going to map each output to vs. its current
+ * CRTC.  If they don't match, we have to disable the output and the CRTC
+ * since the driver will have to re-route things.
+ */
+static void
+drm_crtc_prepare_encoders(struct drm_device *dev)
+{
+       struct drm_encoder_helper_funcs *encoder_funcs;
+       struct drm_encoder *encoder;
+
+       list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+               encoder_funcs = encoder->helper_private;
+               /* Disable unused encoders */
+               if (encoder->crtc == NULL)
+                       (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
+               /* Disable encoders whose CRTC is about to change */
+               if (encoder_funcs->get_crtc &&
+                   encoder->crtc != (*encoder_funcs->get_crtc)(encoder))
+                       (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
+       }
+}
+
 /**
  * drm_crtc_set_mode - set a mode
  * @crtc: CRTC to program
@@ -547,6 +600,8 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
                encoder_funcs->prepare(encoder);
        }
 
+       drm_crtc_prepare_encoders(dev);
+
        crtc_funcs->prepare(crtc);
 
        /* Set up the DPLL and any encoders state that needs to adjust or depend
@@ -617,7 +672,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
        struct drm_device *dev;
        struct drm_crtc **save_crtcs, *new_crtc;
        struct drm_encoder **save_encoders, *new_encoder;
-       struct drm_framebuffer *old_fb;
+       struct drm_framebuffer *old_fb = NULL;
        bool save_enabled;
        bool mode_changed = false;
        bool fb_changed = false;
@@ -668,9 +723,10 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
         * and then just flip_or_move it */
        if (set->crtc->fb != set->fb) {
                /* If we have no fb then treat it as a full mode set */
-               if (set->crtc->fb == NULL)
+               if (set->crtc->fb == NULL) {
+                       DRM_DEBUG("crtc has no fb, full mode set\n");
                        mode_changed = true;
-               else if ((set->fb->bits_per_pixel !=
+               else if ((set->fb->bits_per_pixel !=
                         set->crtc->fb->bits_per_pixel) ||
                         set->fb->depth != set->crtc->fb->depth)
                        fb_changed = true;
@@ -682,7 +738,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                fb_changed = true;
 
        if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
-               DRM_DEBUG("modes are different\n");
+               DRM_DEBUG("modes are different, full mode set\n");
                drm_mode_debug_printmodeline(&set->crtc->mode);
                drm_mode_debug_printmodeline(set->mode);
                mode_changed = true;
@@ -708,6 +764,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                }
 
                if (new_encoder != connector->encoder) {
+                       DRM_DEBUG("encoder changed, full mode switch\n");
                        mode_changed = true;
                        connector->encoder = new_encoder;
                }
@@ -734,10 +791,20 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                        if (set->connectors[ro] == connector)
                                new_crtc = set->crtc;
                }
+
+               /* Make sure the new CRTC will work with the encoder */
+               if (new_crtc &&
+                   !drm_encoder_crtc_ok(connector->encoder, new_crtc)) {
+                       ret = -EINVAL;
+                       goto fail_set_mode;
+               }
                if (new_crtc != connector->encoder->crtc) {
+                       DRM_DEBUG("crtc changed, full mode switch\n");
                        mode_changed = true;
                        connector->encoder->crtc = new_crtc;
                }
+               DRM_DEBUG("setting connector %d crtc to %p\n",
+                         connector->base.id, new_crtc);
        }
 
        /* mode_set_base is not a required function */
@@ -781,6 +848,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
 
 fail_set_mode:
        set->crtc->enabled = save_enabled;
+       set->crtc->fb = old_fb;
        count = 0;
        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                if (!connector->encoder)
index 5a4d3244758a102ec7cea6ed87342619dd47c85e..a839a28d8ee606763ad213d9dc785bc4dde0dd6c 100644 (file)
@@ -125,7 +125,7 @@ static bool edid_is_valid(struct edid *edid)
                DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
                goto bad;
        }
-       if (edid->revision <= 0 || edid->revision > 3) {
+       if (edid->revision > 3) {
                DRM_ERROR("EDID has minor version %d, which is not between 0-3\n", edid->revision);
                goto bad;
        }
@@ -320,10 +320,10 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
        mode->htotal = mode->hdisplay + ((pt->hblank_hi << 8) | pt->hblank_lo);
 
        mode->vdisplay = (pt->vactive_hi << 8) | pt->vactive_lo;
-       mode->vsync_start = mode->vdisplay + ((pt->vsync_offset_hi << 8) |
+       mode->vsync_start = mode->vdisplay + ((pt->vsync_offset_hi << 4) |
                                              pt->vsync_offset_lo);
        mode->vsync_end = mode->vsync_start +
-               ((pt->vsync_pulse_width_hi << 8) |
+               ((pt->vsync_pulse_width_hi << 4) |
                 pt->vsync_pulse_width_lo);
        mode->vtotal = mode->vdisplay + ((pt->vblank_hi << 8) | pt->vblank_lo);
 
index 3795dbc0f50cff99b167fc0659f0d0862c8d57d5..93e677a481f5388f380bc86547297e8f87bddbb0 100644 (file)
@@ -435,6 +435,8 @@ EXPORT_SYMBOL(drm_vblank_get);
  */
 void drm_vblank_put(struct drm_device *dev, int crtc)
 {
+       BUG_ON (atomic_read (&dev->vblank_refcount[crtc]) == 0);
+
        /* Last user schedules interrupt disable */
        if (atomic_dec_and_test(&dev->vblank_refcount[crtc]))
                mod_timer(&dev->vblank_disable_timer, jiffies + 5*DRM_HZ);
@@ -460,8 +462,9 @@ void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
         * so that interrupts remain enabled in the interim.
         */
        if (!dev->vblank_inmodeset[crtc]) {
-               dev->vblank_inmodeset[crtc] = 1;
-               drm_vblank_get(dev, crtc);
+               dev->vblank_inmodeset[crtc] = 0x1;
+               if (drm_vblank_get(dev, crtc) == 0)
+                       dev->vblank_inmodeset[crtc] |= 0x2;
        }
 }
 EXPORT_SYMBOL(drm_vblank_pre_modeset);
@@ -473,9 +476,12 @@ void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
        if (dev->vblank_inmodeset[crtc]) {
                spin_lock_irqsave(&dev->vbl_lock, irqflags);
                dev->vblank_disable_allowed = 1;
-               dev->vblank_inmodeset[crtc] = 0;
                spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
-               drm_vblank_put(dev, crtc);
+
+               if (dev->vblank_inmodeset[crtc] & 0x2)
+                       drm_vblank_put(dev, crtc);
+
+               dev->vblank_inmodeset[crtc] = 0;
        }
 }
 EXPORT_SYMBOL(drm_vblank_post_modeset);
index 2d797ffe8137c43472f08a3019ecb2052d664ec6..cc4649577a61d0c5aae865e8f219f931c44519e5 100644 (file)
@@ -811,7 +811,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
        dev_priv->hws_map.flags = 0;
        dev_priv->hws_map.mtrr = 0;
 
-       drm_core_ioremap(&dev_priv->hws_map, dev);
+       drm_core_ioremap_wc(&dev_priv->hws_map, dev);
        if (dev_priv->hws_map.handle == NULL) {
                i915_dma_cleanup(dev);
                dev_priv->status_gfx_addr = 0;
index 0692622ee2b3dc3d75e47c086a344b1e0fd8bb3b..b293ef0bae7153805d587201c8ce6c84f3703f4c 100644 (file)
@@ -68,9 +68,11 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
        i915_save_state(dev);
 
        /* If KMS is active, we do the leavevt stuff here */
-       if (drm_core_check_feature(dev, DRIVER_MODESET) && i915_gem_idle(dev)) {
-               dev_err(&dev->pdev->dev, "GEM idle failed, aborting suspend\n");
-               return -EBUSY;
+       if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+               if (i915_gem_idle(dev))
+                       dev_err(&dev->pdev->dev,
+                               "GEM idle failed, resume may fail\n");
+               drm_irq_uninstall(dev);
        }
 
        intel_opregion_free(dev);
@@ -108,6 +110,8 @@ static int i915_resume(struct drm_device *dev)
                if (ret != 0)
                        ret = -1;
                mutex_unlock(&dev->struct_mutex);
+
+               drm_irq_install(dev);
        }
 
        return ret;
index 25b337438ca737d4148bbc473f68483ece0d40bc..85685bfd12daf02fb26bea88a90e521d6e3237c2 100644 (file)
@@ -1051,6 +1051,9 @@ i915_gem_retire_requests(struct drm_device *dev)
        drm_i915_private_t *dev_priv = dev->dev_private;
        uint32_t seqno;
 
+       if (!dev_priv->hw_status_page)
+               return;
+
        seqno = i915_get_gem_seqno(dev);
 
        while (!list_empty(&dev_priv->mm.request_list)) {
@@ -3545,7 +3548,7 @@ i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
        user_data = (char __user *) (uintptr_t) args->data_ptr;
        obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
 
-       DRM_ERROR("obj_addr %p, %lld\n", obj_addr, args->size);
+       DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
        ret = copy_from_user(obj_addr, user_data, args->size);
        if (ret)
                return -EFAULT;
index 65be30dccc7767d8781cad444a317c43930a6064..fc28e2bbd5427e6030869724dfb9bd20b5797451 100644 (file)
@@ -111,6 +111,12 @@ parse_panel_data(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
        panel_fixed_mode->clock = dvo_timing->clock * 10;
        panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
 
+       /* Some VBTs have bogus h/vtotal values */
+       if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
+               panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
+       if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
+               panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
+
        drm_mode_set_name(panel_fixed_mode);
 
        dev_priv->vbt_mode = panel_fixed_mode;
index 65b635ce28c8c78da6563f21538d9d6434de23a9..a2834276cb38637949648dad2ae2b59de8995fbf 100644 (file)
@@ -217,7 +217,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
     return false;
 }
 
-#define INTELPllInvalid(s)   do { DRM_DEBUG(s); return false; } while (0)
+#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 /**
  * Returns whether the given set of divisors are valid for a given refclk with
  * the given connectors.
index 9fee3ca17344b9ab6adf895b4869a82e7d8bac6b..9aefb5e5864df92b9f5d6226db680c55e8bdf274 100644 (file)
@@ -79,10 +79,11 @@ static struct i2c_algo_bit_data ioc_data = {
        .getsda         = ioc_getsda,
        .getscl         = ioc_getscl,
        .udelay         = 80,
-       .timeout        = 100
+       .timeout        = HZ,
 };
 
 static struct i2c_adapter ioc_ops = {
+       .nr                     = 0,
        .algo_data              = &ioc_data,
 };
 
@@ -90,7 +91,7 @@ static int __init i2c_ioc_init(void)
 {
        force_ones = FORCE_ONES | SCL | SDA;
 
-       return i2c_bit_add_bus(&ioc_ops);
+       return i2c_bit_add_numbered_bus(&ioc_ops);
 }
 
 module_init(i2c_ioc_init);
index edab51973bf5501c303fc56a23b1f90f722b1e6a..a7c59908c457cbeb23937904dc6d6a76a05e060c 100644 (file)
@@ -72,7 +72,7 @@ static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
 {
        int timeout = 500;
 
-       while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
+       while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout)
                udelay(1);
 
        if (!timeout) {
@@ -88,7 +88,7 @@ static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
 {
        int timeout = 500;
 
-       while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
+       while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout)
                udelay(1);
 
        if (!timeout) {
index 8e8467970481bb86972eadcb16bdb2dce7cf6a3d..c016f7a2c5fc2712433dbd83ec7d1c6dd1d48f3b 100644 (file)
@@ -114,7 +114,7 @@ static int ixp2000_i2c_probe(struct platform_device *plat_dev)
        drv_data->algo_data.getsda = ixp2000_bit_getsda;
        drv_data->algo_data.getscl = ixp2000_bit_getscl;
        drv_data->algo_data.udelay = 6;
-       drv_data->algo_data.timeout = 100;
+       drv_data->algo_data.timeout = HZ;
 
        strlcpy(drv_data->adapter.name, plat_dev->dev.driver->name,
                sizeof(drv_data->adapter.name));
index 6af68146c34248507c0d8df07691992c31d54991..bdb1f7510e91555209bdf5dedfd20a48f50e1aba 100644 (file)
@@ -644,7 +644,7 @@ static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 
        i2c_pxa_start_message(i2c);
 
-       while (timeout-- && i2c->msg_num > 0) {
+       while (i2c->msg_num > 0 && --timeout) {
                i2c_pxa_handler(0, i2c);
                udelay(10);
        }
index 162b74a04886c5497296579c6bbabda7015f2948..42df0eca43d5229b1fd88624e3fee4c369f0f462 100644 (file)
@@ -76,7 +76,7 @@ static struct i2c_algo_bit_data scx200_i2c_data = {
        .getsda         = scx200_i2c_getsda,
        .getscl         = scx200_i2c_getscl,
        .udelay         = 10,
-       .timeout        = 100,
+       .timeout        = HZ,
 };
 
 static struct i2c_adapter scx200_i2c_ops = {
index b1c9abe24c7b2a84f143c264d82a3ee74cdc0639..e7d984866de0465f5846225c6b59a0072fec7fd1 100644 (file)
@@ -1831,7 +1831,8 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter * adapter, u16 addr,
        case I2C_SMBUS_QUICK:
                msg[0].len = 0;
                /* Special case: The read/write field is used as data */
-               msg[0].flags = flags | (read_write==I2C_SMBUS_READ)?I2C_M_RD:0;
+               msg[0].flags = flags | (read_write == I2C_SMBUS_READ ?
+                                       I2C_M_RD : 0);
                num = 1;
                break;
        case I2C_SMBUS_BYTE:
index c171988a9f517d7009319674265c47a10859a8c3..7e13d2df9af384f0b048faa36c427171dab30fa0 100644 (file)
@@ -35,6 +35,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-dev.h>
 #include <linux/smp_lock.h>
+#include <linux/jiffies.h>
 #include <asm/uaccess.h>
 
 static struct i2c_driver i2cdev_driver;
@@ -422,7 +423,10 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
                client->adapter->retries = arg;
                break;
        case I2C_TIMEOUT:
-               client->adapter->timeout = arg;
+               /* For historical reasons, user-space sets the timeout
+                * value in units of 10 ms.
+                */
+               client->adapter->timeout = msecs_to_jiffies(arg * 10);
                break;
        default:
                /* NOTE:  returning a fault code here could cause trouble
index 3dad2299d9c57e9b22ec420bb180c93d975b1e77..e072903b12f016aab1aa0d72e0939907253ff033 100644 (file)
@@ -46,7 +46,7 @@ menuconfig IDE
          SMART parameters from disk drives.
 
          To compile this driver as a module, choose M here: the
-         module will be called ide.
+         module will be called ide-core.ko.
 
          For further information, please read <file:Documentation/ide/ide.txt>.
 
index 69660a431cd9890f707c87d7e7a38f3429e643de..77267c85996578a47adb19d7104db6992e128e38 100644 (file)
@@ -166,7 +166,7 @@ static unsigned int init_chipset_amd74xx(struct pci_dev *dev)
         * Check for broken FIFO support.
         */
        if (dev->vendor == PCI_VENDOR_ID_AMD &&
-           dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411)
+           dev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
                t &= 0x0f;
        else
                t |= 0xf0;
index b2735d28f5cc22019b88c8f159da1af91dccbb7e..ecd1e62ca91a86b0373bf7156e8326e67ffbfa25 100644 (file)
@@ -52,7 +52,7 @@ static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
 {
        struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
        unsigned long flags;
-       int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
+       int timing_shift = (drive->dn ^ 1) * 8;
        u32 pio_timing_data;
        u16 pio_mode_data;
 
@@ -85,7 +85,7 @@ static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
 {
        struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
        unsigned long flags;
-       int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
+       int timing_shift = (drive->dn ^ 1) * 8;
        u32 tmp32;
        u16 tmp16;
        u16 udma_ctl = 0;
index 0bfeb0c79d6e8e172cdbb5fd3af9a9df084351c5..ddfbea41d296a738a1efb5ace07b22b9a7dff2ad 100644 (file)
@@ -55,7 +55,7 @@
 
 static DEFINE_MUTEX(idecd_ref_mutex);
 
-static void ide_cd_release(struct kref *);
+static void ide_cd_release(struct device *);
 
 static struct cdrom_info *ide_cd_get(struct gendisk *disk)
 {
@@ -67,7 +67,7 @@ static struct cdrom_info *ide_cd_get(struct gendisk *disk)
                if (ide_device_get(cd->drive))
                        cd = NULL;
                else
-                       kref_get(&cd->kref);
+                       get_device(&cd->dev);
 
        }
        mutex_unlock(&idecd_ref_mutex);
@@ -79,7 +79,7 @@ static void ide_cd_put(struct cdrom_info *cd)
        ide_drive_t *drive = cd->drive;
 
        mutex_lock(&idecd_ref_mutex);
-       kref_put(&cd->kref, ide_cd_release);
+       put_device(&cd->dev);
        ide_device_put(drive);
        mutex_unlock(&idecd_ref_mutex);
 }
@@ -194,6 +194,14 @@ static void cdrom_analyze_sense_data(ide_drive_t *drive,
                        bio_sectors = max(bio_sectors(failed_command->bio), 4U);
                        sector &= ~(bio_sectors - 1);
 
+                       /*
+                        * The SCSI specification allows for the value
+                        * returned by READ CAPACITY to be up to 75 2K
+                        * sectors past the last readable block.
+                        * Therefore, if we hit a medium error within the
+                        * last 75 2K sectors, we decrease the saved size
+                        * value.
+                        */
                        if (sector < get_capacity(info->disk) &&
                            drive->probed_capacity - sector < 4 * 75)
                                set_capacity(info->disk, sector);
@@ -1790,15 +1798,17 @@ static void ide_cd_remove(ide_drive_t *drive)
        ide_debug_log(IDE_DBG_FUNC, "Call %s\n", __func__);
 
        ide_proc_unregister_driver(drive, info->driver);
-
+       device_del(&info->dev);
        del_gendisk(info->disk);
 
-       ide_cd_put(info);
+       mutex_lock(&idecd_ref_mutex);
+       put_device(&info->dev);
+       mutex_unlock(&idecd_ref_mutex);
 }
 
-static void ide_cd_release(struct kref *kref)
+static void ide_cd_release(struct device *dev)
 {
-       struct cdrom_info *info = to_ide_drv(kref, cdrom_info);
+       struct cdrom_info *info = to_ide_drv(dev, cdrom_info);
        struct cdrom_device_info *devinfo = &info->devinfo;
        ide_drive_t *drive = info->drive;
        struct gendisk *g = info->disk;
@@ -1997,7 +2007,12 @@ static int ide_cd_probe(ide_drive_t *drive)
 
        ide_init_disk(g, drive);
 
-       kref_init(&info->kref);
+       info->dev.parent = &drive->gendev;
+       info->dev.release = ide_cd_release;
+       dev_set_name(&info->dev, dev_name(&drive->gendev));
+
+       if (device_register(&info->dev))
+               goto out_free_disk;
 
        info->drive = drive;
        info->driver = &ide_cdrom_driver;
@@ -2011,7 +2026,7 @@ static int ide_cd_probe(ide_drive_t *drive)
        g->driverfs_dev = &drive->gendev;
        g->flags = GENHD_FL_CD | GENHD_FL_REMOVABLE;
        if (ide_cdrom_setup(drive)) {
-               ide_cd_release(&info->kref);
+               put_device(&info->dev);
                goto failed;
        }
 
@@ -2021,6 +2036,8 @@ static int ide_cd_probe(ide_drive_t *drive)
        add_disk(g);
        return 0;
 
+out_free_disk:
+       put_disk(g);
 out_free_cd:
        kfree(info);
 failed:
index ac40d6cb90a240725ae40d661e428e27ebc36aef..c878bfcf111698430e8f870c0ccbc4e12b6e71ca 100644 (file)
@@ -80,7 +80,7 @@ struct cdrom_info {
        ide_drive_t             *drive;
        struct ide_driver       *driver;
        struct gendisk          *disk;
-       struct kref             kref;
+       struct device           dev;
 
        /* Buffer for table of contents.  NULL if we haven't allocated
           a TOC buffer for this device yet. */
index 7857b209c6df7616397e9a1e20a621807729f83e..047109419902c0ad6b3f741e68fdaab0e05a1069 100644 (file)
@@ -25,7 +25,7 @@ module_param(debug_mask, ulong, 0644);
 
 static DEFINE_MUTEX(ide_disk_ref_mutex);
 
-static void ide_disk_release(struct kref *);
+static void ide_disk_release(struct device *);
 
 static struct ide_disk_obj *ide_disk_get(struct gendisk *disk)
 {
@@ -37,7 +37,7 @@ static struct ide_disk_obj *ide_disk_get(struct gendisk *disk)
                if (ide_device_get(idkp->drive))
                        idkp = NULL;
                else
-                       kref_get(&idkp->kref);
+                       get_device(&idkp->dev);
        }
        mutex_unlock(&ide_disk_ref_mutex);
        return idkp;
@@ -48,7 +48,7 @@ static void ide_disk_put(struct ide_disk_obj *idkp)
        ide_drive_t *drive = idkp->drive;
 
        mutex_lock(&ide_disk_ref_mutex);
-       kref_put(&idkp->kref, ide_disk_release);
+       put_device(&idkp->dev);
        ide_device_put(drive);
        mutex_unlock(&ide_disk_ref_mutex);
 }
@@ -66,17 +66,18 @@ static void ide_gd_remove(ide_drive_t *drive)
        struct gendisk *g = idkp->disk;
 
        ide_proc_unregister_driver(drive, idkp->driver);
-
+       device_del(&idkp->dev);
        del_gendisk(g);
-
        drive->disk_ops->flush(drive);
 
-       ide_disk_put(idkp);
+       mutex_lock(&ide_disk_ref_mutex);
+       put_device(&idkp->dev);
+       mutex_unlock(&ide_disk_ref_mutex);
 }
 
-static void ide_disk_release(struct kref *kref)
+static void ide_disk_release(struct device *dev)
 {
-       struct ide_disk_obj *idkp = to_ide_drv(kref, ide_disk_obj);
+       struct ide_disk_obj *idkp = to_ide_drv(dev, ide_disk_obj);
        ide_drive_t *drive = idkp->drive;
        struct gendisk *g = idkp->disk;
 
@@ -348,7 +349,12 @@ static int ide_gd_probe(ide_drive_t *drive)
 
        ide_init_disk(g, drive);
 
-       kref_init(&idkp->kref);
+       idkp->dev.parent = &drive->gendev;
+       idkp->dev.release = ide_disk_release;
+       dev_set_name(&idkp->dev, dev_name(&drive->gendev));
+
+       if (device_register(&idkp->dev))
+               goto out_free_disk;
 
        idkp->drive = drive;
        idkp->driver = &ide_gd_driver;
@@ -373,6 +379,8 @@ static int ide_gd_probe(ide_drive_t *drive)
        add_disk(g);
        return 0;
 
+out_free_disk:
+       put_disk(g);
 out_free_idkp:
        kfree(idkp);
 failed:
index a86779f0756b7c117ece8a93c3acaa649c6dd9d9..b604bdd318a1294a6e7cb8c9d2addcca68f8759d 100644 (file)
@@ -17,7 +17,7 @@ struct ide_disk_obj {
        ide_drive_t             *drive;
        struct ide_driver       *driver;
        struct gendisk          *disk;
-       struct kref             kref;
+       struct device           dev;
        unsigned int            openers;        /* protected by BKL for now */
 
        /* Last failed packet command */
index d7ecd3c79757f036e0f9f5d083a63f31b64059b1..bb450a7608c2fe9a8ef08f19b03d86ba980f3fde 100644 (file)
@@ -169,7 +169,7 @@ typedef struct ide_tape_obj {
        ide_drive_t             *drive;
        struct ide_driver       *driver;
        struct gendisk          *disk;
-       struct kref             kref;
+       struct device           dev;
 
        /*
         *      failed_pc points to the last failed packet command, or contains
@@ -267,7 +267,7 @@ static DEFINE_MUTEX(idetape_ref_mutex);
 
 static struct class *idetape_sysfs_class;
 
-static void ide_tape_release(struct kref *);
+static void ide_tape_release(struct device *);
 
 static struct ide_tape_obj *ide_tape_get(struct gendisk *disk)
 {
@@ -279,7 +279,7 @@ static struct ide_tape_obj *ide_tape_get(struct gendisk *disk)
                if (ide_device_get(tape->drive))
                        tape = NULL;
                else
-                       kref_get(&tape->kref);
+                       get_device(&tape->dev);
        }
        mutex_unlock(&idetape_ref_mutex);
        return tape;
@@ -290,7 +290,7 @@ static void ide_tape_put(struct ide_tape_obj *tape)
        ide_drive_t *drive = tape->drive;
 
        mutex_lock(&idetape_ref_mutex);
-       kref_put(&tape->kref, ide_tape_release);
+       put_device(&tape->dev);
        ide_device_put(drive);
        mutex_unlock(&idetape_ref_mutex);
 }
@@ -308,7 +308,7 @@ static struct ide_tape_obj *ide_tape_chrdev_get(unsigned int i)
        mutex_lock(&idetape_ref_mutex);
        tape = idetape_devs[i];
        if (tape)
-               kref_get(&tape->kref);
+               get_device(&tape->dev);
        mutex_unlock(&idetape_ref_mutex);
        return tape;
 }
@@ -2256,15 +2256,17 @@ static void ide_tape_remove(ide_drive_t *drive)
        idetape_tape_t *tape = drive->driver_data;
 
        ide_proc_unregister_driver(drive, tape->driver);
-
+       device_del(&tape->dev);
        ide_unregister_region(tape->disk);
 
-       ide_tape_put(tape);
+       mutex_lock(&idetape_ref_mutex);
+       put_device(&tape->dev);
+       mutex_unlock(&idetape_ref_mutex);
 }
 
-static void ide_tape_release(struct kref *kref)
+static void ide_tape_release(struct device *dev)
 {
-       struct ide_tape_obj *tape = to_ide_drv(kref, ide_tape_obj);
+       struct ide_tape_obj *tape = to_ide_drv(dev, ide_tape_obj);
        ide_drive_t *drive = tape->drive;
        struct gendisk *g = tape->disk;
 
@@ -2407,7 +2409,12 @@ static int ide_tape_probe(ide_drive_t *drive)
 
        ide_init_disk(g, drive);
 
-       kref_init(&tape->kref);
+       tape->dev.parent = &drive->gendev;
+       tape->dev.release = ide_tape_release;
+       dev_set_name(&tape->dev, dev_name(&drive->gendev));
+
+       if (device_register(&tape->dev))
+               goto out_free_disk;
 
        tape->drive = drive;
        tape->driver = &idetape_driver;
@@ -2436,6 +2443,8 @@ static int ide_tape_probe(ide_drive_t *drive)
 
        return 0;
 
+out_free_disk:
+       put_disk(g);
 out_free_tape:
        kfree(tape);
 failed:
index 258805da15c33f596079fd1a804b25d24d10c2cb..0920e3b0c962451d6e98cff91bf87e5e150b0afb 100644 (file)
@@ -337,6 +337,7 @@ static int ide_set_dev_param_mask(const char *s, struct kernel_param *kp)
        int a, b, i, j = 1;
        unsigned int *dev_param_mask = (unsigned int *)kp->arg;
 
+       /* controller . device (0 or 1) [ : 1 (set) | 0 (clear) ] */
        if (sscanf(s, "%d.%d:%d", &a, &b, &j) != 3 &&
            sscanf(s, "%d.%d", &a, &b) != 2)
                return -EINVAL;
@@ -349,7 +350,7 @@ static int ide_set_dev_param_mask(const char *s, struct kernel_param *kp)
        if (j)
                *dev_param_mask |= (1 << i);
        else
-               *dev_param_mask &= (1 << i);
+               *dev_param_mask &= ~(1 << i);
 
        return 0;
 }
@@ -392,6 +393,8 @@ static int ide_set_disk_chs(const char *str, struct kernel_param *kp)
 {
        int a, b, c = 0, h = 0, s = 0, i, j = 1;
 
+       /* controller . device (0 or 1) : Cylinders , Heads , Sectors */
+       /* controller . device (0 or 1) : 1 (use CHS) | 0 (ignore CHS) */
        if (sscanf(str, "%d.%d:%d,%d,%d", &a, &b, &c, &h, &s) != 5 &&
            sscanf(str, "%d.%d:%d", &a, &b, &j) != 3)
                return -EINVAL;
@@ -407,7 +410,7 @@ static int ide_set_disk_chs(const char *str, struct kernel_param *kp)
        if (j)
                ide_disks |= (1 << i);
        else
-               ide_disks &= (1 << i);
+               ide_disks &= ~(1 << i);
 
        ide_disks_chs[i].cyl  = c;
        ide_disks_chs[i].head = h;
@@ -469,6 +472,8 @@ static int ide_set_ignore_cable(const char *s, struct kernel_param *kp)
 {
        int i, j = 1;
 
+       /* controller (ignore) */
+       /* controller : 1 (ignore) | 0 (use) */
        if (sscanf(s, "%d:%d", &i, &j) != 2 && sscanf(s, "%d", &i) != 1)
                return -EINVAL;
 
@@ -478,7 +483,7 @@ static int ide_set_ignore_cable(const char *s, struct kernel_param *kp)
        if (j)
                ide_ignore_cable |= (1 << i);
        else
-               ide_ignore_cable &= (1 << i);
+               ide_ignore_cable &= ~(1 << i);
 
        return 0;
 }
index e1c4f5437396b076bf09f55f32eed07e9ef6b9f4..13b8153112edf3394235f3009aaefd18e1197bc4 100644 (file)
@@ -5,9 +5,8 @@
  *  May be copied or modified under the terms of the GNU General Public License
  *  Based in part on the ITE vendor provided SCSI driver.
  *
- *  Documentation available from
- *     http://www.ite.com.tw/pc/IT8212F_V04.pdf
- *  Some other documents are NDA.
+ *  Documentation:
+ *     Datasheet is freely available, some other documents under NDA.
  *
  *  The ITE8212 isn't exactly a standard IDE controller. It has two
  *  modes. In pass through mode then it is an IDE controller. In its smart
index 2727bcd24194c6e36651fadbc9439721708e93a8..467373cab8e5a1fc7ed1ffcea2e14560b8898db3 100644 (file)
@@ -12,6 +12,7 @@
 
 #include <asm/types.h>
 
+struct file;
 struct pci_dev;
 struct scatterlist;
 struct vm_area_struct;
index 2beb8d94f7bd3b7584c2c30003c98892b97d3e43..1028e725a27e2ca96248b6957688a94a821b3ca6 100644 (file)
@@ -1314,6 +1314,7 @@ EXPORT_SYMBOL(hpsb_make_lock64packet);
 EXPORT_SYMBOL(hpsb_make_phypacket);
 EXPORT_SYMBOL(hpsb_read);
 EXPORT_SYMBOL(hpsb_write);
+EXPORT_SYMBOL(hpsb_lock);
 EXPORT_SYMBOL(hpsb_packet_success);
 
 /** highlevel.c **/
index 10c3d9f8c038ea944750bff2e913ef8b3c12d8b0..675b3135d5f19a78816976b0835deb54468c94af 100644 (file)
@@ -501,8 +501,6 @@ int hpsb_read(struct hpsb_host *host, nodeid_t node, unsigned int generation,
        if (length == 0)
                return -EINVAL;
 
-       BUG_ON(in_interrupt()); // We can't be called in an interrupt, yet
-
        packet = hpsb_make_readpacket(host, node, addr, length);
 
        if (!packet) {
@@ -550,8 +548,6 @@ int hpsb_write(struct hpsb_host *host, nodeid_t node, unsigned int generation,
        if (length == 0)
                return -EINVAL;
 
-       BUG_ON(in_interrupt()); // We can't be called in an interrupt, yet
-
        packet = hpsb_make_writepacket(host, node, addr, buffer, length);
 
        if (!packet)
@@ -570,3 +566,30 @@ int hpsb_write(struct hpsb_host *host, nodeid_t node, unsigned int generation,
 
        return retval;
 }
+
+int hpsb_lock(struct hpsb_host *host, nodeid_t node, unsigned int generation,
+             u64 addr, int extcode, quadlet_t *data, quadlet_t arg)
+{
+       struct hpsb_packet *packet;
+       int retval = 0;
+
+       packet = hpsb_make_lockpacket(host, node, addr, extcode, data, arg);
+       if (!packet)
+               return -ENOMEM;
+
+       packet->generation = generation;
+       retval = hpsb_send_packet_and_wait(packet);
+       if (retval < 0)
+               goto hpsb_lock_fail;
+
+       retval = hpsb_packet_success(packet);
+
+       if (retval == 0)
+               *data = packet->data[0];
+
+hpsb_lock_fail:
+       hpsb_free_tlabel(packet);
+       hpsb_free_packet(packet);
+
+       return retval;
+}
index d2d5bc3546d74093b2fe0ce56ef913b63ef6648e..20b693be14b22f558491285e895e7cad5bf20828 100644 (file)
@@ -30,6 +30,8 @@ int hpsb_read(struct hpsb_host *host, nodeid_t node, unsigned int generation,
              u64 addr, quadlet_t *buffer, size_t length);
 int hpsb_write(struct hpsb_host *host, nodeid_t node, unsigned int generation,
               u64 addr, quadlet_t *buffer, size_t length);
+int hpsb_lock(struct hpsb_host *host, nodeid_t node, unsigned int generation,
+             u64 addr, int extcode, quadlet_t *data, quadlet_t arg);
 
 #ifdef HPSB_DEBUG_TLABELS
 extern spinlock_t hpsb_tlabel_lock;
index b5de5f21ef78a57e45032500867fdb24538de00e..c2089c093aa76eaf1165391a3ea2d8d5b023b960 100644 (file)
@@ -13,6 +13,7 @@
 #define IEEE1394_ISO_H
 
 #include <linux/spinlock_types.h>
+#include <linux/wait.h>
 #include <asm/atomic.h>
 #include <asm/types.h>
 
index 906c5a98d8142585a1ad86ef2c1d55f9b16cc3eb..53aada5bbe1ebad918803836b8752a21cecbb37e 100644 (file)
@@ -971,6 +971,9 @@ static struct unit_directory *nodemgr_process_unit_directory
        ud->ud_kv = ud_kv;
        ud->id = (*id)++;
 
+       /* inherit vendor_id from root directory if none exists in unit dir */
+       ud->vendor_id = ne->vendor_id;
+
        csr1212_for_each_dir_entry(ne->csr, kv, ud_kv, dentry) {
                switch (kv->key.id) {
                case CSR1212_KV_ID_VENDOR:
@@ -1265,7 +1268,8 @@ static void nodemgr_update_node(struct node_entry *ne, struct csr1212_csr *csr,
                csr1212_destroy_csr(csr);
        }
 
-       /* Mark the node current */
+       /* Finally, mark the node current */
+       smp_wmb();
        ne->generation = generation;
 
        if (ne->in_limbo) {
@@ -1798,7 +1802,7 @@ void hpsb_node_fill_packet(struct node_entry *ne, struct hpsb_packet *packet)
 {
        packet->host = ne->host;
        packet->generation = ne->generation;
-       barrier();
+       smp_rmb();
        packet->node_id = ne->nodeid;
 }
 
@@ -1807,7 +1811,7 @@ int hpsb_node_write(struct node_entry *ne, u64 addr,
 {
        unsigned int generation = ne->generation;
 
-       barrier();
+       smp_rmb();
        return hpsb_write(ne->host, ne->nodeid, generation,
                          addr, buffer, length);
 }
index 15ea09733e84fbc1ee4588f730ed77b049aa1e5c..ee5acdbd114aed18c942fd11c6a38bbc3193be10 100644 (file)
 #define _IEEE1394_NODEMGR_H
 
 #include <linux/device.h>
+#include <asm/system.h>
 #include <asm/types.h>
 
 #include "ieee1394_core.h"
+#include "ieee1394_transactions.h"
 #include "ieee1394_types.h"
 
 struct csr1212_csr;
@@ -154,6 +156,22 @@ static inline int hpsb_node_entry_valid(struct node_entry *ne)
 void hpsb_node_fill_packet(struct node_entry *ne, struct hpsb_packet *packet);
 int hpsb_node_write(struct node_entry *ne, u64 addr,
                    quadlet_t *buffer, size_t length);
+static inline int hpsb_node_read(struct node_entry *ne, u64 addr,
+                                quadlet_t *buffer, size_t length)
+{
+       unsigned int g = ne->generation;
+
+       smp_rmb();
+       return hpsb_read(ne->host, ne->nodeid, g, addr, buffer, length);
+}
+static inline int hpsb_node_lock(struct node_entry *ne, u64 addr, int extcode,
+                                quadlet_t *buffer, quadlet_t arg)
+{
+       unsigned int g = ne->generation;
+
+       smp_rmb();
+       return hpsb_lock(ne->host, ne->nodeid, g, addr, extcode, buffer, arg);
+}
 int nodemgr_for_each_host(void *data, int (*cb)(struct hpsb_host *, void *));
 
 int init_ieee1394_nodemgr(void);
index 712220cef139469f93bd82ad5c97239c932d4841..7f16d75d2d89fa1137cad8651e765eb9b4a512e2 100644 (file)
@@ -54,7 +54,7 @@ void memcpy_toshmem(int card, void *dest, const void *src, size_t n)
        spin_unlock_irqrestore(&sc_adapter[card]->lock, flags);
        pr_debug("%s: set page to %#x\n",sc_adapter[card]->devicename,
                ((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE)>>14)|0x80);
-       pr_debug("%s: copying %d bytes from %#lx to %#lx\n",
+       pr_debug("%s: copying %zu bytes from %#lx to %#lx\n",
                sc_adapter[card]->devicename, n,
                (unsigned long) src,
                sc_adapter[card]->rambase + ((unsigned long) dest %0x4000));
index 01e3cffd03b8fd28dae613614f3efd10c04f2416..e2466425d9cad798edf40858183404408b319e3d 100644 (file)
@@ -1237,8 +1237,9 @@ static void end_sync_write(struct bio *bio, int error)
        update_head_pos(mirror, r1_bio);
 
        if (atomic_dec_and_test(&r1_bio->remaining)) {
-               md_done_sync(mddev, r1_bio->sectors, uptodate);
+               sector_t s = r1_bio->sectors;
                put_buf(r1_bio);
+               md_done_sync(mddev, s, uptodate);
        }
 }
 
index 6736d6dff981c8a1a5c12e773c3d788410a0f191..7301631abe0453a4791dec55ba0eff84912876c3 100644 (file)
@@ -1236,6 +1236,7 @@ static void end_sync_read(struct bio *bio, int error)
        /* for reconstruct, we always reschedule after a read.
         * for resync, only after all reads
         */
+       rdev_dec_pending(conf->mirrors[d].rdev, conf->mddev);
        if (test_bit(R10BIO_IsRecover, &r10_bio->state) ||
            atomic_dec_and_test(&r10_bio->remaining)) {
                /* we have read all the blocks,
@@ -1243,7 +1244,6 @@ static void end_sync_read(struct bio *bio, int error)
                 */
                reschedule_retry(r10_bio);
        }
-       rdev_dec_pending(conf->mirrors[d].rdev, conf->mddev);
 }
 
 static void end_sync_write(struct bio *bio, int error)
@@ -1264,11 +1264,13 @@ static void end_sync_write(struct bio *bio, int error)
 
        update_head_pos(i, r10_bio);
 
+       rdev_dec_pending(conf->mirrors[d].rdev, mddev);
        while (atomic_dec_and_test(&r10_bio->remaining)) {
                if (r10_bio->master_bio == NULL) {
                        /* the primary of several recovery bios */
-                       md_done_sync(mddev, r10_bio->sectors, 1);
+                       sector_t s = r10_bio->sectors;
                        put_buf(r10_bio);
+                       md_done_sync(mddev, s, 1);
                        break;
                } else {
                        r10bio_t *r10_bio2 = (r10bio_t *)r10_bio->master_bio;
@@ -1276,7 +1278,6 @@ static void end_sync_write(struct bio *bio, int error)
                        r10_bio = r10_bio2;
                }
        }
-       rdev_dec_pending(conf->mirrors[d].rdev, mddev);
 }
 
 /*
@@ -1749,8 +1750,6 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
        if (!go_faster && conf->nr_waiting)
                msleep_interruptible(1000);
 
-       bitmap_cond_end_sync(mddev->bitmap, sector_nr);
-
        /* Again, very different code for resync and recovery.
         * Both must result in an r10bio with a list of bios that
         * have bi_end_io, bi_sector, bi_bdev set,
@@ -1886,6 +1885,8 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
                /* resync. Schedule a read for every block at this virt offset */
                int count = 0;
 
+               bitmap_cond_end_sync(mddev->bitmap, sector_nr);
+
                if (!bitmap_start_sync(mddev->bitmap, sector_nr,
                                       &sync_blocks, mddev->degraded) &&
                    !conf->fullsync && !test_bit(MD_RECOVERY_REQUESTED, &mddev->recovery)) {
@@ -2010,13 +2011,13 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
        /* There is nowhere to write, so all non-sync
         * drives must be failed, so try the next chunk...
         */
-       {
-       sector_t sec = max_sector - sector_nr;
-       sectors_skipped += sec;
+       if (sector_nr + max_sync < max_sector)
+               max_sector = sector_nr + max_sync;
+
+       sectors_skipped += (max_sector - sector_nr);
        chunks_skipped ++;
        sector_nr = max_sector;
        goto skipped;
-       }
 }
 
 static int run(mddev_t *mddev)
index 40ebde53b3ce22443a60be62357c5722f64f256d..b0198691892a4a4ecab85d7febccf554c5dfe381 100644 (file)
@@ -51,6 +51,10 @@ comment "Supported SDMC DM1105 Adapters"
        depends on DVB_CORE && PCI && I2C
 source "drivers/media/dvb/dm1105/Kconfig"
 
+comment "Supported FireWire (IEEE 1394) Adapters"
+       depends on DVB_CORE && IEEE1394
+source "drivers/media/dvb/firewire/Kconfig"
+
 comment "Supported DVB Frontends"
        depends on DVB_CORE
 source "drivers/media/dvb/frontends/Kconfig"
index f91e9eb15e52effa8e9f15d1e0e2e4573beeae59..6092a5bb5a7d8901562e4efee7868cb003819d4f 100644 (file)
@@ -3,3 +3,5 @@
 #
 
 obj-y        := dvb-core/ frontends/ ttpci/ ttusb-dec/ ttusb-budget/ b2c2/ bt8xx/ dvb-usb/ pluto2/ siano/ dm1105/
+
+obj-$(CONFIG_DVB_FIREDTV)      += firewire/
diff --git a/drivers/media/dvb/firewire/Kconfig b/drivers/media/dvb/firewire/Kconfig
new file mode 100644 (file)
index 0000000..6902825
--- /dev/null
@@ -0,0 +1,22 @@
+config DVB_FIREDTV
+       tristate "FireDTV and FloppyDTV"
+       depends on DVB_CORE && IEEE1394
+       help
+         Support for DVB receivers from Digital Everywhere
+         which are connected via IEEE 1394 (FireWire).
+
+         These devices don't have an MPEG decoder built in,
+         so you need an external software decoder to watch TV.
+
+         To compile this driver as a module, say M here:
+         the module will be called firedtv.
+
+if DVB_FIREDTV
+
+config DVB_FIREDTV_IEEE1394
+       def_bool IEEE1394
+
+config DVB_FIREDTV_INPUT
+       def_bool INPUT = y || (INPUT = m && DVB_FIREDTV = m)
+
+endif # DVB_FIREDTV
diff --git a/drivers/media/dvb/firewire/Makefile b/drivers/media/dvb/firewire/Makefile
new file mode 100644 (file)
index 0000000..2034695
--- /dev/null
@@ -0,0 +1,8 @@
+obj-$(CONFIG_DVB_FIREDTV) += firedtv.o
+
+firedtv-y := firedtv-avc.o firedtv-ci.o firedtv-dvb.o firedtv-fe.o
+firedtv-$(CONFIG_DVB_FIREDTV_IEEE1394) += firedtv-1394.o
+firedtv-$(CONFIG_DVB_FIREDTV_INPUT)    += firedtv-rc.o
+
+ccflags-y += -Idrivers/media/dvb/dvb-core
+ccflags-$(CONFIG_DVB_FIREDTV_IEEE1394) += -Idrivers/ieee1394
diff --git a/drivers/media/dvb/firewire/firedtv-1394.c b/drivers/media/dvb/firewire/firedtv-1394.c
new file mode 100644 (file)
index 0000000..4e20765
--- /dev/null
@@ -0,0 +1,285 @@
+/*
+ * FireDTV driver (formerly known as FireSAT)
+ *
+ * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
+ * Copyright (C) 2007-2008 Ben Backx <ben@bbackx.com>
+ * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <dma.h>
+#include <csr1212.h>
+#include <highlevel.h>
+#include <hosts.h>
+#include <ieee1394.h>
+#include <iso.h>
+#include <nodemgr.h>
+
+#include "firedtv.h"
+
+static LIST_HEAD(node_list);
+static DEFINE_SPINLOCK(node_list_lock);
+
+#define FIREWIRE_HEADER_SIZE   4
+#define CIP_HEADER_SIZE                8
+
+static void rawiso_activity_cb(struct hpsb_iso *iso)
+{
+       struct firedtv *f, *fdtv = NULL;
+       unsigned int i, num, packet;
+       unsigned char *buf;
+       unsigned long flags;
+       int count;
+
+       spin_lock_irqsave(&node_list_lock, flags);
+       list_for_each_entry(f, &node_list, list)
+               if (f->backend_data == iso) {
+                       fdtv = f;
+                       break;
+               }
+       spin_unlock_irqrestore(&node_list_lock, flags);
+
+       packet = iso->first_packet;
+       num = hpsb_iso_n_ready(iso);
+
+       if (!fdtv) {
+               dev_err(fdtv->device, "received at unknown iso channel\n");
+               goto out;
+       }
+
+       for (i = 0; i < num; i++, packet = (packet + 1) % iso->buf_packets) {
+               buf = dma_region_i(&iso->data_buf, unsigned char,
+                       iso->infos[packet].offset + CIP_HEADER_SIZE);
+               count = (iso->infos[packet].len - CIP_HEADER_SIZE) /
+                       (188 + FIREWIRE_HEADER_SIZE);
+
+               /* ignore empty packet */
+               if (iso->infos[packet].len <= CIP_HEADER_SIZE)
+                       continue;
+
+               while (count--) {
+                       if (buf[FIREWIRE_HEADER_SIZE] == 0x47)
+                               dvb_dmx_swfilter_packets(&fdtv->demux,
+                                               &buf[FIREWIRE_HEADER_SIZE], 1);
+                       else
+                               dev_err(fdtv->device,
+                                       "skipping invalid packet\n");
+                       buf += 188 + FIREWIRE_HEADER_SIZE;
+               }
+       }
+out:
+       hpsb_iso_recv_release_packets(iso, num);
+}
+
+static inline struct node_entry *node_of(struct firedtv *fdtv)
+{
+       return container_of(fdtv->device, struct unit_directory, device)->ne;
+}
+
+static int node_lock(struct firedtv *fdtv, u64 addr, void *data, __be32 arg)
+{
+       return hpsb_node_lock(node_of(fdtv), addr, EXTCODE_COMPARE_SWAP, data,
+                             (__force quadlet_t)arg);
+}
+
+static int node_read(struct firedtv *fdtv, u64 addr, void *data, size_t len)
+{
+       return hpsb_node_read(node_of(fdtv), addr, data, len);
+}
+
+static int node_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
+{
+       return hpsb_node_write(node_of(fdtv), addr, data, len);
+}
+
+#define FDTV_ISO_BUFFER_PACKETS 256
+#define FDTV_ISO_BUFFER_SIZE (FDTV_ISO_BUFFER_PACKETS * 200)
+
+static int start_iso(struct firedtv *fdtv)
+{
+       struct hpsb_iso *iso_handle;
+       int ret;
+
+       iso_handle = hpsb_iso_recv_init(node_of(fdtv)->host,
+                               FDTV_ISO_BUFFER_SIZE, FDTV_ISO_BUFFER_PACKETS,
+                               fdtv->isochannel, HPSB_ISO_DMA_DEFAULT,
+                               -1, /* stat.config.irq_interval */
+                               rawiso_activity_cb);
+       if (iso_handle == NULL) {
+               dev_err(fdtv->device, "cannot initialize iso receive\n");
+               return -ENOMEM;
+       }
+       fdtv->backend_data = iso_handle;
+
+       ret = hpsb_iso_recv_start(iso_handle, -1, -1, 0);
+       if (ret != 0) {
+               dev_err(fdtv->device, "cannot start iso receive\n");
+               hpsb_iso_shutdown(iso_handle);
+               fdtv->backend_data = NULL;
+       }
+       return ret;
+}
+
+static void stop_iso(struct firedtv *fdtv)
+{
+       struct hpsb_iso *iso_handle = fdtv->backend_data;
+
+       if (iso_handle != NULL) {
+               hpsb_iso_stop(iso_handle);
+               hpsb_iso_shutdown(iso_handle);
+       }
+       fdtv->backend_data = NULL;
+}
+
+static const struct firedtv_backend fdtv_1394_backend = {
+       .lock           = node_lock,
+       .read           = node_read,
+       .write          = node_write,
+       .start_iso      = start_iso,
+       .stop_iso       = stop_iso,
+};
+
+static void fcp_request(struct hpsb_host *host, int nodeid, int direction,
+                       int cts, u8 *data, size_t length)
+{
+       struct firedtv *f, *fdtv = NULL;
+       unsigned long flags;
+       int su;
+
+       if (length == 0 || (data[0] & 0xf0) != 0)
+               return;
+
+       su = data[1] & 0x7;
+
+       spin_lock_irqsave(&node_list_lock, flags);
+       list_for_each_entry(f, &node_list, list)
+               if (node_of(f)->host == host &&
+                   node_of(f)->nodeid == nodeid &&
+                   (f->subunit == su || (f->subunit == 0 && su == 0x7))) {
+                       fdtv = f;
+                       break;
+               }
+       spin_unlock_irqrestore(&node_list_lock, flags);
+
+       if (fdtv)
+               avc_recv(fdtv, data, length);
+}
+
+static int node_probe(struct device *dev)
+{
+       struct unit_directory *ud =
+                       container_of(dev, struct unit_directory, device);
+       struct firedtv *fdtv;
+       int kv_len, err;
+       void *kv_str;
+
+       kv_len = (ud->model_name_kv->value.leaf.len - 2) * sizeof(quadlet_t);
+       kv_str = CSR1212_TEXTUAL_DESCRIPTOR_LEAF_DATA(ud->model_name_kv);
+
+       fdtv = fdtv_alloc(dev, &fdtv_1394_backend, kv_str, kv_len);
+       if (!fdtv)
+               return -ENOMEM;
+
+       /*
+        * Work around a bug in udev's path_id script:  Use the fw-host's dev
+        * instead of the unit directory's dev as parent of the input device.
+        */
+       err = fdtv_register_rc(fdtv, dev->parent->parent);
+       if (err)
+               goto fail_free;
+
+       spin_lock_irq(&node_list_lock);
+       list_add_tail(&fdtv->list, &node_list);
+       spin_unlock_irq(&node_list_lock);
+
+       err = avc_identify_subunit(fdtv);
+       if (err)
+               goto fail;
+
+       err = fdtv_dvb_register(fdtv);
+       if (err)
+               goto fail;
+
+       avc_register_remote_control(fdtv);
+       return 0;
+fail:
+       spin_lock_irq(&node_list_lock);
+       list_del(&fdtv->list);
+       spin_unlock_irq(&node_list_lock);
+       fdtv_unregister_rc(fdtv);
+fail_free:
+       kfree(fdtv);
+       return err;
+}
+
+static int node_remove(struct device *dev)
+{
+       struct firedtv *fdtv = dev->driver_data;
+
+       fdtv_dvb_unregister(fdtv);
+
+       spin_lock_irq(&node_list_lock);
+       list_del(&fdtv->list);
+       spin_unlock_irq(&node_list_lock);
+
+       cancel_work_sync(&fdtv->remote_ctrl_work);
+       fdtv_unregister_rc(fdtv);
+
+       kfree(fdtv);
+       return 0;
+}
+
+static int node_update(struct unit_directory *ud)
+{
+       struct firedtv *fdtv = ud->device.driver_data;
+
+       if (fdtv->isochannel >= 0)
+               cmp_establish_pp_connection(fdtv, fdtv->subunit,
+                                           fdtv->isochannel);
+       return 0;
+}
+
+static struct hpsb_protocol_driver fdtv_driver = {
+       .name           = "firedtv",
+       .update         = node_update,
+       .driver         = {
+               .probe  = node_probe,
+               .remove = node_remove,
+       },
+};
+
+static struct hpsb_highlevel fdtv_highlevel = {
+       .name           = "firedtv",
+       .fcp_request    = fcp_request,
+};
+
+int __init fdtv_1394_init(struct ieee1394_device_id id_table[])
+{
+       int ret;
+
+       hpsb_register_highlevel(&fdtv_highlevel);
+       fdtv_driver.id_table = id_table;
+       ret = hpsb_register_protocol(&fdtv_driver);
+       if (ret) {
+               printk(KERN_ERR "firedtv: failed to register protocol\n");
+               hpsb_unregister_highlevel(&fdtv_highlevel);
+       }
+       return ret;
+}
+
+void __exit fdtv_1394_exit(void)
+{
+       hpsb_unregister_protocol(&fdtv_driver);
+       hpsb_unregister_highlevel(&fdtv_highlevel);
+}
diff --git a/drivers/media/dvb/firewire/firedtv-avc.c b/drivers/media/dvb/firewire/firedtv-avc.c
new file mode 100644 (file)
index 0000000..b55d9cc
--- /dev/null
@@ -0,0 +1,1315 @@
+/*
+ * FireDTV driver (formerly known as FireSAT)
+ *
+ * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
+ * Copyright (C) 2008 Ben Backx <ben@bbackx.com>
+ * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ */
+
+#include <linux/bug.h>
+#include <linux/crc32.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+#include <linux/stringify.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#include "firedtv.h"
+
+#define FCP_COMMAND_REGISTER           0xfffff0000b00ULL
+
+#define AVC_CTYPE_CONTROL              0x0
+#define AVC_CTYPE_STATUS               0x1
+#define AVC_CTYPE_NOTIFY               0x3
+
+#define AVC_RESPONSE_ACCEPTED          0x9
+#define AVC_RESPONSE_STABLE            0xc
+#define AVC_RESPONSE_CHANGED           0xd
+#define AVC_RESPONSE_INTERIM           0xf
+
+#define AVC_SUBUNIT_TYPE_TUNER         (0x05 << 3)
+#define AVC_SUBUNIT_TYPE_UNIT          (0x1f << 3)
+
+#define AVC_OPCODE_VENDOR              0x00
+#define AVC_OPCODE_READ_DESCRIPTOR     0x09
+#define AVC_OPCODE_DSIT                        0xc8
+#define AVC_OPCODE_DSD                 0xcb
+
+#define DESCRIPTOR_TUNER_STATUS        0x80
+#define DESCRIPTOR_SUBUNIT_IDENTIFIER  0x00
+
+#define SFE_VENDOR_DE_COMPANYID_0      0x00 /* OUI of Digital Everywhere */
+#define SFE_VENDOR_DE_COMPANYID_1      0x12
+#define SFE_VENDOR_DE_COMPANYID_2      0x87
+
+#define SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL 0x0a
+#define SFE_VENDOR_OPCODE_LNB_CONTROL          0x52
+#define SFE_VENDOR_OPCODE_TUNE_QPSK            0x58 /* for DVB-S */
+
+#define SFE_VENDOR_OPCODE_GET_FIRMWARE_VERSION 0x00
+#define SFE_VENDOR_OPCODE_HOST2CA              0x56
+#define SFE_VENDOR_OPCODE_CA2HOST              0x57
+#define SFE_VENDOR_OPCODE_CISTATUS             0x59
+#define SFE_VENDOR_OPCODE_TUNE_QPSK2           0x60 /* for DVB-S2 */
+
+#define SFE_VENDOR_TAG_CA_RESET                        0x00
+#define SFE_VENDOR_TAG_CA_APPLICATION_INFO     0x01
+#define SFE_VENDOR_TAG_CA_PMT                  0x02
+#define SFE_VENDOR_TAG_CA_DATE_TIME            0x04
+#define SFE_VENDOR_TAG_CA_MMI                  0x05
+#define SFE_VENDOR_TAG_CA_ENTER_MENU           0x07
+
+#define EN50221_LIST_MANAGEMENT_ONLY   0x03
+#define EN50221_TAG_APP_INFO           0x9f8021
+#define EN50221_TAG_CA_INFO            0x9f8031
+
+struct avc_command_frame {
+       int length;
+       u8 ctype;
+       u8 subunit;
+       u8 opcode;
+       u8 operand[509];
+};
+
+struct avc_response_frame {
+       int length;
+       u8 response;
+       u8 subunit;
+       u8 opcode;
+       u8 operand[509];
+};
+
+#define AVC_DEBUG_FCP_SUBACTIONS       1
+#define AVC_DEBUG_FCP_PAYLOADS         2
+
+static int avc_debug;
+module_param_named(debug, avc_debug, int, 0644);
+MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
+       ", FCP subactions = "   __stringify(AVC_DEBUG_FCP_SUBACTIONS)
+       ", FCP payloads = "     __stringify(AVC_DEBUG_FCP_PAYLOADS)
+       ", or all = -1)");
+
+static const char *debug_fcp_ctype(unsigned int ctype)
+{
+       static const char *ctypes[] = {
+               [0x0] = "CONTROL",              [0x1] = "STATUS",
+               [0x2] = "SPECIFIC INQUIRY",     [0x3] = "NOTIFY",
+               [0x4] = "GENERAL INQUIRY",      [0x8] = "NOT IMPLEMENTED",
+               [0x9] = "ACCEPTED",             [0xa] = "REJECTED",
+               [0xb] = "IN TRANSITION",        [0xc] = "IMPLEMENTED/STABLE",
+               [0xd] = "CHANGED",              [0xf] = "INTERIM",
+       };
+       const char *ret = ctype < ARRAY_SIZE(ctypes) ? ctypes[ctype] : NULL;
+
+       return ret ? ret : "?";
+}
+
+static const char *debug_fcp_opcode(unsigned int opcode,
+                                   const u8 *data, size_t length)
+{
+       switch (opcode) {
+       case AVC_OPCODE_VENDOR:                 break;
+       case AVC_OPCODE_READ_DESCRIPTOR:        return "ReadDescriptor";
+       case AVC_OPCODE_DSIT:                   return "DirectSelectInfo.Type";
+       case AVC_OPCODE_DSD:                    return "DirectSelectData";
+       default:                                return "?";
+       }
+
+       if (length < 7 ||
+           data[3] != SFE_VENDOR_DE_COMPANYID_0 ||
+           data[4] != SFE_VENDOR_DE_COMPANYID_1 ||
+           data[5] != SFE_VENDOR_DE_COMPANYID_2)
+               return "Vendor";
+
+       switch (data[6]) {
+       case SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL: return "RegisterRC";
+       case SFE_VENDOR_OPCODE_LNB_CONTROL:             return "LNBControl";
+       case SFE_VENDOR_OPCODE_TUNE_QPSK:               return "TuneQPSK";
+       case SFE_VENDOR_OPCODE_HOST2CA:                 return "Host2CA";
+       case SFE_VENDOR_OPCODE_CA2HOST:                 return "CA2Host";
+       }
+       return "Vendor";
+}
+
+static void debug_fcp(const u8 *data, size_t length)
+{
+       unsigned int subunit_type, subunit_id, op;
+       const char *prefix = data[0] > 7 ? "FCP <- " : "FCP -> ";
+
+       if (avc_debug & AVC_DEBUG_FCP_SUBACTIONS) {
+               subunit_type = data[1] >> 3;
+               subunit_id = data[1] & 7;
+               op = subunit_type == 0x1e || subunit_id == 5 ? ~0 : data[2];
+               printk(KERN_INFO "%ssu=%x.%x l=%d: %-8s - %s\n",
+                      prefix, subunit_type, subunit_id, length,
+                      debug_fcp_ctype(data[0]),
+                      debug_fcp_opcode(op, data, length));
+       }
+
+       if (avc_debug & AVC_DEBUG_FCP_PAYLOADS)
+               print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_NONE, 16, 1,
+                              data, length, false);
+}
+
+static int __avc_write(struct firedtv *fdtv,
+               const struct avc_command_frame *c, struct avc_response_frame *r)
+{
+       int err, retry;
+
+       if (r)
+               fdtv->avc_reply_received = false;
+
+       for (retry = 0; retry < 6; retry++) {
+               if (unlikely(avc_debug))
+                       debug_fcp(&c->ctype, c->length);
+
+               err = fdtv->backend->write(fdtv, FCP_COMMAND_REGISTER,
+                                          (void *)&c->ctype, c->length);
+               if (err) {
+                       fdtv->avc_reply_received = true;
+                       dev_err(fdtv->device, "FCP command write failed\n");
+                       return err;
+               }
+
+               if (!r)
+                       return 0;
+
+               /*
+                * AV/C specs say that answers should be sent within 150 ms.
+                * Time out after 200 ms.
+                */
+               if (wait_event_timeout(fdtv->avc_wait,
+                                      fdtv->avc_reply_received,
+                                      msecs_to_jiffies(200)) != 0) {
+                       r->length = fdtv->response_length;
+                       memcpy(&r->response, fdtv->response, r->length);
+
+                       return 0;
+               }
+       }
+       dev_err(fdtv->device, "FCP response timed out\n");
+       return -ETIMEDOUT;
+}
+
+static int avc_write(struct firedtv *fdtv,
+               const struct avc_command_frame *c, struct avc_response_frame *r)
+{
+       int ret;
+
+       if (mutex_lock_interruptible(&fdtv->avc_mutex))
+               return -EINTR;
+
+       ret = __avc_write(fdtv, c, r);
+
+       mutex_unlock(&fdtv->avc_mutex);
+       return ret;
+}
+
+int avc_recv(struct firedtv *fdtv, void *data, size_t length)
+{
+       struct avc_response_frame *r =
+                       data - offsetof(struct avc_response_frame, response);
+
+       if (unlikely(avc_debug))
+               debug_fcp(data, length);
+
+       if (length >= 8 &&
+           r->operand[0] == SFE_VENDOR_DE_COMPANYID_0 &&
+           r->operand[1] == SFE_VENDOR_DE_COMPANYID_1 &&
+           r->operand[2] == SFE_VENDOR_DE_COMPANYID_2 &&
+           r->operand[3] == SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL) {
+               if (r->response == AVC_RESPONSE_CHANGED) {
+                       fdtv_handle_rc(fdtv,
+                           r->operand[4] << 8 | r->operand[5]);
+                       schedule_work(&fdtv->remote_ctrl_work);
+               } else if (r->response != AVC_RESPONSE_INTERIM) {
+                       dev_info(fdtv->device,
+                                "remote control result = %d\n", r->response);
+               }
+               return 0;
+       }
+
+       if (fdtv->avc_reply_received) {
+               dev_err(fdtv->device, "out-of-order AVC response, ignored\n");
+               return -EIO;
+       }
+
+       memcpy(fdtv->response, data, length);
+       fdtv->response_length = length;
+
+       fdtv->avc_reply_received = true;
+       wake_up(&fdtv->avc_wait);
+
+       return 0;
+}
+
+/*
+ * tuning command for setting the relative LNB frequency
+ * (not supported by the AVC standard)
+ */
+static void avc_tuner_tuneqpsk(struct firedtv *fdtv,
+                              struct dvb_frontend_parameters *params,
+                              struct avc_command_frame *c)
+{
+       c->opcode = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_TUNE_QPSK;
+
+       c->operand[4] = (params->frequency >> 24) & 0xff;
+       c->operand[5] = (params->frequency >> 16) & 0xff;
+       c->operand[6] = (params->frequency >> 8) & 0xff;
+       c->operand[7] = params->frequency & 0xff;
+
+       c->operand[8] = ((params->u.qpsk.symbol_rate / 1000) >> 8) & 0xff;
+       c->operand[9] = (params->u.qpsk.symbol_rate / 1000) & 0xff;
+
+       switch (params->u.qpsk.fec_inner) {
+       case FEC_1_2:   c->operand[10] = 0x1; break;
+       case FEC_2_3:   c->operand[10] = 0x2; break;
+       case FEC_3_4:   c->operand[10] = 0x3; break;
+       case FEC_5_6:   c->operand[10] = 0x4; break;
+       case FEC_7_8:   c->operand[10] = 0x5; break;
+       case FEC_4_5:
+       case FEC_8_9:
+       case FEC_AUTO:
+       default:        c->operand[10] = 0x0;
+       }
+
+       if (fdtv->voltage == 0xff)
+               c->operand[11] = 0xff;
+       else if (fdtv->voltage == SEC_VOLTAGE_18) /* polarisation */
+               c->operand[11] = 0;
+       else
+               c->operand[11] = 1;
+
+       if (fdtv->tone == 0xff)
+               c->operand[12] = 0xff;
+       else if (fdtv->tone == SEC_TONE_ON) /* band */
+               c->operand[12] = 1;
+       else
+               c->operand[12] = 0;
+
+       if (fdtv->type == FIREDTV_DVB_S2) {
+               c->operand[13] = 0x1;
+               c->operand[14] = 0xff;
+               c->operand[15] = 0xff;
+               c->length = 20;
+       } else {
+               c->length = 16;
+       }
+}
+
+static void avc_tuner_dsd_dvb_c(struct dvb_frontend_parameters *params,
+                               struct avc_command_frame *c)
+{
+       c->opcode = AVC_OPCODE_DSD;
+
+       c->operand[0] = 0;    /* source plug */
+       c->operand[1] = 0xd2; /* subfunction replace */
+       c->operand[2] = 0x20; /* system id = DVB */
+       c->operand[3] = 0x00; /* antenna number */
+       c->operand[4] = 0x11; /* system_specific_multiplex selection_length */
+
+       /* multiplex_valid_flags, high byte */
+       c->operand[5] =   0 << 7 /* reserved */
+                       | 0 << 6 /* Polarisation */
+                       | 0 << 5 /* Orbital_Pos */
+                       | 1 << 4 /* Frequency */
+                       | 1 << 3 /* Symbol_Rate */
+                       | 0 << 2 /* FEC_outer */
+                       | (params->u.qam.fec_inner  != FEC_AUTO ? 1 << 1 : 0)
+                       | (params->u.qam.modulation != QAM_AUTO ? 1 << 0 : 0);
+
+       /* multiplex_valid_flags, low byte */
+       c->operand[6] =   0 << 7 /* NetworkID */
+                       | 0 << 0 /* reserved */ ;
+
+       c->operand[7]  = 0x00;
+       c->operand[8]  = 0x00;
+       c->operand[9]  = 0x00;
+       c->operand[10] = 0x00;
+
+       c->operand[11] = (((params->frequency / 4000) >> 16) & 0xff) | (2 << 6);
+       c->operand[12] = ((params->frequency / 4000) >> 8) & 0xff;
+       c->operand[13] = (params->frequency / 4000) & 0xff;
+       c->operand[14] = ((params->u.qpsk.symbol_rate / 1000) >> 12) & 0xff;
+       c->operand[15] = ((params->u.qpsk.symbol_rate / 1000) >> 4) & 0xff;
+       c->operand[16] = ((params->u.qpsk.symbol_rate / 1000) << 4) & 0xf0;
+       c->operand[17] = 0x00;
+
+       switch (params->u.qpsk.fec_inner) {
+       case FEC_1_2:   c->operand[18] = 0x1; break;
+       case FEC_2_3:   c->operand[18] = 0x2; break;
+       case FEC_3_4:   c->operand[18] = 0x3; break;
+       case FEC_5_6:   c->operand[18] = 0x4; break;
+       case FEC_7_8:   c->operand[18] = 0x5; break;
+       case FEC_8_9:   c->operand[18] = 0x6; break;
+       case FEC_4_5:   c->operand[18] = 0x8; break;
+       case FEC_AUTO:
+       default:        c->operand[18] = 0x0;
+       }
+
+       switch (params->u.qam.modulation) {
+       case QAM_16:    c->operand[19] = 0x08; break;
+       case QAM_32:    c->operand[19] = 0x10; break;
+       case QAM_64:    c->operand[19] = 0x18; break;
+       case QAM_128:   c->operand[19] = 0x20; break;
+       case QAM_256:   c->operand[19] = 0x28; break;
+       case QAM_AUTO:
+       default:        c->operand[19] = 0x00;
+       }
+
+       c->operand[20] = 0x00;
+       c->operand[21] = 0x00;
+       /* Nr_of_dsd_sel_specs = 0 -> no PIDs are transmitted */
+       c->operand[22] = 0x00;
+
+       c->length = 28;
+}
+
+static void avc_tuner_dsd_dvb_t(struct dvb_frontend_parameters *params,
+                               struct avc_command_frame *c)
+{
+       struct dvb_ofdm_parameters *ofdm = &params->u.ofdm;
+
+       c->opcode = AVC_OPCODE_DSD;
+
+       c->operand[0] = 0;    /* source plug */
+       c->operand[1] = 0xd2; /* subfunction replace */
+       c->operand[2] = 0x20; /* system id = DVB */
+       c->operand[3] = 0x00; /* antenna number */
+       c->operand[4] = 0x0c; /* system_specific_multiplex selection_length */
+
+       /* multiplex_valid_flags, high byte */
+       c->operand[5] =
+             0 << 7 /* reserved */
+           | 1 << 6 /* CenterFrequency */
+           | (ofdm->bandwidth      != BANDWIDTH_AUTO        ? 1 << 5 : 0)
+           | (ofdm->constellation  != QAM_AUTO              ? 1 << 4 : 0)
+           | (ofdm->hierarchy_information != HIERARCHY_AUTO ? 1 << 3 : 0)
+           | (ofdm->code_rate_HP   != FEC_AUTO              ? 1 << 2 : 0)
+           | (ofdm->code_rate_LP   != FEC_AUTO              ? 1 << 1 : 0)
+           | (ofdm->guard_interval != GUARD_INTERVAL_AUTO   ? 1 << 0 : 0);
+
+       /* multiplex_valid_flags, low byte */
+       c->operand[6] =
+             0 << 7 /* NetworkID */
+           | (ofdm->transmission_mode != TRANSMISSION_MODE_AUTO ? 1 << 6 : 0)
+           | 0 << 5 /* OtherFrequencyFlag */
+           | 0 << 0 /* reserved */ ;
+
+       c->operand[7]  = 0x0;
+       c->operand[8]  = (params->frequency / 10) >> 24;
+       c->operand[9]  = ((params->frequency / 10) >> 16) & 0xff;
+       c->operand[10] = ((params->frequency / 10) >>  8) & 0xff;
+       c->operand[11] = (params->frequency / 10) & 0xff;
+
+       switch (ofdm->bandwidth) {
+       case BANDWIDTH_7_MHZ:   c->operand[12] = 0x20; break;
+       case BANDWIDTH_8_MHZ:
+       case BANDWIDTH_6_MHZ:   /* not defined by AVC spec */
+       case BANDWIDTH_AUTO:
+       default:                c->operand[12] = 0x00;
+       }
+
+       switch (ofdm->constellation) {
+       case QAM_16:    c->operand[13] = 1 << 6; break;
+       case QAM_64:    c->operand[13] = 2 << 6; break;
+       case QPSK:
+       default:        c->operand[13] = 0x00;
+       }
+
+       switch (ofdm->hierarchy_information) {
+       case HIERARCHY_1:       c->operand[13] |= 1 << 3; break;
+       case HIERARCHY_2:       c->operand[13] |= 2 << 3; break;
+       case HIERARCHY_4:       c->operand[13] |= 3 << 3; break;
+       case HIERARCHY_AUTO:
+       case HIERARCHY_NONE:
+       default:                break;
+       }
+
+       switch (ofdm->code_rate_HP) {
+       case FEC_2_3:   c->operand[13] |= 1; break;
+       case FEC_3_4:   c->operand[13] |= 2; break;
+       case FEC_5_6:   c->operand[13] |= 3; break;
+       case FEC_7_8:   c->operand[13] |= 4; break;
+       case FEC_1_2:
+       default:        break;
+       }
+
+       switch (ofdm->code_rate_LP) {
+       case FEC_2_3:   c->operand[14] = 1 << 5; break;
+       case FEC_3_4:   c->operand[14] = 2 << 5; break;
+       case FEC_5_6:   c->operand[14] = 3 << 5; break;
+       case FEC_7_8:   c->operand[14] = 4 << 5; break;
+       case FEC_1_2:
+       default:        c->operand[14] = 0x00; break;
+       }
+
+       switch (ofdm->guard_interval) {
+       case GUARD_INTERVAL_1_16:       c->operand[14] |= 1 << 3; break;
+       case GUARD_INTERVAL_1_8:        c->operand[14] |= 2 << 3; break;
+       case GUARD_INTERVAL_1_4:        c->operand[14] |= 3 << 3; break;
+       case GUARD_INTERVAL_1_32:
+       case GUARD_INTERVAL_AUTO:
+       default:                        break;
+       }
+
+       switch (ofdm->transmission_mode) {
+       case TRANSMISSION_MODE_8K:      c->operand[14] |= 1 << 1; break;
+       case TRANSMISSION_MODE_2K:
+       case TRANSMISSION_MODE_AUTO:
+       default:                        break;
+       }
+
+       c->operand[15] = 0x00; /* network_ID[0] */
+       c->operand[16] = 0x00; /* network_ID[1] */
+       /* Nr_of_dsd_sel_specs = 0 -> no PIDs are transmitted */
+       c->operand[17] = 0x00;
+
+       c->length = 24;
+}
+
+int avc_tuner_dsd(struct firedtv *fdtv,
+                 struct dvb_frontend_parameters *params)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+
+       switch (fdtv->type) {
+       case FIREDTV_DVB_S:
+       case FIREDTV_DVB_S2: avc_tuner_tuneqpsk(fdtv, params, c); break;
+       case FIREDTV_DVB_C: avc_tuner_dsd_dvb_c(params, c); break;
+       case FIREDTV_DVB_T: avc_tuner_dsd_dvb_t(params, c); break;
+       default:
+               BUG();
+       }
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       msleep(500);
+#if 0
+       /* FIXME: */
+       /* u8 *status was an out-parameter of avc_tuner_dsd, unused by caller */
+       if (status)
+               *status = r->operand[2];
+#endif
+       return 0;
+}
+
+int avc_tuner_set_pids(struct firedtv *fdtv, unsigned char pidc, u16 pid[])
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
+       int pos, k;
+
+       if (pidc > 16 && pidc != 0xff)
+               return -EINVAL;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_DSD;
+
+       c->operand[0] = 0;      /* source plug */
+       c->operand[1] = 0xd2;   /* subfunction replace */
+       c->operand[2] = 0x20;   /* system id = DVB */
+       c->operand[3] = 0x00;   /* antenna number */
+       c->operand[4] = 0x00;   /* system_specific_multiplex selection_length */
+       c->operand[5] = pidc;   /* Nr_of_dsd_sel_specs */
+
+       pos = 6;
+       if (pidc != 0xff)
+               for (k = 0; k < pidc; k++) {
+                       c->operand[pos++] = 0x13; /* flowfunction relay */
+                       c->operand[pos++] = 0x80; /* dsd_sel_spec_valid_flags -> PID */
+                       c->operand[pos++] = (pid[k] >> 8) & 0x1f;
+                       c->operand[pos++] = pid[k] & 0xff;
+                       c->operand[pos++] = 0x00; /* tableID */
+                       c->operand[pos++] = 0x00; /* filter_length */
+               }
+
+       c->length = ALIGN(3 + pos, 4);
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       msleep(50);
+       return 0;
+}
+
+int avc_tuner_get_ts(struct firedtv *fdtv)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
+       int sl;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_DSIT;
+
+       sl = fdtv->type == FIREDTV_DVB_T ? 0x0c : 0x11;
+
+       c->operand[0] = 0;      /* source plug */
+       c->operand[1] = 0xd2;   /* subfunction replace */
+       c->operand[2] = 0xff;   /* status */
+       c->operand[3] = 0x20;   /* system id = DVB */
+       c->operand[4] = 0x00;   /* antenna number */
+       c->operand[5] = 0x0;    /* system_specific_search_flags */
+       c->operand[6] = sl;     /* system_specific_multiplex selection_length */
+       c->operand[7] = 0x00;   /* valid_flags [0] */
+       c->operand[8] = 0x00;   /* valid_flags [1] */
+       c->operand[7 + sl] = 0x00; /* nr_of_dsit_sel_specs (always 0) */
+
+       c->length = fdtv->type == FIREDTV_DVB_T ? 24 : 28;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       msleep(250);
+       return 0;
+}
+
+int avc_identify_subunit(struct firedtv *fdtv)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_READ_DESCRIPTOR;
+
+       c->operand[0] = DESCRIPTOR_SUBUNIT_IDENTIFIER;
+       c->operand[1] = 0xff;
+       c->operand[2] = 0x00;
+       c->operand[3] = 0x00; /* length highbyte */
+       c->operand[4] = 0x08; /* length lowbyte  */
+       c->operand[5] = 0x00; /* offset highbyte */
+       c->operand[6] = 0x0d; /* offset lowbyte  */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       if ((r->response != AVC_RESPONSE_STABLE &&
+            r->response != AVC_RESPONSE_ACCEPTED) ||
+           (r->operand[3] << 8) + r->operand[4] != 8) {
+               dev_err(fdtv->device, "cannot read subunit identifier\n");
+               return -EINVAL;
+       }
+       return 0;
+}
+
+#define SIZEOF_ANTENNA_INPUT_INFO 22
+
+int avc_tuner_status(struct firedtv *fdtv, struct firedtv_tuner_status *stat)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+       int length;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_READ_DESCRIPTOR;
+
+       c->operand[0] = DESCRIPTOR_TUNER_STATUS;
+       c->operand[1] = 0xff;   /* read_result_status */
+       c->operand[2] = 0x00;   /* reserved */
+       c->operand[3] = 0;      /* SIZEOF_ANTENNA_INPUT_INFO >> 8; */
+       c->operand[4] = 0;      /* SIZEOF_ANTENNA_INPUT_INFO & 0xff; */
+       c->operand[5] = 0x00;
+       c->operand[6] = 0x00;
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       if (r->response != AVC_RESPONSE_STABLE &&
+           r->response != AVC_RESPONSE_ACCEPTED) {
+               dev_err(fdtv->device, "cannot read tuner status\n");
+               return -EINVAL;
+       }
+
+       length = r->operand[9];
+       if (r->operand[1] != 0x10 || length != SIZEOF_ANTENNA_INPUT_INFO) {
+               dev_err(fdtv->device, "got invalid tuner status\n");
+               return -EINVAL;
+       }
+
+       stat->active_system             = r->operand[10];
+       stat->searching                 = r->operand[11] >> 7 & 1;
+       stat->moving                    = r->operand[11] >> 6 & 1;
+       stat->no_rf                     = r->operand[11] >> 5 & 1;
+       stat->input                     = r->operand[12] >> 7 & 1;
+       stat->selected_antenna          = r->operand[12] & 0x7f;
+       stat->ber                       = r->operand[13] << 24 |
+                                         r->operand[14] << 16 |
+                                         r->operand[15] << 8 |
+                                         r->operand[16];
+       stat->signal_strength           = r->operand[17];
+       stat->raster_frequency          = r->operand[18] >> 6 & 2;
+       stat->rf_frequency              = (r->operand[18] & 0x3f) << 16 |
+                                         r->operand[19] << 8 |
+                                         r->operand[20];
+       stat->man_dep_info_length       = r->operand[21];
+       stat->front_end_error           = r->operand[22] >> 4 & 1;
+       stat->antenna_error             = r->operand[22] >> 3 & 1;
+       stat->front_end_power_status    = r->operand[22] >> 1 & 1;
+       stat->power_supply              = r->operand[22] & 1;
+       stat->carrier_noise_ratio       = r->operand[23] << 8 |
+                                         r->operand[24];
+       stat->power_supply_voltage      = r->operand[27];
+       stat->antenna_voltage           = r->operand[28];
+       stat->firewire_bus_voltage      = r->operand[29];
+       stat->ca_mmi                    = r->operand[30] & 1;
+       stat->ca_pmt_reply              = r->operand[31] >> 7 & 1;
+       stat->ca_date_time_request      = r->operand[31] >> 6 & 1;
+       stat->ca_application_info       = r->operand[31] >> 5 & 1;
+       stat->ca_module_present_status  = r->operand[31] >> 4 & 1;
+       stat->ca_dvb_flag               = r->operand[31] >> 3 & 1;
+       stat->ca_error_flag             = r->operand[31] >> 2 & 1;
+       stat->ca_initialization_status  = r->operand[31] >> 1 & 1;
+
+       return 0;
+}
+
+int avc_lnb_control(struct firedtv *fdtv, char voltage, char burst,
+                   char conttone, char nrdiseq,
+                   struct dvb_diseqc_master_cmd *diseqcmd)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+       int i, j, k;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_LNB_CONTROL;
+
+       c->operand[4] = voltage;
+       c->operand[5] = nrdiseq;
+
+       i = 6;
+
+       for (j = 0; j < nrdiseq; j++) {
+               c->operand[i++] = diseqcmd[j].msg_len;
+
+               for (k = 0; k < diseqcmd[j].msg_len; k++)
+                       c->operand[i++] = diseqcmd[j].msg[k];
+       }
+
+       c->operand[i++] = burst;
+       c->operand[i++] = conttone;
+
+       c->length = ALIGN(3 + i, 4);
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       if (r->response != AVC_RESPONSE_ACCEPTED) {
+               dev_err(fdtv->device, "LNB control failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+int avc_register_remote_control(struct firedtv *fdtv)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_NOTIFY;
+       c->subunit = AVC_SUBUNIT_TYPE_UNIT | 7;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL;
+
+       c->length = 8;
+
+       return avc_write(fdtv, c, NULL);
+}
+
+void avc_remote_ctrl_work(struct work_struct *work)
+{
+       struct firedtv *fdtv =
+                       container_of(work, struct firedtv, remote_ctrl_work);
+
+       /* Should it be rescheduled in failure cases? */
+       avc_register_remote_control(fdtv);
+}
+
+#if 0 /* FIXME: unused */
+int avc_tuner_host2ca(struct firedtv *fdtv)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
+       c->operand[6] = 0; /* more/last */
+       c->operand[7] = 0; /* length */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       return 0;
+}
+#endif
+
+static int get_ca_object_pos(struct avc_response_frame *r)
+{
+       int length = 1;
+
+       /* Check length of length field */
+       if (r->operand[7] & 0x80)
+               length = (r->operand[7] & 0x7f) + 1;
+       return length + 7;
+}
+
+static int get_ca_object_length(struct avc_response_frame *r)
+{
+#if 0 /* FIXME: unused */
+       int size = 0;
+       int i;
+
+       if (r->operand[7] & 0x80)
+               for (i = 0; i < (r->operand[7] & 0x7f); i++) {
+                       size <<= 8;
+                       size += r->operand[8 + i];
+               }
+#endif
+       return r->operand[7];
+}
+
+int avc_ca_app_info(struct firedtv *fdtv, char *app_info, unsigned int *len)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+       int pos;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_STATUS;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       /* FIXME: check response code and validate response data */
+
+       pos = get_ca_object_pos(r);
+       app_info[0] = (EN50221_TAG_APP_INFO >> 16) & 0xff;
+       app_info[1] = (EN50221_TAG_APP_INFO >>  8) & 0xff;
+       app_info[2] = (EN50221_TAG_APP_INFO >>  0) & 0xff;
+       app_info[3] = 6 + r->operand[pos + 4];
+       app_info[4] = 0x01;
+       memcpy(&app_info[5], &r->operand[pos], 5 + r->operand[pos + 4]);
+       *len = app_info[3] + 4;
+
+       return 0;
+}
+
+int avc_ca_info(struct firedtv *fdtv, char *app_info, unsigned int *len)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+       int pos;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_STATUS;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       pos = get_ca_object_pos(r);
+       app_info[0] = (EN50221_TAG_CA_INFO >> 16) & 0xff;
+       app_info[1] = (EN50221_TAG_CA_INFO >>  8) & 0xff;
+       app_info[2] = (EN50221_TAG_CA_INFO >>  0) & 0xff;
+       app_info[3] = 2;
+       app_info[4] = r->operand[pos + 0];
+       app_info[5] = r->operand[pos + 1];
+       *len = app_info[3] + 4;
+
+       return 0;
+}
+
+int avc_ca_reset(struct firedtv *fdtv)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_RESET; /* ca tag */
+       c->operand[6] = 0; /* more/last */
+       c->operand[7] = 1; /* length */
+       c->operand[8] = 0; /* force hardware reset */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       return 0;
+}
+
+int avc_ca_pmt(struct firedtv *fdtv, char *msg, int length)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+       int list_management;
+       int program_info_length;
+       int pmt_cmd_id;
+       int read_pos;
+       int write_pos;
+       int es_info_length;
+       int crc32_csum;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_CONTROL;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       if (msg[0] != EN50221_LIST_MANAGEMENT_ONLY) {
+               dev_info(fdtv->device, "forcing list_management to ONLY\n");
+               msg[0] = EN50221_LIST_MANAGEMENT_ONLY;
+       }
+       /* We take the cmd_id from the programme level only! */
+       list_management = msg[0];
+       program_info_length = ((msg[4] & 0x0f) << 8) + msg[5];
+       if (program_info_length > 0)
+               program_info_length--; /* Remove pmt_cmd_id */
+       pmt_cmd_id = msg[6];
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_PMT; /* ca tag */
+       c->operand[6] = 0; /* more/last */
+       /* c->operand[7] = XXXprogram_info_length + 17; */ /* length */
+       c->operand[8] = list_management;
+       c->operand[9] = 0x01; /* pmt_cmd=OK_descramble */
+
+       /* TS program map table */
+
+       c->operand[10] = 0x02; /* Table id=2 */
+       c->operand[11] = 0x80; /* Section syntax + length */
+       /* c->operand[12] = XXXprogram_info_length + 12; */
+       c->operand[13] = msg[1]; /* Program number */
+       c->operand[14] = msg[2];
+       c->operand[15] = 0x01; /* Version number=0 + current/next=1 */
+       c->operand[16] = 0x00; /* Section number=0 */
+       c->operand[17] = 0x00; /* Last section number=0 */
+       c->operand[18] = 0x1f; /* PCR_PID=1FFF */
+       c->operand[19] = 0xff;
+       c->operand[20] = (program_info_length >> 8); /* Program info length */
+       c->operand[21] = (program_info_length & 0xff);
+
+       /* CA descriptors at programme level */
+       read_pos = 6;
+       write_pos = 22;
+       if (program_info_length > 0) {
+               pmt_cmd_id = msg[read_pos++];
+               if (pmt_cmd_id != 1 && pmt_cmd_id != 4)
+                       dev_err(fdtv->device,
+                               "invalid pmt_cmd_id %d\n", pmt_cmd_id);
+
+               memcpy(&c->operand[write_pos], &msg[read_pos],
+                      program_info_length);
+               read_pos += program_info_length;
+               write_pos += program_info_length;
+       }
+       while (read_pos < length) {
+               c->operand[write_pos++] = msg[read_pos++];
+               c->operand[write_pos++] = msg[read_pos++];
+               c->operand[write_pos++] = msg[read_pos++];
+               es_info_length =
+                       ((msg[read_pos] & 0x0f) << 8) + msg[read_pos + 1];
+               read_pos += 2;
+               if (es_info_length > 0)
+                       es_info_length--; /* Remove pmt_cmd_id */
+               c->operand[write_pos++] = es_info_length >> 8;
+               c->operand[write_pos++] = es_info_length & 0xff;
+               if (es_info_length > 0) {
+                       pmt_cmd_id = msg[read_pos++];
+                       if (pmt_cmd_id != 1 && pmt_cmd_id != 4)
+                               dev_err(fdtv->device, "invalid pmt_cmd_id %d "
+                                       "at stream level\n", pmt_cmd_id);
+
+                       memcpy(&c->operand[write_pos], &msg[read_pos],
+                              es_info_length);
+                       read_pos += es_info_length;
+                       write_pos += es_info_length;
+               }
+       }
+
+       /* CRC */
+       c->operand[write_pos++] = 0x00;
+       c->operand[write_pos++] = 0x00;
+       c->operand[write_pos++] = 0x00;
+       c->operand[write_pos++] = 0x00;
+
+       c->operand[7] = write_pos - 8;
+       c->operand[12] = write_pos - 13;
+
+       crc32_csum = crc32_be(0, &c->operand[10], c->operand[12] - 1);
+       c->operand[write_pos - 4] = (crc32_csum >> 24) & 0xff;
+       c->operand[write_pos - 3] = (crc32_csum >> 16) & 0xff;
+       c->operand[write_pos - 2] = (crc32_csum >>  8) & 0xff;
+       c->operand[write_pos - 1] = (crc32_csum >>  0) & 0xff;
+
+       c->length = ALIGN(3 + write_pos, 4);
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       if (r->response != AVC_RESPONSE_ACCEPTED) {
+               dev_err(fdtv->device,
+                       "CA PMT failed with response 0x%x\n", r->response);
+               return -EFAULT;
+       }
+
+       return 0;
+}
+
+int avc_ca_get_time_date(struct firedtv *fdtv, int *interval)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_STATUS;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_DATE_TIME; /* ca tag */
+       c->operand[6] = 0; /* more/last */
+       c->operand[7] = 0; /* length */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       /* FIXME: check response code and validate response data */
+
+       *interval = r->operand[get_ca_object_pos(r)];
+
+       return 0;
+}
+
+int avc_ca_enter_menu(struct firedtv *fdtv)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_STATUS;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_ENTER_MENU;
+       c->operand[6] = 0; /* more/last */
+       c->operand[7] = 0; /* length */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       return 0;
+}
+
+int avc_ca_get_mmi(struct firedtv *fdtv, char *mmi_object, unsigned int *len)
+{
+       char buffer[sizeof(struct avc_command_frame)];
+       struct avc_command_frame *c = (void *)buffer;
+       struct avc_response_frame *r = (void *)buffer;
+
+       memset(c, 0, sizeof(*c));
+
+       c->ctype   = AVC_CTYPE_STATUS;
+       c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
+       c->opcode  = AVC_OPCODE_VENDOR;
+
+       c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
+       c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
+       c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
+       c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
+       c->operand[4] = 0; /* slot */
+       c->operand[5] = SFE_VENDOR_TAG_CA_MMI;
+       c->operand[6] = 0; /* more/last */
+       c->operand[7] = 0; /* length */
+
+       c->length = 12;
+
+       if (avc_write(fdtv, c, r) < 0)
+               return -EIO;
+
+       /* FIXME: check response code and validate response data */
+
+       *len = get_ca_object_length(r);
+       memcpy(mmi_object, &r->operand[get_ca_object_pos(r)], *len);
+
+       return 0;
+}
+
+#define CMP_OUTPUT_PLUG_CONTROL_REG_0  0xfffff0000904ULL
+
+static int cmp_read(struct firedtv *fdtv, void *buf, u64 addr, size_t len)
+{
+       int ret;
+
+       if (mutex_lock_interruptible(&fdtv->avc_mutex))
+               return -EINTR;
+
+       ret = fdtv->backend->read(fdtv, addr, buf, len);
+       if (ret < 0)
+               dev_err(fdtv->device, "CMP: read I/O error\n");
+
+       mutex_unlock(&fdtv->avc_mutex);
+       return ret;
+}
+
+static int cmp_lock(struct firedtv *fdtv, void *data, u64 addr, __be32 arg)
+{
+       int ret;
+
+       if (mutex_lock_interruptible(&fdtv->avc_mutex))
+               return -EINTR;
+
+       ret = fdtv->backend->lock(fdtv, addr, data, arg);
+       if (ret < 0)
+               dev_err(fdtv->device, "CMP: lock I/O error\n");
+
+       mutex_unlock(&fdtv->avc_mutex);
+       return ret;
+}
+
+static inline u32 get_opcr(__be32 opcr, u32 mask, u32 shift)
+{
+       return (be32_to_cpu(opcr) >> shift) & mask;
+}
+
+static inline void set_opcr(__be32 *opcr, u32 value, u32 mask, u32 shift)
+{
+       *opcr &= ~cpu_to_be32(mask << shift);
+       *opcr |= cpu_to_be32((value & mask) << shift);
+}
+
+#define get_opcr_online(v)             get_opcr((v), 0x1, 31)
+#define get_opcr_p2p_connections(v)    get_opcr((v), 0x3f, 24)
+#define get_opcr_channel(v)            get_opcr((v), 0x3f, 16)
+
+#define set_opcr_p2p_connections(p, v) set_opcr((p), (v), 0x3f, 24)
+#define set_opcr_channel(p, v)         set_opcr((p), (v), 0x3f, 16)
+#define set_opcr_data_rate(p, v)       set_opcr((p), (v), 0x3, 14)
+#define set_opcr_overhead_id(p, v)     set_opcr((p), (v), 0xf, 10)
+
+int cmp_establish_pp_connection(struct firedtv *fdtv, int plug, int channel)
+{
+       __be32 old_opcr, opcr;
+       u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
+       int attempts = 0;
+       int ret;
+
+       ret = cmp_read(fdtv, &opcr, opcr_address, 4);
+       if (ret < 0)
+               return ret;
+
+repeat:
+       if (!get_opcr_online(opcr)) {
+               dev_err(fdtv->device, "CMP: output offline\n");
+               return -EBUSY;
+       }
+
+       old_opcr = opcr;
+
+       if (get_opcr_p2p_connections(opcr)) {
+               if (get_opcr_channel(opcr) != channel) {
+                       dev_err(fdtv->device, "CMP: cannot change channel\n");
+                       return -EBUSY;
+               }
+               dev_info(fdtv->device, "CMP: overlaying connection\n");
+
+               /* We don't allocate isochronous resources. */
+       } else {
+               set_opcr_channel(&opcr, channel);
+               set_opcr_data_rate(&opcr, 2); /* S400 */
+
+               /* FIXME: this is for the worst case - optimize */
+               set_opcr_overhead_id(&opcr, 0);
+
+               /*
+                * FIXME: allocate isochronous channel and bandwidth at IRM
+                * fdtv->backend->alloc_resources(fdtv, channels_mask, bw);
+                */
+       }
+
+       set_opcr_p2p_connections(&opcr, get_opcr_p2p_connections(opcr) + 1);
+
+       ret = cmp_lock(fdtv, &opcr, opcr_address, old_opcr);
+       if (ret < 0)
+               return ret;
+
+       if (old_opcr != opcr) {
+               /*
+                * FIXME: if old_opcr.P2P_Connections > 0,
+                * deallocate isochronous channel and bandwidth at IRM
+                * if (...)
+                *      fdtv->backend->dealloc_resources(fdtv, channel, bw);
+                */
+
+               if (++attempts < 6) /* arbitrary limit */
+                       goto repeat;
+               return -EBUSY;
+       }
+
+       return 0;
+}
+
+void cmp_break_pp_connection(struct firedtv *fdtv, int plug, int channel)
+{
+       __be32 old_opcr, opcr;
+       u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
+       int attempts = 0;
+
+       if (cmp_read(fdtv, &opcr, opcr_address, 4) < 0)
+               return;
+
+repeat:
+       if (!get_opcr_online(opcr) || !get_opcr_p2p_connections(opcr) ||
+           get_opcr_channel(opcr) != channel) {
+               dev_err(fdtv->device, "CMP: no connection to break\n");
+               return;
+       }
+
+       old_opcr = opcr;
+       set_opcr_p2p_connections(&opcr, get_opcr_p2p_connections(opcr) - 1);
+
+       if (cmp_lock(fdtv, &opcr, opcr_address, old_opcr) < 0)
+               return;
+
+       if (old_opcr != opcr) {
+               /*
+                * FIXME: if old_opcr.P2P_Connections == 1, i.e. we were last
+                * owner, deallocate isochronous channel and bandwidth at IRM
+                * if (...)
+                *      fdtv->backend->dealloc_resources(fdtv, channel, bw);
+                */
+
+               if (++attempts < 6) /* arbitrary limit */
+                       goto repeat;
+       }
+}
diff --git a/drivers/media/dvb/firewire/firedtv-ci.c b/drivers/media/dvb/firewire/firedtv-ci.c
new file mode 100644 (file)
index 0000000..eeb80d0
--- /dev/null
@@ -0,0 +1,260 @@
+/*
+ * FireDTV driver (formerly known as FireSAT)
+ *
+ * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
+ * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/dvb/ca.h>
+#include <linux/fs.h>
+#include <linux/module.h>
+
+#include <dvbdev.h>
+
+#include "firedtv.h"
+
+#define EN50221_TAG_APP_INFO_ENQUIRY   0x9f8020
+#define EN50221_TAG_CA_INFO_ENQUIRY    0x9f8030
+#define EN50221_TAG_CA_PMT             0x9f8032
+#define EN50221_TAG_ENTER_MENU         0x9f8022
+
+static int fdtv_ca_ready(struct firedtv_tuner_status *stat)
+{
+       return stat->ca_initialization_status   == 1 &&
+              stat->ca_error_flag              == 0 &&
+              stat->ca_dvb_flag                == 1 &&
+              stat->ca_module_present_status   == 1;
+}
+
+static int fdtv_get_ca_flags(struct firedtv_tuner_status *stat)
+{
+       int flags = 0;
+
+       if (stat->ca_module_present_status == 1)
+               flags |= CA_CI_MODULE_PRESENT;
+       if (stat->ca_initialization_status == 1 &&
+           stat->ca_error_flag            == 0 &&
+           stat->ca_dvb_flag              == 1)
+               flags |= CA_CI_MODULE_READY;
+       return flags;
+}
+
+static int fdtv_ca_reset(struct firedtv *fdtv)
+{
+       return avc_ca_reset(fdtv) ? -EFAULT : 0;
+}
+
+static int fdtv_ca_get_caps(void *arg)
+{
+       struct ca_caps *cap = arg;
+
+       cap->slot_num = 1;
+       cap->slot_type = CA_CI;
+       cap->descr_num = 1;
+       cap->descr_type = CA_ECD;
+       return 0;
+}
+
+static int fdtv_ca_get_slot_info(struct firedtv *fdtv, void *arg)
+{
+       struct firedtv_tuner_status stat;
+       struct ca_slot_info *slot = arg;
+
+       if (avc_tuner_status(fdtv, &stat))
+               return -EFAULT;
+
+       if (slot->num != 0)
+               return -EFAULT;
+
+       slot->type = CA_CI;
+       slot->flags = fdtv_get_ca_flags(&stat);
+       return 0;
+}
+
+static int fdtv_ca_app_info(struct firedtv *fdtv, void *arg)
+{
+       struct ca_msg *reply = arg;
+
+       return avc_ca_app_info(fdtv, reply->msg, &reply->length) ? -EFAULT : 0;
+}
+
+static int fdtv_ca_info(struct firedtv *fdtv, void *arg)
+{
+       struct ca_msg *reply = arg;
+
+       return avc_ca_info(fdtv, reply->msg, &reply->length) ? -EFAULT : 0;
+}
+
+static int fdtv_ca_get_mmi(struct firedtv *fdtv, void *arg)
+{
+       struct ca_msg *reply = arg;
+
+       return avc_ca_get_mmi(fdtv, reply->msg, &reply->length) ? -EFAULT : 0;
+}
+
+static int fdtv_ca_get_msg(struct firedtv *fdtv, void *arg)
+{
+       struct firedtv_tuner_status stat;
+       int err;
+
+       switch (fdtv->ca_last_command) {
+       case EN50221_TAG_APP_INFO_ENQUIRY:
+               err = fdtv_ca_app_info(fdtv, arg);
+               break;
+       case EN50221_TAG_CA_INFO_ENQUIRY:
+               err = fdtv_ca_info(fdtv, arg);
+               break;
+       default:
+               if (avc_tuner_status(fdtv, &stat))
+                       err = -EFAULT;
+               else if (stat.ca_mmi == 1)
+                       err = fdtv_ca_get_mmi(fdtv, arg);
+               else {
+                       dev_info(fdtv->device, "unhandled CA message 0x%08x\n",
+                                fdtv->ca_last_command);
+                       err = -EFAULT;
+               }
+       }
+       fdtv->ca_last_command = 0;
+       return err;
+}
+
+static int fdtv_ca_pmt(struct firedtv *fdtv, void *arg)
+{
+       struct ca_msg *msg = arg;
+       int data_pos;
+       int data_length;
+       int i;
+
+       data_pos = 4;
+       if (msg->msg[3] & 0x80) {
+               data_length = 0;
+               for (i = 0; i < (msg->msg[3] & 0x7f); i++)
+                       data_length = (data_length << 8) + msg->msg[data_pos++];
+       } else {
+               data_length = msg->msg[3];
+       }
+
+       return avc_ca_pmt(fdtv, &msg->msg[data_pos], data_length) ? -EFAULT : 0;
+}
+
+static int fdtv_ca_send_msg(struct firedtv *fdtv, void *arg)
+{
+       struct ca_msg *msg = arg;
+       int err;
+
+       /* Do we need a semaphore for this? */
+       fdtv->ca_last_command =
+               (msg->msg[0] << 16) + (msg->msg[1] << 8) + msg->msg[2];
+       switch (fdtv->ca_last_command) {
+       case EN50221_TAG_CA_PMT:
+               err = fdtv_ca_pmt(fdtv, arg);
+               break;
+       case EN50221_TAG_APP_INFO_ENQUIRY:
+               /* handled in ca_get_msg */
+               err = 0;
+               break;
+       case EN50221_TAG_CA_INFO_ENQUIRY:
+               /* handled in ca_get_msg */
+               err = 0;
+               break;
+       case EN50221_TAG_ENTER_MENU:
+               err = avc_ca_enter_menu(fdtv);
+               break;
+       default:
+               dev_err(fdtv->device, "unhandled CA message 0x%08x\n",
+                       fdtv->ca_last_command);
+               err = -EFAULT;
+       }
+       return err;
+}
+
+static int fdtv_ca_ioctl(struct inode *inode, struct file *file,
+                           unsigned int cmd, void *arg)
+{
+       struct dvb_device *dvbdev = file->private_data;
+       struct firedtv *fdtv = dvbdev->priv;
+       struct firedtv_tuner_status stat;
+       int err;
+
+       switch (cmd) {
+       case CA_RESET:
+               err = fdtv_ca_reset(fdtv);
+               break;
+       case CA_GET_CAP:
+               err = fdtv_ca_get_caps(arg);
+               break;
+       case CA_GET_SLOT_INFO:
+               err = fdtv_ca_get_slot_info(fdtv, arg);
+               break;
+       case CA_GET_MSG:
+               err = fdtv_ca_get_msg(fdtv, arg);
+               break;
+       case CA_SEND_MSG:
+               err = fdtv_ca_send_msg(fdtv, arg);
+               break;
+       default:
+               dev_info(fdtv->device, "unhandled CA ioctl %u\n", cmd);
+               err = -EOPNOTSUPP;
+       }
+
+       /* FIXME Is this necessary? */
+       avc_tuner_status(fdtv, &stat);
+
+       return err;
+}
+
+static unsigned int fdtv_ca_io_poll(struct file *file, poll_table *wait)
+{
+       return POLLIN;
+}
+
+static struct file_operations fdtv_ca_fops = {
+       .owner          = THIS_MODULE,
+       .ioctl          = dvb_generic_ioctl,
+       .open           = dvb_generic_open,
+       .release        = dvb_generic_release,
+       .poll           = fdtv_ca_io_poll,
+};
+
+static struct dvb_device fdtv_ca = {
+       .users          = 1,
+       .readers        = 1,
+       .writers        = 1,
+       .fops           = &fdtv_ca_fops,
+       .kernel_ioctl   = fdtv_ca_ioctl,
+};
+
+int fdtv_ca_register(struct firedtv *fdtv)
+{
+       struct firedtv_tuner_status stat;
+       int err;
+
+       if (avc_tuner_status(fdtv, &stat))
+               return -EINVAL;
+
+       if (!fdtv_ca_ready(&stat))
+               return -EFAULT;
+
+       err = dvb_register_device(&fdtv->adapter, &fdtv->cadev,
+                                 &fdtv_ca, fdtv, DVB_DEVICE_CA);
+
+       if (stat.ca_application_info == 0)
+               dev_err(fdtv->device, "CaApplicationInfo is not set\n");
+       if (stat.ca_date_time_request == 1)
+               avc_ca_get_time_date(fdtv, &fdtv->ca_time_interval);
+
+       return err;
+}
+
+void fdtv_ca_release(struct firedtv *fdtv)
+{
+       if (fdtv->cadev)
+               dvb_unregister_device(fdtv->cadev);
+}
diff --git a/drivers/media/dvb/firewire/firedtv-dvb.c b/drivers/media/dvb/firewire/firedtv-dvb.c
new file mode 100644 (file)
index 0000000..9d308dd
--- /dev/null
@@ -0,0 +1,364 @@
+/*
+ * FireDTV driver (formerly known as FireSAT)
+ *
+ * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
+ * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#include <dmxdev.h>
+#include <dvb_demux.h>
+#include <dvbdev.h>
+#include <dvb_frontend.h>
+
+#include "firedtv.h"
+
+static int alloc_channel(struct firedtv *fdtv)
+{
+       int i;
+
+       for (i = 0; i < 16; i++)
+               if (!__test_and_set_bit(i, &fdtv->channel_active))
+                       break;
+       return i;
+}
+
+static void collect_channels(struct firedtv *fdtv, int *pidc, u16 pid[])
+{
+       int i, n;
+
+       for (i = 0, n = 0; i < 16; i++)
+               if (test_bit(i, &fdtv->channel_active))
+                       pid[n++] = fdtv->channel_pid[i];
+       *pidc = n;
+}
+
+static inline void dealloc_channel(struct firedtv *fdtv, int i)
+{
+       __clear_bit(i, &fdtv->channel_active);
+}
+
+int fdtv_start_feed(struct dvb_demux_feed *dvbdmxfeed)
+{
+       struct firedtv *fdtv = dvbdmxfeed->demux->priv;
+       int pidc, c, ret;
+       u16 pids[16];
+
+       switch (dvbdmxfeed->type) {
+       case DMX_TYPE_TS:
+       case DMX_TYPE_SEC:
+               break;
+       default:
+               dev_err(fdtv->device, "can't start dmx feed: invalid type %u\n",
+                       dvbdmxfeed->type);
+               return -EINVAL;
+       }
+
+       if (mutex_lock_interruptible(&fdtv->demux_mutex))
+               return -EINTR;
+
+       if (dvbdmxfeed->type == DMX_TYPE_TS) {
+               switch (dvbdmxfeed->pes_type) {
+               case DMX_TS_PES_VIDEO:
+               case DMX_TS_PES_AUDIO:
+               case DMX_TS_PES_TELETEXT:
+               case DMX_TS_PES_PCR:
+               case DMX_TS_PES_OTHER:
+                       c = alloc_channel(fdtv);
+                       break;
+               default:
+                       dev_err(fdtv->device,
+                               "can't start dmx feed: invalid pes type %u\n",
+                               dvbdmxfeed->pes_type);
+                       ret = -EINVAL;
+                       goto out;
+               }
+       } else {
+               c = alloc_channel(fdtv);
+       }
+
+       if (c > 15) {
+               dev_err(fdtv->device, "can't start dmx feed: busy\n");
+               ret = -EBUSY;
+               goto out;
+       }
+
+       dvbdmxfeed->priv = (typeof(dvbdmxfeed->priv))(unsigned long)c;
+       fdtv->channel_pid[c] = dvbdmxfeed->pid;
+       collect_channels(fdtv, &pidc, pids);
+
+       if (dvbdmxfeed->pid == 8192) {
+               ret = avc_tuner_get_ts(fdtv);
+               if (ret) {
+                       dealloc_channel(fdtv, c);
+                       dev_err(fdtv->device, "can't get TS\n");
+                       goto out;
+               }
+       } else {
+               ret = avc_tuner_set_pids(fdtv, pidc, pids);
+               if (ret) {
+                       dealloc_channel(fdtv, c);
+                       dev_err(fdtv->device, "can't set PIDs\n");
+                       goto out;
+               }
+       }
+out:
+       mutex_unlock(&fdtv->demux_mutex);
+
+       return ret;
+}
+
+int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
+{
+       struct dvb_demux *demux = dvbdmxfeed->demux;
+       struct firedtv *fdtv = demux->priv;
+       int pidc, c, ret;
+       u16 pids[16];
+
+       if (dvbdmxfeed->type == DMX_TYPE_TS &&
+           !((dvbdmxfeed->ts_type & TS_PACKET) &&
+             (demux->dmx.frontend->source != DMX_MEMORY_FE))) {
+
+               if (dvbdmxfeed->ts_type & TS_DECODER) {
+                       if (dvbdmxfeed->pes_type >= DMX_TS_PES_OTHER ||
+                           !demux->pesfilter[dvbdmxfeed->pes_type])
+                               return -EINVAL;
+
+                       demux->pids[dvbdmxfeed->pes_type] |= 0x8000;
+                       demux->pesfilter[dvbdmxfeed->pes_type] = NULL;
+               }
+
+               if (!(dvbdmxfeed->ts_type & TS_DECODER &&
+                     dvbdmxfeed->pes_type < DMX_TS_PES_OTHER))
+                       return 0;
+       }
+
+       if (mutex_lock_interruptible(&fdtv->demux_mutex))
+               return -EINTR;
+
+       c = (unsigned long)dvbdmxfeed->priv;
+       dealloc_channel(fdtv, c);
+       collect_channels(fdtv, &pidc, pids);
+
+       ret = avc_tuner_set_pids(fdtv, pidc, pids);
+
+       mutex_unlock(&fdtv->demux_mutex);
+
+       return ret;
+}
+
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+
+int fdtv_dvb_register(struct firedtv *fdtv)
+{
+       int err;
+
+       err = dvb_register_adapter(&fdtv->adapter, fdtv_model_names[fdtv->type],
+                                  THIS_MODULE, fdtv->device, adapter_nr);
+       if (err < 0)
+               goto fail_log;
+
+       /*DMX_TS_FILTERING | DMX_SECTION_FILTERING*/
+       fdtv->demux.dmx.capabilities = 0;
+
+       fdtv->demux.priv        = fdtv;
+       fdtv->demux.filternum   = 16;
+       fdtv->demux.feednum     = 16;
+       fdtv->demux.start_feed  = fdtv_start_feed;
+       fdtv->demux.stop_feed   = fdtv_stop_feed;
+       fdtv->demux.write_to_decoder = NULL;
+
+       err = dvb_dmx_init(&fdtv->demux);
+       if (err)
+               goto fail_unreg_adapter;
+
+       fdtv->dmxdev.filternum    = 16;
+       fdtv->dmxdev.demux        = &fdtv->demux.dmx;
+       fdtv->dmxdev.capabilities = 0;
+
+       err = dvb_dmxdev_init(&fdtv->dmxdev, &fdtv->adapter);
+       if (err)
+               goto fail_dmx_release;
+
+       fdtv->frontend.source = DMX_FRONTEND_0;
+
+       err = fdtv->demux.dmx.add_frontend(&fdtv->demux.dmx, &fdtv->frontend);
+       if (err)
+               goto fail_dmxdev_release;
+
+       err = fdtv->demux.dmx.connect_frontend(&fdtv->demux.dmx,
+                                              &fdtv->frontend);
+       if (err)
+               goto fail_rem_frontend;
+
+       dvb_net_init(&fdtv->adapter, &fdtv->dvbnet, &fdtv->demux.dmx);
+
+       fdtv_frontend_init(fdtv);
+       err = dvb_register_frontend(&fdtv->adapter, &fdtv->fe);
+       if (err)
+               goto fail_net_release;
+
+       err = fdtv_ca_register(fdtv);
+       if (err)
+               dev_info(fdtv->device,
+                        "Conditional Access Module not enabled\n");
+       return 0;
+
+fail_net_release:
+       dvb_net_release(&fdtv->dvbnet);
+       fdtv->demux.dmx.close(&fdtv->demux.dmx);
+fail_rem_frontend:
+       fdtv->demux.dmx.remove_frontend(&fdtv->demux.dmx, &fdtv->frontend);
+fail_dmxdev_release:
+       dvb_dmxdev_release(&fdtv->dmxdev);
+fail_dmx_release:
+       dvb_dmx_release(&fdtv->demux);
+fail_unreg_adapter:
+       dvb_unregister_adapter(&fdtv->adapter);
+fail_log:
+       dev_err(fdtv->device, "DVB initialization failed\n");
+       return err;
+}
+
+void fdtv_dvb_unregister(struct firedtv *fdtv)
+{
+       fdtv_ca_release(fdtv);
+       dvb_unregister_frontend(&fdtv->fe);
+       dvb_net_release(&fdtv->dvbnet);
+       fdtv->demux.dmx.close(&fdtv->demux.dmx);
+       fdtv->demux.dmx.remove_frontend(&fdtv->demux.dmx, &fdtv->frontend);
+       dvb_dmxdev_release(&fdtv->dmxdev);
+       dvb_dmx_release(&fdtv->demux);
+       dvb_unregister_adapter(&fdtv->adapter);
+}
+
+const char *fdtv_model_names[] = {
+       [FIREDTV_UNKNOWN] = "unknown type",
+       [FIREDTV_DVB_S]   = "FireDTV S/CI",
+       [FIREDTV_DVB_C]   = "FireDTV C/CI",
+       [FIREDTV_DVB_T]   = "FireDTV T/CI",
+       [FIREDTV_DVB_S2]  = "FireDTV S2  ",
+};
+
+struct firedtv *fdtv_alloc(struct device *dev,
+                          const struct firedtv_backend *backend,
+                          const char *name, size_t name_len)
+{
+       struct firedtv *fdtv;
+       int i;
+
+       fdtv = kzalloc(sizeof(*fdtv), GFP_KERNEL);
+       if (!fdtv)
+               return NULL;
+
+       dev->driver_data        = fdtv;
+       fdtv->device            = dev;
+       fdtv->isochannel        = -1;
+       fdtv->voltage           = 0xff;
+       fdtv->tone              = 0xff;
+       fdtv->backend           = backend;
+
+       mutex_init(&fdtv->avc_mutex);
+       init_waitqueue_head(&fdtv->avc_wait);
+       fdtv->avc_reply_received = true;
+       mutex_init(&fdtv->demux_mutex);
+       INIT_WORK(&fdtv->remote_ctrl_work, avc_remote_ctrl_work);
+
+       for (i = ARRAY_SIZE(fdtv_model_names); --i; )
+               if (strlen(fdtv_model_names[i]) <= name_len &&
+                   strncmp(name, fdtv_model_names[i], name_len) == 0)
+                       break;
+       fdtv->type = i;
+
+       return fdtv;
+}
+
+#define MATCH_FLAGS (IEEE1394_MATCH_VENDOR_ID | IEEE1394_MATCH_MODEL_ID | \
+                    IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION)
+
+#define DIGITAL_EVERYWHERE_OUI 0x001287
+#define AVC_UNIT_SPEC_ID_ENTRY 0x00a02d
+#define AVC_SW_VERSION_ENTRY   0x010001
+
+static struct ieee1394_device_id fdtv_id_table[] = {
+       {
+               /* FloppyDTV S/CI and FloppyDTV S2 */
+               .match_flags    = MATCH_FLAGS,
+               .vendor_id      = DIGITAL_EVERYWHERE_OUI,
+               .model_id       = 0x000024,
+               .specifier_id   = AVC_UNIT_SPEC_ID_ENTRY,
+               .version        = AVC_SW_VERSION_ENTRY,
+       }, {
+               /* FloppyDTV T/CI */
+               .match_flags    = MATCH_FLAGS,
+               .vendor_id      = DIGITAL_EVERYWHERE_OUI,
+               .model_id       = 0x000025,
+               .specifier_id   = AVC_UNIT_SPEC_ID_ENTRY,
+               .version        = AVC_SW_VERSION_ENTRY,
+       }, {
+               /* FloppyDTV C/CI */
+               .match_flags    = MATCH_FLAGS,
+               .vendor_id      = DIGITAL_EVERYWHERE_OUI,
+               .model_id       = 0x000026,
+               .specifier_id   = AVC_UNIT_SPEC_ID_ENTRY,
+               .version        = AVC_SW_VERSION_ENTRY,
+       }, {
+               /* FireDTV S/CI and FloppyDTV S2 */
+               .match_flags    = MATCH_FLAGS,
+               .vendor_id      = DIGITAL_EVERYWHERE_OUI,
+               .model_id       = 0x000034,
+               .specifier_id   = AVC_UNIT_SPEC_ID_ENTRY,
+               .version        = AVC_SW_VERSION_ENTRY,
+       }, {
+               /* FireDTV T/CI */
+               .match_flags    = MATCH_FLAGS,
+               .vendor_id      = DIGITAL_EVERYWHERE_OUI,
+               .model_id       = 0x000035,
+               .specifier_id   = AVC_UNIT_SPEC_ID_ENTRY,
+               .version        = AVC_SW_VERSION_ENTRY,
+       }, {
+               /* FireDTV C/CI */
+               .match_flags    = MATCH_FLAGS,
+               .vendor_id      = DIGITAL_EVERYWHERE_OUI,
+               .model_id       = 0x000036,
+               .specifier_id   = AVC_UNIT_SPEC_ID_ENTRY,
+               .version        = AVC_SW_VERSION_ENTRY,
+       }, {}
+};
+MODULE_DEVICE_TABLE(ieee1394, fdtv_id_table);
+
+static int __init fdtv_init(void)
+{
+       return fdtv_1394_init(fdtv_id_table);
+}
+
+static void __exit fdtv_exit(void)
+{
+       fdtv_1394_exit();
+}
+
+module_init(fdtv_init);
+module_exit(fdtv_exit);
+
+MODULE_AUTHOR("Andreas Monitzer <andy@monitzer.com>");
+MODULE_AUTHOR("Ben Backx <ben@bbackx.com>");
+MODULE_DESCRIPTION("FireDTV DVB Driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("FireDTV DVB");
diff --git a/drivers/media/dvb/firewire/firedtv-fe.c b/drivers/media/dvb/firewire/firedtv-fe.c
new file mode 100644 (file)
index 0000000..7ba4363
--- /dev/null
@@ -0,0 +1,247 @@
+/*
+ * FireDTV driver (formerly known as FireSAT)
+ *
+ * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
+ * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include <dvb_frontend.h>
+
+#include "firedtv.h"
+
+static int fdtv_dvb_init(struct dvb_frontend *fe)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+       int err;
+
+       /* FIXME - allocate free channel at IRM */
+       fdtv->isochannel = fdtv->adapter.num;
+
+       err = cmp_establish_pp_connection(fdtv, fdtv->subunit,
+                                         fdtv->isochannel);
+       if (err) {
+               dev_err(fdtv->device,
+                       "could not establish point to point connection\n");
+               return err;
+       }
+
+       return fdtv->backend->start_iso(fdtv);
+}
+
+static int fdtv_sleep(struct dvb_frontend *fe)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+
+       fdtv->backend->stop_iso(fdtv);
+       cmp_break_pp_connection(fdtv, fdtv->subunit, fdtv->isochannel);
+       fdtv->isochannel = -1;
+       return 0;
+}
+
+#define LNBCONTROL_DONTCARE 0xff
+
+static int fdtv_diseqc_send_master_cmd(struct dvb_frontend *fe,
+                                      struct dvb_diseqc_master_cmd *cmd)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+
+       return avc_lnb_control(fdtv, LNBCONTROL_DONTCARE, LNBCONTROL_DONTCARE,
+                              LNBCONTROL_DONTCARE, 1, cmd);
+}
+
+static int fdtv_diseqc_send_burst(struct dvb_frontend *fe,
+                                 fe_sec_mini_cmd_t minicmd)
+{
+       return 0;
+}
+
+static int fdtv_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+
+       fdtv->tone = tone;
+       return 0;
+}
+
+static int fdtv_set_voltage(struct dvb_frontend *fe,
+                           fe_sec_voltage_t voltage)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+
+       fdtv->voltage = voltage;
+       return 0;
+}
+
+static int fdtv_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+       struct firedtv_tuner_status stat;
+
+       if (avc_tuner_status(fdtv, &stat))
+               return -EINVAL;
+
+       if (stat.no_rf)
+               *status = 0;
+       else
+               *status = FE_HAS_SIGNAL | FE_HAS_VITERBI | FE_HAS_SYNC |
+                         FE_HAS_CARRIER | FE_HAS_LOCK;
+       return 0;
+}
+
+static int fdtv_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+       struct firedtv_tuner_status stat;
+
+       if (avc_tuner_status(fdtv, &stat))
+               return -EINVAL;
+
+       *ber = stat.ber;
+       return 0;
+}
+
+static int fdtv_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+       struct firedtv_tuner_status stat;
+
+       if (avc_tuner_status(fdtv, &stat))
+               return -EINVAL;
+
+       *strength = stat.signal_strength << 8;
+       return 0;
+}
+
+static int fdtv_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+       struct firedtv_tuner_status stat;
+
+       if (avc_tuner_status(fdtv, &stat))
+               return -EINVAL;
+
+       /* C/N[dB] = -10 * log10(snr / 65535) */
+       *snr = stat.carrier_noise_ratio * 257;
+       return 0;
+}
+
+static int fdtv_read_uncorrected_blocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+       return -EOPNOTSUPP;
+}
+
+#define ACCEPTED 0x9
+
+static int fdtv_set_frontend(struct dvb_frontend *fe,
+                            struct dvb_frontend_parameters *params)
+{
+       struct firedtv *fdtv = fe->sec_priv;
+
+       /* FIXME: avc_tuner_dsd never returns ACCEPTED. Check status? */
+       if (avc_tuner_dsd(fdtv, params) != ACCEPTED)
+               return -EINVAL;
+       else
+               return 0; /* not sure of this... */
+}
+
+static int fdtv_get_frontend(struct dvb_frontend *fe,
+                            struct dvb_frontend_parameters *params)
+{
+       return -EOPNOTSUPP;
+}
+
+void fdtv_frontend_init(struct firedtv *fdtv)
+{
+       struct dvb_frontend_ops *ops = &fdtv->fe.ops;
+       struct dvb_frontend_info *fi = &ops->info;
+
+       ops->init                       = fdtv_dvb_init;
+       ops->sleep                      = fdtv_sleep;
+
+       ops->set_frontend               = fdtv_set_frontend;
+       ops->get_frontend               = fdtv_get_frontend;
+
+       ops->read_status                = fdtv_read_status;
+       ops->read_ber                   = fdtv_read_ber;
+       ops->read_signal_strength       = fdtv_read_signal_strength;
+       ops->read_snr                   = fdtv_read_snr;
+       ops->read_ucblocks              = fdtv_read_uncorrected_blocks;
+
+       ops->diseqc_send_master_cmd     = fdtv_diseqc_send_master_cmd;
+       ops->diseqc_send_burst          = fdtv_diseqc_send_burst;
+       ops->set_tone                   = fdtv_set_tone;
+       ops->set_voltage                = fdtv_set_voltage;
+
+       switch (fdtv->type) {
+       case FIREDTV_DVB_S:
+       case FIREDTV_DVB_S2:
+               fi->type                = FE_QPSK;
+
+               fi->frequency_min       = 950000;
+               fi->frequency_max       = 2150000;
+               fi->frequency_stepsize  = 125;
+               fi->symbol_rate_min     = 1000000;
+               fi->symbol_rate_max     = 40000000;
+
+               fi->caps                = FE_CAN_INVERSION_AUTO |
+                                         FE_CAN_FEC_1_2        |
+                                         FE_CAN_FEC_2_3        |
+                                         FE_CAN_FEC_3_4        |
+                                         FE_CAN_FEC_5_6        |
+                                         FE_CAN_FEC_7_8        |
+                                         FE_CAN_FEC_AUTO       |
+                                         FE_CAN_QPSK;
+               break;
+
+       case FIREDTV_DVB_C:
+               fi->type                = FE_QAM;
+
+               fi->frequency_min       = 47000000;
+               fi->frequency_max       = 866000000;
+               fi->frequency_stepsize  = 62500;
+               fi->symbol_rate_min     = 870000;
+               fi->symbol_rate_max     = 6900000;
+
+               fi->caps                = FE_CAN_INVERSION_AUTO |
+                                         FE_CAN_QAM_16         |
+                                         FE_CAN_QAM_32         |
+                                         FE_CAN_QAM_64         |
+                                         FE_CAN_QAM_128        |
+                                         FE_CAN_QAM_256        |
+                                         FE_CAN_QAM_AUTO;
+               break;
+
+       case FIREDTV_DVB_T:
+               fi->type                = FE_OFDM;
+
+               fi->frequency_min       = 49000000;
+               fi->frequency_max       = 861000000;
+               fi->frequency_stepsize  = 62500;
+
+               fi->caps                = FE_CAN_INVERSION_AUTO         |
+                                         FE_CAN_FEC_2_3                |
+                                         FE_CAN_TRANSMISSION_MODE_AUTO |
+                                         FE_CAN_GUARD_INTERVAL_AUTO    |
+                                         FE_CAN_HIERARCHY_AUTO;
+               break;
+
+       default:
+               dev_err(fdtv->device, "no frontend for model type %d\n",
+                       fdtv->type);
+       }
+       strcpy(fi->name, fdtv_model_names[fdtv->type]);
+
+       fdtv->fe.dvb = &fdtv->adapter;
+       fdtv->fe.sec_priv = fdtv;
+}
diff --git a/drivers/media/dvb/firewire/firedtv-rc.c b/drivers/media/dvb/firewire/firedtv-rc.c
new file mode 100644 (file)
index 0000000..46a6324
--- /dev/null
@@ -0,0 +1,190 @@
+/*
+ * FireDTV driver (formerly known as FireSAT)
+ *
+ * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/input.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "firedtv.h"
+
+/* fixed table with older keycodes, geared towards MythTV */
+const static u16 oldtable[] = {
+
+       /* code from device: 0x4501...0x451f */
+
+       KEY_ESC,
+       KEY_F9,
+       KEY_1,
+       KEY_2,
+       KEY_3,
+       KEY_4,
+       KEY_5,
+       KEY_6,
+       KEY_7,
+       KEY_8,
+       KEY_9,
+       KEY_I,
+       KEY_0,
+       KEY_ENTER,
+       KEY_RED,
+       KEY_UP,
+       KEY_GREEN,
+       KEY_F10,
+       KEY_SPACE,
+       KEY_F11,
+       KEY_YELLOW,
+       KEY_DOWN,
+       KEY_BLUE,
+       KEY_Z,
+       KEY_P,
+       KEY_PAGEDOWN,
+       KEY_LEFT,
+       KEY_W,
+       KEY_RIGHT,
+       KEY_P,
+       KEY_M,
+
+       /* code from device: 0x4540...0x4542 */
+
+       KEY_R,
+       KEY_V,
+       KEY_C,
+};
+
+/* user-modifiable table for a remote as sold in 2008 */
+const static u16 keytable[] = {
+
+       /* code from device: 0x0300...0x031f */
+
+       [0x00] = KEY_POWER,
+       [0x01] = KEY_SLEEP,
+       [0x02] = KEY_STOP,
+       [0x03] = KEY_OK,
+       [0x04] = KEY_RIGHT,
+       [0x05] = KEY_1,
+       [0x06] = KEY_2,
+       [0x07] = KEY_3,
+       [0x08] = KEY_LEFT,
+       [0x09] = KEY_4,
+       [0x0a] = KEY_5,
+       [0x0b] = KEY_6,
+       [0x0c] = KEY_UP,
+       [0x0d] = KEY_7,
+       [0x0e] = KEY_8,
+       [0x0f] = KEY_9,
+       [0x10] = KEY_DOWN,
+       [0x11] = KEY_TITLE,     /* "OSD" - fixme */
+       [0x12] = KEY_0,
+       [0x13] = KEY_F20,       /* "16:9" - fixme */
+       [0x14] = KEY_SCREEN,    /* "FULL" - fixme */
+       [0x15] = KEY_MUTE,
+       [0x16] = KEY_SUBTITLE,
+       [0x17] = KEY_RECORD,
+       [0x18] = KEY_TEXT,
+       [0x19] = KEY_AUDIO,
+       [0x1a] = KEY_RED,
+       [0x1b] = KEY_PREVIOUS,
+       [0x1c] = KEY_REWIND,
+       [0x1d] = KEY_PLAYPAUSE,
+       [0x1e] = KEY_NEXT,
+       [0x1f] = KEY_VOLUMEUP,
+
+       /* code from device: 0x0340...0x0354 */
+
+       [0x20] = KEY_CHANNELUP,
+       [0x21] = KEY_F21,       /* "4:3" - fixme */
+       [0x22] = KEY_TV,
+       [0x23] = KEY_DVD,
+       [0x24] = KEY_VCR,
+       [0x25] = KEY_AUX,
+       [0x26] = KEY_GREEN,
+       [0x27] = KEY_YELLOW,
+       [0x28] = KEY_BLUE,
+       [0x29] = KEY_CHANNEL,   /* "CH.LIST" */
+       [0x2a] = KEY_VENDOR,    /* "CI" - fixme */
+       [0x2b] = KEY_VOLUMEDOWN,
+       [0x2c] = KEY_CHANNELDOWN,
+       [0x2d] = KEY_LAST,
+       [0x2e] = KEY_INFO,
+       [0x2f] = KEY_FORWARD,
+       [0x30] = KEY_LIST,
+       [0x31] = KEY_FAVORITES,
+       [0x32] = KEY_MENU,
+       [0x33] = KEY_EPG,
+       [0x34] = KEY_EXIT,
+};
+
+int fdtv_register_rc(struct firedtv *fdtv, struct device *dev)
+{
+       struct input_dev *idev;
+       int i, err;
+
+       idev = input_allocate_device();
+       if (!idev)
+               return -ENOMEM;
+
+       fdtv->remote_ctrl_dev = idev;
+       idev->name = "FireDTV remote control";
+       idev->dev.parent = dev;
+       idev->evbit[0] = BIT_MASK(EV_KEY);
+       idev->keycode = kmemdup(keytable, sizeof(keytable), GFP_KERNEL);
+       if (!idev->keycode) {
+               err = -ENOMEM;
+               goto fail;
+       }
+       idev->keycodesize = sizeof(keytable[0]);
+       idev->keycodemax = ARRAY_SIZE(keytable);
+
+       for (i = 0; i < ARRAY_SIZE(keytable); i++)
+               set_bit(keytable[i], idev->keybit);
+
+       err = input_register_device(idev);
+       if (err)
+               goto fail_free_keymap;
+
+       return 0;
+
+fail_free_keymap:
+       kfree(idev->keycode);
+fail:
+       input_free_device(idev);
+       return err;
+}
+
+void fdtv_unregister_rc(struct firedtv *fdtv)
+{
+       kfree(fdtv->remote_ctrl_dev->keycode);
+       input_unregister_device(fdtv->remote_ctrl_dev);
+}
+
+void fdtv_handle_rc(struct firedtv *fdtv, unsigned int code)
+{
+       u16 *keycode = fdtv->remote_ctrl_dev->keycode;
+
+       if (code >= 0x0300 && code <= 0x031f)
+               code = keycode[code - 0x0300];
+       else if (code >= 0x0340 && code <= 0x0354)
+               code = keycode[code - 0x0320];
+       else if (code >= 0x4501 && code <= 0x451f)
+               code = oldtable[code - 0x4501];
+       else if (code >= 0x4540 && code <= 0x4542)
+               code = oldtable[code - 0x4521];
+       else {
+               printk(KERN_DEBUG "firedtv: invalid key code 0x%04x "
+                      "from remote control\n", code);
+               return;
+       }
+
+       input_report_key(fdtv->remote_ctrl_dev, code, 1);
+       input_report_key(fdtv->remote_ctrl_dev, code, 0);
+}
diff --git a/drivers/media/dvb/firewire/firedtv.h b/drivers/media/dvb/firewire/firedtv.h
new file mode 100644 (file)
index 0000000..d48530b
--- /dev/null
@@ -0,0 +1,182 @@
+/*
+ * FireDTV driver (formerly known as FireSAT)
+ *
+ * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
+ * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
+ *
+ *     This program is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ */
+
+#ifndef _FIREDTV_H
+#define _FIREDTV_H
+
+#include <linux/dvb/dmx.h>
+#include <linux/dvb/frontend.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock_types.h>
+#include <linux/types.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+
+#include <demux.h>
+#include <dmxdev.h>
+#include <dvb_demux.h>
+#include <dvb_frontend.h>
+#include <dvb_net.h>
+#include <dvbdev.h>
+
+struct firedtv_tuner_status {
+       unsigned active_system:8;
+       unsigned searching:1;
+       unsigned moving:1;
+       unsigned no_rf:1;
+       unsigned input:1;
+       unsigned selected_antenna:7;
+       unsigned ber:32;
+       unsigned signal_strength:8;
+       unsigned raster_frequency:2;
+       unsigned rf_frequency:22;
+       unsigned man_dep_info_length:8;
+       unsigned front_end_error:1;
+       unsigned antenna_error:1;
+       unsigned front_end_power_status:1;
+       unsigned power_supply:1;
+       unsigned carrier_noise_ratio:16;
+       unsigned power_supply_voltage:8;
+       unsigned antenna_voltage:8;
+       unsigned firewire_bus_voltage:8;
+       unsigned ca_mmi:1;
+       unsigned ca_pmt_reply:1;
+       unsigned ca_date_time_request:1;
+       unsigned ca_application_info:1;
+       unsigned ca_module_present_status:1;
+       unsigned ca_dvb_flag:1;
+       unsigned ca_error_flag:1;
+       unsigned ca_initialization_status:1;
+};
+
+enum model_type {
+       FIREDTV_UNKNOWN = 0,
+       FIREDTV_DVB_S   = 1,
+       FIREDTV_DVB_C   = 2,
+       FIREDTV_DVB_T   = 3,
+       FIREDTV_DVB_S2  = 4,
+};
+
+struct device;
+struct input_dev;
+struct firedtv;
+
+struct firedtv_backend {
+       int (*lock)(struct firedtv *fdtv, u64 addr, void *data, __be32 arg);
+       int (*read)(struct firedtv *fdtv, u64 addr, void *data, size_t len);
+       int (*write)(struct firedtv *fdtv, u64 addr, void *data, size_t len);
+       int (*start_iso)(struct firedtv *fdtv);
+       void (*stop_iso)(struct firedtv *fdtv);
+};
+
+struct firedtv {
+       struct device *device;
+       struct list_head list;
+
+       struct dvb_adapter      adapter;
+       struct dmxdev           dmxdev;
+       struct dvb_demux        demux;
+       struct dmx_frontend     frontend;
+       struct dvb_net          dvbnet;
+       struct dvb_frontend     fe;
+
+       struct dvb_device       *cadev;
+       int                     ca_last_command;
+       int                     ca_time_interval;
+
+       struct mutex            avc_mutex;
+       wait_queue_head_t       avc_wait;
+       bool                    avc_reply_received;
+       struct work_struct      remote_ctrl_work;
+       struct input_dev        *remote_ctrl_dev;
+
+       enum model_type         type;
+       char                    subunit;
+       char                    isochannel;
+       fe_sec_voltage_t        voltage;
+       fe_sec_tone_mode_t      tone;
+
+       const struct firedtv_backend *backend;
+       void                    *backend_data;
+
+       struct mutex            demux_mutex;
+       unsigned long           channel_active;
+       u16                     channel_pid[16];
+
+       size_t                  response_length;
+       u8                      response[512];
+};
+
+/* firedtv-1394.c */
+#ifdef CONFIG_DVB_FIREDTV_IEEE1394
+int fdtv_1394_init(struct ieee1394_device_id id_table[]);
+void fdtv_1394_exit(void);
+#else
+static inline int fdtv_1394_init(struct ieee1394_device_id it[]) { return 0; }
+static inline void fdtv_1394_exit(void) {}
+#endif
+
+/* firedtv-avc.c */
+int avc_recv(struct firedtv *fdtv, void *data, size_t length);
+int avc_tuner_status(struct firedtv *fdtv, struct firedtv_tuner_status *stat);
+struct dvb_frontend_parameters;
+int avc_tuner_dsd(struct firedtv *fdtv, struct dvb_frontend_parameters *params);
+int avc_tuner_set_pids(struct firedtv *fdtv, unsigned char pidc, u16 pid[]);
+int avc_tuner_get_ts(struct firedtv *fdtv);
+int avc_identify_subunit(struct firedtv *fdtv);
+struct dvb_diseqc_master_cmd;
+int avc_lnb_control(struct firedtv *fdtv, char voltage, char burst,
+                   char conttone, char nrdiseq,
+                   struct dvb_diseqc_master_cmd *diseqcmd);
+void avc_remote_ctrl_work(struct work_struct *work);
+int avc_register_remote_control(struct firedtv *fdtv);
+int avc_ca_app_info(struct firedtv *fdtv, char *app_info, unsigned int *len);
+int avc_ca_info(struct firedtv *fdtv, char *app_info, unsigned int *len);
+int avc_ca_reset(struct firedtv *fdtv);
+int avc_ca_pmt(struct firedtv *fdtv, char *app_info, int length);
+int avc_ca_get_time_date(struct firedtv *fdtv, int *interval);
+int avc_ca_enter_menu(struct firedtv *fdtv);
+int avc_ca_get_mmi(struct firedtv *fdtv, char *mmi_object, unsigned int *len);
+int cmp_establish_pp_connection(struct firedtv *fdtv, int plug, int channel);
+void cmp_break_pp_connection(struct firedtv *fdtv, int plug, int channel);
+
+/* firedtv-ci.c */
+int fdtv_ca_register(struct firedtv *fdtv);
+void fdtv_ca_release(struct firedtv *fdtv);
+
+/* firedtv-dvb.c */
+int fdtv_start_feed(struct dvb_demux_feed *dvbdmxfeed);
+int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
+int fdtv_dvb_register(struct firedtv *fdtv);
+void fdtv_dvb_unregister(struct firedtv *fdtv);
+struct firedtv *fdtv_alloc(struct device *dev,
+                          const struct firedtv_backend *backend,
+                          const char *name, size_t name_len);
+extern const char *fdtv_model_names[];
+
+/* firedtv-fe.c */
+void fdtv_frontend_init(struct firedtv *fdtv);
+
+/* firedtv-rc.c */
+#ifdef CONFIG_DVB_FIREDTV_INPUT
+int fdtv_register_rc(struct firedtv *fdtv, struct device *dev);
+void fdtv_unregister_rc(struct firedtv *fdtv);
+void fdtv_handle_rc(struct firedtv *fdtv, unsigned int code);
+#else
+static inline int fdtv_register_rc(struct firedtv *fdtv,
+                                  struct device *dev) { return 0; }
+static inline void fdtv_unregister_rc(struct firedtv *fdtv) {}
+static inline void fdtv_handle_rc(struct firedtv *fdtv, unsigned int code) {}
+#endif
+
+#endif /* _FIREDTV_H */
index 6bdfd47d679d9425d777ac68cc7b6b22d13e46f0..a2f185fd70725eb84c1e239afe7831c7a3ba828b 100644 (file)
@@ -2342,6 +2342,17 @@ config ATL1E
          To compile this driver as a module, choose M here.  The module
          will be called atl1e.
 
+config ATL1C
+       tristate "Atheros L1C Gigabit Ethernet support (EXPERIMENTAL)"
+       depends on PCI && EXPERIMENTAL
+       select CRC32
+       select MII
+       help
+         This driver supports the Atheros L1C gigabit ethernet adapter.
+
+         To compile this driver as a module, choose M here.  The module
+         will be called atl1c.
+
 config JME
        tristate "JMicron(R) PCI-Express Gigabit Ethernet support"
        depends on PCI
index a3c5c002f224343ad30343b0ffc485b358075c77..aca8492db65453fed3bae5a106497d597fb7c0c6 100644 (file)
@@ -17,6 +17,7 @@ obj-$(CONFIG_BONDING) += bonding/
 obj-$(CONFIG_ATL1) += atlx/
 obj-$(CONFIG_ATL2) += atlx/
 obj-$(CONFIG_ATL1E) += atl1e/
+obj-$(CONFIG_ATL1C) += atl1c/
 obj-$(CONFIG_GIANFAR) += gianfar_driver.o
 obj-$(CONFIG_TEHUTI) += tehuti.o
 obj-$(CONFIG_ENIC) += enic/
diff --git a/drivers/net/atl1c/Makefile b/drivers/net/atl1c/Makefile
new file mode 100644 (file)
index 0000000..c37d966
--- /dev/null
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ATL1C) += atl1c.o
+atl1c-objs := atl1c_main.o atl1c_hw.o atl1c_ethtool.o
diff --git a/drivers/net/atl1c/atl1c.h b/drivers/net/atl1c/atl1c.h
new file mode 100644 (file)
index 0000000..ac11b84
--- /dev/null
@@ -0,0 +1,606 @@
+/*
+ * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
+ *
+ * Derived from Intel e1000 driver
+ * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef _ATL1C_H_
+#define _ATL1C_H_
+
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/udp.h>
+#include <linux/mii.h>
+#include <linux/io.h>
+#include <linux/vmalloc.h>
+#include <linux/pagemap.h>
+#include <linux/tcp.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/if_vlan.h>
+#include <linux/workqueue.h>
+#include <net/checksum.h>
+#include <net/ip6_checksum.h>
+
+#include "atl1c_hw.h"
+
+/* Wake Up Filter Control */
+#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
+#define AT_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
+#define AT_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
+#define AT_WUFC_MC   0x00000008 /* Multicast Wakeup Enable */
+#define AT_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
+
+#define AT_VLAN_TO_TAG(_vlan, _tag)       \
+       _tag =  ((((_vlan) >> 8) & 0xFF)  |\
+                (((_vlan) & 0xFF) << 8))
+
+#define AT_TAG_TO_VLAN(_tag, _vlan)     \
+       _vlan = ((((_tag) >> 8) & 0xFF) |\
+               (((_tag) & 0xFF) << 8))
+
+#define SPEED_0                   0xffff
+#define HALF_DUPLEX        1
+#define FULL_DUPLEX        2
+
+#define AT_RX_BUF_SIZE         (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
+#define MAX_JUMBO_FRAME_SIZE   (9*1024)
+#define MAX_TX_OFFLOAD_THRESH  (9*1024)
+
+#define AT_MAX_RECEIVE_QUEUE    4
+#define AT_DEF_RECEIVE_QUEUE   1
+#define AT_MAX_TRANSMIT_QUEUE  2
+
+#define AT_DMA_HI_ADDR_MASK     0xffffffff00000000ULL
+#define AT_DMA_LO_ADDR_MASK     0x00000000ffffffffULL
+
+#define AT_TX_WATCHDOG  (5 * HZ)
+#define AT_MAX_INT_WORK                5
+#define AT_TWSI_EEPROM_TIMEOUT         100
+#define AT_HW_MAX_IDLE_DELAY   10
+#define AT_SUSPEND_LINK_TIMEOUT 28
+
+#define AT_ASPM_L0S_TIMER      6
+#define AT_ASPM_L1_TIMER       12
+
+#define ATL1C_PCIE_L0S_L1_DISABLE      0x01
+#define ATL1C_PCIE_PHY_RESET           0x02
+
+#define ATL1C_ASPM_L0s_ENABLE          0x0001
+#define ATL1C_ASPM_L1_ENABLE           0x0002
+
+#define AT_REGS_LEN    (75 * sizeof(u32))
+#define AT_EEPROM_LEN  512
+
+#define ATL1C_GET_DESC(R, i, type)     (&(((type *)((R)->desc))[i]))
+#define ATL1C_RFD_DESC(R, i)   ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
+#define ATL1C_TPD_DESC(R, i)   ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
+#define ATL1C_RRD_DESC(R, i)   ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
+
+/* tpd word 1 bit 0:7 General Checksum task offload */
+#define TPD_L4HDR_OFFSET_MASK  0x00FF
+#define TPD_L4HDR_OFFSET_SHIFT 0
+
+/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
+#define TPD_TCPHDR_OFFSET_MASK 0x00FF
+#define TPD_TCPHDR_OFFSET_SHIFT        0
+
+/* tpd word 1 bit 0:7 Custom Checksum task offload */
+#define TPD_PLOADOFFSET_MASK   0x00FF
+#define TPD_PLOADOFFSET_SHIFT  0
+
+/* tpd word 1 bit 8:17 */
+#define TPD_CCSUM_EN_MASK      0x0001
+#define TPD_CCSUM_EN_SHIFT     8
+#define TPD_IP_CSUM_MASK       0x0001
+#define TPD_IP_CSUM_SHIFT      9
+#define TPD_TCP_CSUM_MASK      0x0001
+#define TPD_TCP_CSUM_SHIFT     10
+#define TPD_UDP_CSUM_MASK      0x0001
+#define TPD_UDP_CSUM_SHIFT     11
+#define TPD_LSO_EN_MASK                0x0001  /* TCP Large Send Offload */
+#define TPD_LSO_EN_SHIFT       12
+#define TPD_LSO_VER_MASK       0x0001
+#define TPD_LSO_VER_SHIFT      13      /* 0 : ipv4; 1 : ipv4/ipv6 */
+#define TPD_CON_VTAG_MASK      0x0001
+#define TPD_CON_VTAG_SHIFT     14
+#define TPD_INS_VTAG_MASK      0x0001
+#define TPD_INS_VTAG_SHIFT     15
+#define TPD_IPV4_PACKET_MASK   0x0001  /* valid when LSO VER  is 1 */
+#define TPD_IPV4_PACKET_SHIFT  16
+#define TPD_ETH_TYPE_MASK      0x0001
+#define TPD_ETH_TYPE_SHIFT     17      /* 0 : 802.3 frame; 1 : Ethernet */
+
+/* tpd word 18:25 Custom Checksum task offload */
+#define TPD_CCSUM_OFFSET_MASK  0x00FF
+#define TPD_CCSUM_OFFSET_SHIFT 18
+#define TPD_CCSUM_EPAD_MASK    0x0001
+#define TPD_CCSUM_EPAD_SHIFT   30
+
+/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
+#define TPD_MSS_MASK            0x1FFF
+#define TPD_MSS_SHIFT          18
+
+#define TPD_EOP_MASK           0x0001
+#define TPD_EOP_SHIFT          31
+
+struct atl1c_tpd_desc {
+       __le16  buffer_len; /* include 4-byte CRC */
+       __le16  vlan_tag;
+       __le32  word1;
+       __le64  buffer_addr;
+};
+
+struct atl1c_tpd_ext_desc {
+       u32 reservd_0;
+       __le32 word1;
+       __le32 pkt_len;
+       u32 reservd_1;
+};
+/* rrs word 0 bit 0:31 */
+#define RRS_RX_CSUM_MASK       0xFFFF
+#define RRS_RX_CSUM_SHIFT      0
+#define RRS_RX_RFD_CNT_MASK    0x000F
+#define RRS_RX_RFD_CNT_SHIFT   16
+#define RRS_RX_RFD_INDEX_MASK  0x0FFF
+#define RRS_RX_RFD_INDEX_SHIFT 20
+
+/* rrs flag bit 0:16 */
+#define RRS_HEAD_LEN_MASK      0x00FF
+#define RRS_HEAD_LEN_SHIFT     0
+#define RRS_HDS_TYPE_MASK      0x0003
+#define RRS_HDS_TYPE_SHIFT     8
+#define RRS_CPU_NUM_MASK       0x0003
+#define        RRS_CPU_NUM_SHIFT       10
+#define RRS_HASH_FLG_MASK      0x000F
+#define RRS_HASH_FLG_SHIFT     12
+
+#define RRS_HDS_TYPE_HEAD      1
+#define RRS_HDS_TYPE_DATA      2
+
+#define RRS_IS_NO_HDS_TYPE(flag) \
+       (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == 0)
+
+#define RRS_IS_HDS_HEAD(flag) \
+       (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \
+                       RRS_HDS_TYPE_HEAD)
+
+#define RRS_IS_HDS_DATA(flag) \
+       (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \
+                       RRS_HDS_TYPE_DATA)
+
+/* rrs word 3 bit 0:31 */
+#define RRS_PKT_SIZE_MASK      0x3FFF
+#define RRS_PKT_SIZE_SHIFT     0
+#define RRS_ERR_L4_CSUM_MASK   0x0001
+#define RRS_ERR_L4_CSUM_SHIFT  14
+#define RRS_ERR_IP_CSUM_MASK   0x0001
+#define RRS_ERR_IP_CSUM_SHIFT  15
+#define RRS_VLAN_INS_MASK      0x0001
+#define RRS_VLAN_INS_SHIFT     16
+#define RRS_PROT_ID_MASK       0x0007
+#define RRS_PROT_ID_SHIFT      17
+#define RRS_RX_ERR_SUM_MASK    0x0001
+#define RRS_RX_ERR_SUM_SHIFT   20
+#define RRS_RX_ERR_CRC_MASK    0x0001
+#define RRS_RX_ERR_CRC_SHIFT   21
+#define RRS_RX_ERR_FAE_MASK    0x0001
+#define RRS_RX_ERR_FAE_SHIFT   22
+#define RRS_RX_ERR_TRUNC_MASK  0x0001
+#define RRS_RX_ERR_TRUNC_SHIFT 23
+#define RRS_RX_ERR_RUNC_MASK   0x0001
+#define RRS_RX_ERR_RUNC_SHIFT  24
+#define RRS_RX_ERR_ICMP_MASK   0x0001
+#define RRS_RX_ERR_ICMP_SHIFT  25
+#define RRS_PACKET_BCAST_MASK  0x0001
+#define RRS_PACKET_BCAST_SHIFT 26
+#define RRS_PACKET_MCAST_MASK  0x0001
+#define RRS_PACKET_MCAST_SHIFT 27
+#define RRS_PACKET_TYPE_MASK   0x0001
+#define RRS_PACKET_TYPE_SHIFT  28
+#define RRS_FIFO_FULL_MASK     0x0001
+#define RRS_FIFO_FULL_SHIFT    29
+#define RRS_802_3_LEN_ERR_MASK         0x0001
+#define RRS_802_3_LEN_ERR_SHIFT 30
+#define RRS_RXD_UPDATED_MASK   0x0001
+#define RRS_RXD_UPDATED_SHIFT  31
+
+#define RRS_ERR_L4_CSUM         0x00004000
+#define RRS_ERR_IP_CSUM         0x00008000
+#define RRS_VLAN_INS            0x00010000
+#define RRS_RX_ERR_SUM          0x00100000
+#define RRS_RX_ERR_CRC          0x00200000
+#define RRS_802_3_LEN_ERR      0x40000000
+#define RRS_RXD_UPDATED                0x80000000
+
+#define RRS_PACKET_TYPE_802_3          1
+#define RRS_PACKET_TYPE_ETH    0
+#define RRS_PACKET_IS_ETH(word) \
+       (((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK == \
+                       RRS_PACKET_TYPE_ETH)
+#define RRS_RXD_IS_VALID(word) \
+       ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
+
+#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
+       ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
+#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
+       ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
+
+struct atl1c_recv_ret_status {
+       __le32  word0;
+       __le32  rss_hash;
+       __le16  vlan_tag;
+       __le16  flag;
+       __le32  word3;
+};
+
+/* RFD desciptor */
+struct atl1c_rx_free_desc {
+       __le64  buffer_addr;
+};
+
+/* DMA Order Settings */
+enum atl1c_dma_order {
+       atl1c_dma_ord_in = 1,
+       atl1c_dma_ord_enh = 2,
+       atl1c_dma_ord_out = 4
+};
+
+enum atl1c_dma_rcb {
+       atl1c_rcb_64 = 0,
+       atl1c_rcb_128 = 1
+};
+
+enum atl1c_mac_speed {
+       atl1c_mac_speed_0 = 0,
+       atl1c_mac_speed_10_100 = 1,
+       atl1c_mac_speed_1000 = 2
+};
+
+enum atl1c_dma_req_block {
+       atl1c_dma_req_128 = 0,
+       atl1c_dma_req_256 = 1,
+       atl1c_dma_req_512 = 2,
+       atl1c_dma_req_1024 = 3,
+       atl1c_dma_req_2048 = 4,
+       atl1c_dma_req_4096 = 5
+};
+
+enum atl1c_rss_mode {
+       atl1c_rss_mode_disable = 0,
+       atl1c_rss_sig_que = 1,
+       atl1c_rss_mul_que_sig_int = 2,
+       atl1c_rss_mul_que_mul_int = 4,
+};
+
+enum atl1c_rss_type {
+       atl1c_rss_disable = 0,
+       atl1c_rss_ipv4 = 1,
+       atl1c_rss_ipv4_tcp = 2,
+       atl1c_rss_ipv6 = 4,
+       atl1c_rss_ipv6_tcp = 8
+};
+
+enum atl1c_nic_type {
+       athr_l1c = 0,
+       athr_l2c = 1,
+};
+
+enum atl1c_trans_queue {
+       atl1c_trans_normal = 0,
+       atl1c_trans_high = 1
+};
+
+struct atl1c_hw_stats {
+       /* rx */
+       unsigned long rx_ok;            /* The number of good packet received. */
+       unsigned long rx_bcast;         /* The number of good broadcast packet received. */
+       unsigned long rx_mcast;         /* The number of good multicast packet received. */
+       unsigned long rx_pause;         /* The number of Pause packet received. */
+       unsigned long rx_ctrl;          /* The number of Control packet received other than Pause frame. */
+       unsigned long rx_fcs_err;       /* The number of packets with bad FCS. */
+       unsigned long rx_len_err;       /* The number of packets with mismatch of length field and actual size. */
+       unsigned long rx_byte_cnt;      /* The number of bytes of good packet received. FCS is NOT included. */
+       unsigned long rx_runt;          /* The number of packets received that are less than 64 byte long and with good FCS. */
+       unsigned long rx_frag;          /* The number of packets received that are less than 64 byte long and with bad FCS. */
+       unsigned long rx_sz_64;         /* The number of good and bad packets received that are 64 byte long. */
+       unsigned long rx_sz_65_127;     /* The number of good and bad packets received that are between 65 and 127-byte long. */
+       unsigned long rx_sz_128_255;    /* The number of good and bad packets received that are between 128 and 255-byte long. */
+       unsigned long rx_sz_256_511;    /* The number of good and bad packets received that are between 256 and 511-byte long. */
+       unsigned long rx_sz_512_1023;   /* The number of good and bad packets received that are between 512 and 1023-byte long. */
+       unsigned long rx_sz_1024_1518;  /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
+       unsigned long rx_sz_1519_max;   /* The number of good and bad packets received that are between 1519-byte and MTU. */
+       unsigned long rx_sz_ov;         /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
+       unsigned long rx_rxf_ov;        /* The number of frame dropped due to occurrence of RX FIFO overflow. */
+       unsigned long rx_rrd_ov;        /* The number of frame dropped due to occurrence of RRD overflow. */
+       unsigned long rx_align_err;     /* Alignment Error */
+       unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
+       unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
+       unsigned long rx_err_addr;      /* The number of packets dropped due to address filtering. */
+
+       /* tx */
+       unsigned long tx_ok;            /* The number of good packet transmitted. */
+       unsigned long tx_bcast;         /* The number of good broadcast packet transmitted. */
+       unsigned long tx_mcast;         /* The number of good multicast packet transmitted. */
+       unsigned long tx_pause;         /* The number of Pause packet transmitted. */
+       unsigned long tx_exc_defer;     /* The number of packets transmitted with excessive deferral. */
+       unsigned long tx_ctrl;          /* The number of packets transmitted is a control frame, excluding Pause frame. */
+       unsigned long tx_defer;         /* The number of packets transmitted that is deferred. */
+       unsigned long tx_byte_cnt;      /* The number of bytes of data transmitted. FCS is NOT included. */
+       unsigned long tx_sz_64;         /* The number of good and bad packets transmitted that are 64 byte long. */
+       unsigned long tx_sz_65_127;     /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
+       unsigned long tx_sz_128_255;    /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
+       unsigned long tx_sz_256_511;    /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
+       unsigned long tx_sz_512_1023;   /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
+       unsigned long tx_sz_1024_1518;  /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
+       unsigned long tx_sz_1519_max;   /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
+       unsigned long tx_1_col;         /* The number of packets subsequently transmitted successfully with a single prior collision. */
+       unsigned long tx_2_col;         /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
+       unsigned long tx_late_col;      /* The number of packets transmitted with late collisions. */
+       unsigned long tx_abort_col;     /* The number of transmit packets aborted due to excessive collisions. */
+       unsigned long tx_underrun;      /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
+       unsigned long tx_rd_eop;        /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
+       unsigned long tx_len_err;       /* The number of transmit packets with length field does NOT match the actual frame size. */
+       unsigned long tx_trunc;         /* The number of transmit packets truncated due to size exceeding MTU. */
+       unsigned long tx_bcast_byte;    /* The byte count of broadcast packet transmitted, excluding FCS. */
+       unsigned long tx_mcast_byte;    /* The byte count of multicast packet transmitted, excluding FCS. */
+};
+
+struct atl1c_hw {
+       u8 __iomem      *hw_addr;            /* inner register address */
+       struct atl1c_adapter *adapter;
+       enum atl1c_nic_type  nic_type;
+       enum atl1c_dma_order dma_order;
+       enum atl1c_dma_rcb   rcb_value;
+       enum atl1c_dma_req_block dmar_block;
+       enum atl1c_dma_req_block dmaw_block;
+
+       u16 device_id;
+       u16 vendor_id;
+       u16 subsystem_id;
+       u16 subsystem_vendor_id;
+       u8 revision_id;
+
+       u32 intr_mask;
+       u8 dmaw_dly_cnt;
+       u8 dmar_dly_cnt;
+
+       u8 preamble_len;
+       u16 max_frame_size;
+       u16 min_frame_size;
+
+       enum atl1c_mac_speed mac_speed;
+       bool mac_duplex;
+       bool hibernate;
+       u16 media_type;
+#define MEDIA_TYPE_AUTO_SENSOR  0
+#define MEDIA_TYPE_100M_FULL    1
+#define MEDIA_TYPE_100M_HALF    2
+#define MEDIA_TYPE_10M_FULL     3
+#define MEDIA_TYPE_10M_HALF     4
+
+       u16 autoneg_advertised;
+       u16 mii_autoneg_adv_reg;
+       u16 mii_1000t_ctrl_reg;
+
+       u16 tx_imt;     /* TX Interrupt Moderator timer ( 2us resolution) */
+       u16 rx_imt;     /* RX Interrupt Moderator timer ( 2us resolution) */
+       u16 ict;        /* Interrupt Clear timer (2us resolution) */
+       u16 ctrl_flags;
+#define ATL1C_INTR_CLEAR_ON_READ       0x0001
+#define ATL1C_INTR_MODRT_ENABLE                0x0002
+#define ATL1C_CMB_ENABLE               0x0004
+#define ATL1C_SMB_ENABLE               0x0010
+#define ATL1C_TXQ_MODE_ENHANCE         0x0020
+#define ATL1C_RX_IPV6_CHKSUM           0x0040
+#define ATL1C_ASPM_L0S_SUPPORT         0x0080
+#define ATL1C_ASPM_L1_SUPPORT          0x0100
+#define ATL1C_ASPM_CTRL_MON            0x0200
+#define ATL1C_HIB_DISABLE              0x0400
+#define ATL1C_LINK_CAP_1000M           0x0800
+#define ATL1C_FPGA_VERSION             0x8000
+       u16 cmb_tpd;
+       u16 cmb_rrd;
+       u16 cmb_rx_timer; /* 2us resolution */
+       u16 cmb_tx_timer;
+       u32 smb_timer;
+
+       u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
+                         interrupt request */
+       u16 tpd_thresh;
+       u8 tpd_burst;   /* Number of TPD to prefetch in cache-aligned burst. */
+       u8 rfd_burst;
+       enum atl1c_rss_type rss_type;
+       enum atl1c_rss_mode rss_mode;
+       u8 rss_hash_bits;
+       u32 base_cpu;
+       u32 indirect_tab;
+       u8 mac_addr[ETH_ALEN];
+       u8 perm_mac_addr[ETH_ALEN];
+
+       bool phy_configured;
+       bool re_autoneg;
+       bool emi_ca;
+};
+
+/*
+ * atl1c_ring_header represents a single, contiguous block of DMA space
+ * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
+ * message blocks (cmb, smb) described below
+ */
+struct atl1c_ring_header {
+       void *desc;             /* virtual address */
+       dma_addr_t dma;         /* physical address*/
+       unsigned int size;      /* length in bytes */
+};
+
+/*
+ * atl1c_buffer is wrapper around a pointer to a socket buffer
+ * so a DMA handle can be stored along with the skb
+ */
+struct atl1c_buffer {
+       struct sk_buff *skb;    /* socket buffer */
+       u16 length;             /* rx buffer length */
+       u16 state;              /* state of buffer */
+#define ATL1_BUFFER_FREE       0
+#define ATL1_BUFFER_BUSY       1
+       dma_addr_t dma;
+};
+
+/* transimit packet descriptor (tpd) ring */
+struct atl1c_tpd_ring {
+       void *desc;             /* descriptor ring virtual address */
+       dma_addr_t dma;         /* descriptor ring physical address */
+       u16 size;               /* descriptor ring length in bytes */
+       u16 count;              /* number of descriptors in the ring */
+       u16 next_to_use;        /* this is protectd by adapter->tx_lock */
+       atomic_t next_to_clean;
+       struct atl1c_buffer *buffer_info;
+};
+
+/* receive free descriptor (rfd) ring */
+struct atl1c_rfd_ring {
+       void *desc;             /* descriptor ring virtual address */
+       dma_addr_t dma;         /* descriptor ring physical address */
+       u16 size;               /* descriptor ring length in bytes */
+       u16 count;              /* number of descriptors in the ring */
+       u16 next_to_use;
+       u16 next_to_clean;
+       struct atl1c_buffer *buffer_info;
+};
+
+/* receive return desciptor (rrd) ring */
+struct atl1c_rrd_ring {
+       void *desc;             /* descriptor ring virtual address */
+       dma_addr_t dma;         /* descriptor ring physical address */
+       u16 size;               /* descriptor ring length in bytes */
+       u16 count;              /* number of descriptors in the ring */
+       u16 next_to_use;
+       u16 next_to_clean;
+};
+
+struct atl1c_cmb {
+       void *cmb;
+       dma_addr_t dma;
+};
+
+struct atl1c_smb {
+       void *smb;
+       dma_addr_t dma;
+};
+
+/* board specific private data structure */
+struct atl1c_adapter {
+       struct net_device   *netdev;
+       struct pci_dev      *pdev;
+       struct vlan_group   *vlgrp;
+       struct napi_struct  napi;
+       struct atl1c_hw        hw;
+       struct atl1c_hw_stats  hw_stats;
+       struct net_device_stats net_stats;
+       struct mii_if_info  mii;    /* MII interface info */
+       u16 rx_buffer_len;
+
+       unsigned long flags;
+#define __AT_TESTING        0x0001
+#define __AT_RESETTING      0x0002
+#define __AT_DOWN           0x0003
+       u32 msg_enable;
+
+       bool have_msi;
+       u32 wol;
+       u16 link_speed;
+       u16 link_duplex;
+
+       spinlock_t mdio_lock;
+       spinlock_t tx_lock;
+       atomic_t irq_sem;
+
+       struct work_struct reset_task;
+       struct work_struct link_chg_task;
+       struct timer_list watchdog_timer;
+       struct timer_list phy_config_timer;
+
+       /* All Descriptor memory */
+       struct atl1c_ring_header ring_header;
+       struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
+       struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
+       struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
+       struct atl1c_cmb cmb;
+       struct atl1c_smb smb;
+       int num_rx_queues;
+       u32 bd_number;     /* board number;*/
+};
+
+#define AT_WRITE_REG(a, reg, value) ( \
+               writel((value), ((a)->hw_addr + reg)))
+
+#define AT_WRITE_FLUSH(a) (\
+               readl((a)->hw_addr))
+
+#define AT_READ_REG(a, reg, pdata) do {                                        \
+               if (unlikely((a)->hibernate)) {                         \
+                       readl((a)->hw_addr + reg);                      \
+                       *(u32 *)pdata = readl((a)->hw_addr + reg);      \
+               } else {                                                \
+                       *(u32 *)pdata = readl((a)->hw_addr + reg);      \
+               }                                                       \
+       } while (0)
+
+#define AT_WRITE_REGB(a, reg, value) (\
+               writeb((value), ((a)->hw_addr + reg)))
+
+#define AT_READ_REGB(a, reg) (\
+               readb((a)->hw_addr + reg))
+
+#define AT_WRITE_REGW(a, reg, value) (\
+               writew((value), ((a)->hw_addr + reg)))
+
+#define AT_READ_REGW(a, reg) (\
+               readw((a)->hw_addr + reg))
+
+#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
+               writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
+
+#define AT_READ_REG_ARRAY(a, reg, offset) ( \
+               readl(((a)->hw_addr + reg) + ((offset) << 2)))
+
+extern char atl1c_driver_name[];
+extern char atl1c_driver_version[];
+
+extern int atl1c_up(struct atl1c_adapter *adapter);
+extern void atl1c_down(struct atl1c_adapter *adapter);
+extern void atl1c_reinit_locked(struct atl1c_adapter *adapter);
+extern s32 atl1c_reset_hw(struct atl1c_hw *hw);
+extern void atl1c_set_ethtool_ops(struct net_device *netdev);
+#endif /* _ATL1C_H_ */
diff --git a/drivers/net/atl1c/atl1c_ethtool.c b/drivers/net/atl1c/atl1c_ethtool.c
new file mode 100644 (file)
index 0000000..45c5b73
--- /dev/null
@@ -0,0 +1,317 @@
+/*
+ * Copyright(c) 2009 - 2009 Atheros Corporation. All rights reserved.
+ *
+ * Derived from Intel e1000 driver
+ * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+
+#include "atl1c.h"
+
+static int atl1c_get_settings(struct net_device *netdev,
+                             struct ethtool_cmd *ecmd)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct atl1c_hw *hw = &adapter->hw;
+
+       ecmd->supported = (SUPPORTED_10baseT_Half  |
+                          SUPPORTED_10baseT_Full  |
+                          SUPPORTED_100baseT_Half |
+                          SUPPORTED_100baseT_Full |
+                          SUPPORTED_Autoneg       |
+                          SUPPORTED_TP);
+       if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M)
+               ecmd->supported |= SUPPORTED_1000baseT_Full;
+
+       ecmd->advertising = ADVERTISED_TP;
+
+       ecmd->advertising |= hw->autoneg_advertised;
+
+       ecmd->port = PORT_TP;
+       ecmd->phy_address = 0;
+       ecmd->transceiver = XCVR_INTERNAL;
+
+       if (adapter->link_speed != SPEED_0) {
+               ecmd->speed = adapter->link_speed;
+               if (adapter->link_duplex == FULL_DUPLEX)
+                       ecmd->duplex = DUPLEX_FULL;
+               else
+                       ecmd->duplex = DUPLEX_HALF;
+       } else {
+               ecmd->speed = -1;
+               ecmd->duplex = -1;
+       }
+
+       ecmd->autoneg = AUTONEG_ENABLE;
+       return 0;
+}
+
+static int atl1c_set_settings(struct net_device *netdev,
+                             struct ethtool_cmd *ecmd)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct atl1c_hw *hw = &adapter->hw;
+       u16  autoneg_advertised;
+
+       while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
+               msleep(1);
+
+       if (ecmd->autoneg == AUTONEG_ENABLE) {
+               autoneg_advertised = ADVERTISED_Autoneg;
+       } else {
+               if (ecmd->speed == SPEED_1000) {
+                       if (ecmd->duplex != DUPLEX_FULL) {
+                               if (netif_msg_link(adapter))
+                                       dev_warn(&adapter->pdev->dev,
+                                               "1000M half is invalid\n");
+                               clear_bit(__AT_RESETTING, &adapter->flags);
+                               return -EINVAL;
+                       }
+                       autoneg_advertised = ADVERTISED_1000baseT_Full;
+               } else if (ecmd->speed == SPEED_100) {
+                       if (ecmd->duplex == DUPLEX_FULL)
+                               autoneg_advertised = ADVERTISED_100baseT_Full;
+                       else
+                               autoneg_advertised = ADVERTISED_100baseT_Half;
+               } else {
+                       if (ecmd->duplex == DUPLEX_FULL)
+                               autoneg_advertised = ADVERTISED_10baseT_Full;
+                       else
+                               autoneg_advertised = ADVERTISED_10baseT_Half;
+               }
+       }
+
+       if (hw->autoneg_advertised != autoneg_advertised) {
+               hw->autoneg_advertised = autoneg_advertised;
+               if (atl1c_restart_autoneg(hw) != 0) {
+                       if (netif_msg_link(adapter))
+                               dev_warn(&adapter->pdev->dev,
+                                       "ethtool speed/duplex setting failed\n");
+                       clear_bit(__AT_RESETTING, &adapter->flags);
+                       return -EINVAL;
+               }
+       }
+       clear_bit(__AT_RESETTING, &adapter->flags);
+       return 0;
+}
+
+static u32 atl1c_get_tx_csum(struct net_device *netdev)
+{
+       return (netdev->features & NETIF_F_HW_CSUM) != 0;
+}
+
+static u32 atl1c_get_msglevel(struct net_device *netdev)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       return adapter->msg_enable;
+}
+
+static void atl1c_set_msglevel(struct net_device *netdev, u32 data)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       adapter->msg_enable = data;
+}
+
+static int atl1c_get_regs_len(struct net_device *netdev)
+{
+       return AT_REGS_LEN;
+}
+
+static void atl1c_get_regs(struct net_device *netdev,
+                          struct ethtool_regs *regs, void *p)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct atl1c_hw *hw = &adapter->hw;
+       u32 *regs_buff = p;
+       u16 phy_data;
+
+       memset(p, 0, AT_REGS_LEN);
+
+       regs->version = 0;
+       AT_READ_REG(hw, REG_VPD_CAP,              p++);
+       AT_READ_REG(hw, REG_PM_CTRL,              p++);
+       AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL,  p++);
+       AT_READ_REG(hw, REG_TWSI_CTRL,            p++);
+       AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL,   p++);
+       AT_READ_REG(hw, REG_MASTER_CTRL,          p++);
+       AT_READ_REG(hw, REG_MANUAL_TIMER_INIT,    p++);
+       AT_READ_REG(hw, REG_IRQ_MODRT_TIMER_INIT, p++);
+       AT_READ_REG(hw, REG_GPHY_CTRL,            p++);
+       AT_READ_REG(hw, REG_LINK_CTRL,            p++);
+       AT_READ_REG(hw, REG_IDLE_STATUS,          p++);
+       AT_READ_REG(hw, REG_MDIO_CTRL,            p++);
+       AT_READ_REG(hw, REG_SERDES_LOCK,          p++);
+       AT_READ_REG(hw, REG_MAC_CTRL,             p++);
+       AT_READ_REG(hw, REG_MAC_IPG_IFG,          p++);
+       AT_READ_REG(hw, REG_MAC_STA_ADDR,         p++);
+       AT_READ_REG(hw, REG_MAC_STA_ADDR+4,       p++);
+       AT_READ_REG(hw, REG_RX_HASH_TABLE,        p++);
+       AT_READ_REG(hw, REG_RX_HASH_TABLE+4,      p++);
+       AT_READ_REG(hw, REG_RXQ_CTRL,             p++);
+       AT_READ_REG(hw, REG_TXQ_CTRL,             p++);
+       AT_READ_REG(hw, REG_MTU,                  p++);
+       AT_READ_REG(hw, REG_WOL_CTRL,             p++);
+
+       atl1c_read_phy_reg(hw, MII_BMCR, &phy_data);
+       regs_buff[73] = (u32) phy_data;
+       atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
+       regs_buff[74] = (u32) phy_data;
+}
+
+static int atl1c_get_eeprom_len(struct net_device *netdev)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+
+       if (atl1c_check_eeprom_exist(&adapter->hw))
+               return AT_EEPROM_LEN;
+       else
+               return 0;
+}
+
+static int atl1c_get_eeprom(struct net_device *netdev,
+               struct ethtool_eeprom *eeprom, u8 *bytes)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct atl1c_hw *hw = &adapter->hw;
+       u32 *eeprom_buff;
+       int first_dword, last_dword;
+       int ret_val = 0;
+       int i;
+
+       if (eeprom->len == 0)
+               return -EINVAL;
+
+       if (!atl1c_check_eeprom_exist(hw)) /* not exist */
+               return -EINVAL;
+
+       eeprom->magic = adapter->pdev->vendor |
+                       (adapter->pdev->device << 16);
+
+       first_dword = eeprom->offset >> 2;
+       last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
+
+       eeprom_buff = kmalloc(sizeof(u32) *
+                       (last_dword - first_dword + 1), GFP_KERNEL);
+       if (eeprom_buff == NULL)
+               return -ENOMEM;
+
+       for (i = first_dword; i < last_dword; i++) {
+               if (!atl1c_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) {
+                       kfree(eeprom_buff);
+                       return -EIO;
+               }
+       }
+
+       memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
+                       eeprom->len);
+       kfree(eeprom_buff);
+
+       return ret_val;
+       return 0;
+}
+
+static void atl1c_get_drvinfo(struct net_device *netdev,
+               struct ethtool_drvinfo *drvinfo)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+
+       strncpy(drvinfo->driver,  atl1c_driver_name, sizeof(drvinfo->driver));
+       strncpy(drvinfo->version, atl1c_driver_version,
+               sizeof(drvinfo->version));
+       strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
+       strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
+               sizeof(drvinfo->bus_info));
+       drvinfo->n_stats = 0;
+       drvinfo->testinfo_len = 0;
+       drvinfo->regdump_len = atl1c_get_regs_len(netdev);
+       drvinfo->eedump_len = atl1c_get_eeprom_len(netdev);
+}
+
+static void atl1c_get_wol(struct net_device *netdev,
+                         struct ethtool_wolinfo *wol)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+
+       wol->supported = WAKE_MAGIC | WAKE_PHY;
+       wol->wolopts = 0;
+
+       if (adapter->wol & AT_WUFC_EX)
+               wol->wolopts |= WAKE_UCAST;
+       if (adapter->wol & AT_WUFC_MC)
+               wol->wolopts |= WAKE_MCAST;
+       if (adapter->wol & AT_WUFC_BC)
+               wol->wolopts |= WAKE_BCAST;
+       if (adapter->wol & AT_WUFC_MAG)
+               wol->wolopts |= WAKE_MAGIC;
+       if (adapter->wol & AT_WUFC_LNKC)
+               wol->wolopts |= WAKE_PHY;
+
+       return;
+}
+
+static int atl1c_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+
+       if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
+                           WAKE_MCAST | WAKE_BCAST | WAKE_MCAST))
+               return -EOPNOTSUPP;
+       /* these settings will always override what we currently have */
+       adapter->wol = 0;
+
+       if (wol->wolopts & WAKE_MAGIC)
+               adapter->wol |= AT_WUFC_MAG;
+       if (wol->wolopts & WAKE_PHY)
+               adapter->wol |= AT_WUFC_LNKC;
+
+       return 0;
+}
+
+static int atl1c_nway_reset(struct net_device *netdev)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       if (netif_running(netdev))
+               atl1c_reinit_locked(adapter);
+       return 0;
+}
+
+static struct ethtool_ops atl1c_ethtool_ops = {
+       .get_settings           = atl1c_get_settings,
+       .set_settings           = atl1c_set_settings,
+       .get_drvinfo            = atl1c_get_drvinfo,
+       .get_regs_len           = atl1c_get_regs_len,
+       .get_regs               = atl1c_get_regs,
+       .get_wol                = atl1c_get_wol,
+       .set_wol                = atl1c_set_wol,
+       .get_msglevel           = atl1c_get_msglevel,
+       .set_msglevel           = atl1c_set_msglevel,
+       .nway_reset             = atl1c_nway_reset,
+       .get_link               = ethtool_op_get_link,
+       .get_eeprom_len         = atl1c_get_eeprom_len,
+       .get_eeprom             = atl1c_get_eeprom,
+       .get_tx_csum            = atl1c_get_tx_csum,
+       .get_sg                 = ethtool_op_get_sg,
+       .set_sg                 = ethtool_op_set_sg,
+};
+
+void atl1c_set_ethtool_ops(struct net_device *netdev)
+{
+       SET_ETHTOOL_OPS(netdev, &atl1c_ethtool_ops);
+}
diff --git a/drivers/net/atl1c/atl1c_hw.c b/drivers/net/atl1c/atl1c_hw.c
new file mode 100644 (file)
index 0000000..3e69b94
--- /dev/null
@@ -0,0 +1,527 @@
+/*
+ * Copyright(c) 2007 Atheros Corporation. All rights reserved.
+ *
+ * Derived from Intel e1000 driver
+ * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/mii.h>
+#include <linux/crc32.h>
+
+#include "atl1c.h"
+
+/*
+ * check_eeprom_exist
+ * return 1 if eeprom exist
+ */
+int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
+{
+       u32 data;
+
+       AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
+       if (data & TWSI_DEBUG_DEV_EXIST)
+               return 1;
+
+       return 0;
+}
+
+void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
+{
+       u32 value;
+       /*
+        * 00-0B-6A-F6-00-DC
+        * 0:  6AF600DC 1: 000B
+        * low dword
+        */
+       value = (((u32)hw->mac_addr[2]) << 24) |
+               (((u32)hw->mac_addr[3]) << 16) |
+               (((u32)hw->mac_addr[4]) << 8)  |
+               (((u32)hw->mac_addr[5])) ;
+       AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
+       /* hight dword */
+       value = (((u32)hw->mac_addr[0]) << 8) |
+               (((u32)hw->mac_addr[1])) ;
+       AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
+}
+
+/*
+ * atl1c_get_permanent_address
+ * return 0 if get valid mac address,
+ */
+static int atl1c_get_permanent_address(struct atl1c_hw *hw)
+{
+       u32 addr[2];
+       u32 i;
+       u32 otp_ctrl_data;
+       u32 twsi_ctrl_data;
+       u8  eth_addr[ETH_ALEN];
+
+       /* init */
+       addr[0] = addr[1] = 0;
+       AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
+       if (atl1c_check_eeprom_exist(hw)) {
+               /* Enable OTP CLK */
+               if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
+                       otp_ctrl_data |= OTP_CTRL_CLK_EN;
+                       AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
+                       AT_WRITE_FLUSH(hw);
+                       msleep(1);
+               }
+
+               AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
+               twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
+               AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
+               for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
+                       msleep(10);
+                       AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
+                       if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
+                               break;
+               }
+               if (i >= AT_TWSI_EEPROM_TIMEOUT)
+                       return -1;
+       }
+       /* Disable OTP_CLK */
+       if (otp_ctrl_data & OTP_CTRL_CLK_EN) {
+               otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
+               AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
+               AT_WRITE_FLUSH(hw);
+               msleep(1);
+       }
+
+       /* maybe MAC-address is from BIOS */
+       AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
+       AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
+       *(u32 *) &eth_addr[2] = swab32(addr[0]);
+       *(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
+
+       if (is_valid_ether_addr(eth_addr)) {
+               memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
+               return 0;
+       }
+
+       return -1;
+}
+
+bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value)
+{
+       int i;
+       int ret = false;
+       u32 otp_ctrl_data;
+       u32 control;
+       u32 data;
+
+       if (offset & 3)
+               return ret; /* address do not align */
+
+       AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
+       if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
+               AT_WRITE_REG(hw, REG_OTP_CTRL,
+                               (otp_ctrl_data | OTP_CTRL_CLK_EN));
+
+       AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
+       control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT;
+       AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
+
+       for (i = 0; i < 10; i++) {
+               udelay(100);
+               AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
+               if (control & EEPROM_CTRL_RW)
+                       break;
+       }
+       if (control & EEPROM_CTRL_RW) {
+               AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
+               AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
+               data = data & 0xFFFF;
+               *p_value = swab32((data << 16) | (*p_value >> 16));
+               ret = true;
+       }
+       if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
+               AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
+
+       return ret;
+}
+/*
+ * Reads the adapter's MAC address from the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ */
+int atl1c_read_mac_addr(struct atl1c_hw *hw)
+{
+       int err = 0;
+
+       err = atl1c_get_permanent_address(hw);
+       if (err)
+               random_ether_addr(hw->perm_mac_addr);
+
+       memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
+       return 0;
+}
+
+/*
+ * atl1c_hash_mc_addr
+ *  purpose
+ *      set hash value for a multicast address
+ *      hash calcu processing :
+ *          1. calcu 32bit CRC for multicast address
+ *          2. reverse crc with MSB to LSB
+ */
+u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr)
+{
+       u32 crc32;
+       u32 value = 0;
+       int i;
+
+       crc32 = ether_crc_le(6, mc_addr);
+       for (i = 0; i < 32; i++)
+               value |= (((crc32 >> i) & 1) << (31 - i));
+
+       return value;
+}
+
+/*
+ * Sets the bit in the multicast table corresponding to the hash value.
+ * hw - Struct containing variables accessed by shared code
+ * hash_value - Multicast address hash value
+ */
+void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
+{
+       u32 hash_bit, hash_reg;
+       u32 mta;
+
+       /*
+        * The HASH Table  is a register array of 2 32-bit registers.
+        * It is treated like an array of 64 bits.  We want to set
+        * bit BitArray[hash_value]. So we figure out what register
+        * the bit is in, read it, OR in the new bit, then write
+        * back the new value.  The register is determined by the
+        * upper bit of the hash value and the bit within that
+        * register are determined by the lower 5 bits of the value.
+        */
+       hash_reg = (hash_value >> 31) & 0x1;
+       hash_bit = (hash_value >> 26) & 0x1F;
+
+       mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
+
+       mta |= (1 << hash_bit);
+
+       AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
+}
+
+/*
+ * Reads the value from a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to read
+ */
+int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
+{
+       u32 val;
+       int i;
+
+       val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
+               MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
+               MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
+
+       AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
+
+       for (i = 0; i < MDIO_WAIT_TIMES; i++) {
+               udelay(2);
+               AT_READ_REG(hw, REG_MDIO_CTRL, &val);
+               if (!(val & (MDIO_START | MDIO_BUSY)))
+                       break;
+       }
+       if (!(val & (MDIO_START | MDIO_BUSY))) {
+               *phy_data = (u16)val;
+               return 0;
+       }
+
+       return -1;
+}
+
+/*
+ * Writes a value to a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to write
+ * data - data to write to the PHY
+ */
+int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
+{
+       int i;
+       u32 val;
+
+       val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT   |
+              (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
+              MDIO_SUP_PREAMBLE | MDIO_START |
+              MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
+
+       AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
+
+       for (i = 0; i < MDIO_WAIT_TIMES; i++) {
+               udelay(2);
+               AT_READ_REG(hw, REG_MDIO_CTRL, &val);
+               if (!(val & (MDIO_START | MDIO_BUSY)))
+                       break;
+       }
+
+       if (!(val & (MDIO_START | MDIO_BUSY)))
+               return 0;
+
+       return -1;
+}
+
+/*
+ * Configures PHY autoneg and flow control advertisement settings
+ *
+ * hw - Struct containing variables accessed by shared code
+ */
+static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
+{
+       u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_SPEED_MASK;
+       u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP &
+                               ~GIGA_CR_1000T_SPEED_MASK;
+
+       if (hw->autoneg_advertised & ADVERTISED_10baseT_Half)
+               mii_adv_data |= ADVERTISE_10HALF;
+       if (hw->autoneg_advertised & ADVERTISED_10baseT_Full)
+               mii_adv_data |= ADVERTISE_10FULL;
+       if (hw->autoneg_advertised & ADVERTISED_100baseT_Half)
+               mii_adv_data |= ADVERTISE_100HALF;
+       if (hw->autoneg_advertised & ADVERTISED_100baseT_Full)
+               mii_adv_data |= ADVERTISE_100FULL;
+
+       if (hw->autoneg_advertised & ADVERTISED_Autoneg)
+               mii_adv_data |= ADVERTISE_10HALF  | ADVERTISE_10FULL |
+                               ADVERTISE_100HALF | ADVERTISE_100FULL;
+
+       if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M) {
+               if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
+                       mii_giga_ctrl_data |= ADVERTISE_1000HALF;
+               if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
+                       mii_giga_ctrl_data |= ADVERTISE_1000FULL;
+               if (hw->autoneg_advertised & ADVERTISED_Autoneg)
+                       mii_giga_ctrl_data |= ADVERTISE_1000HALF |
+                                       ADVERTISE_1000FULL;
+       }
+
+       if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 ||
+           atl1c_write_phy_reg(hw, MII_GIGA_CR, mii_giga_ctrl_data) != 0)
+               return -1;
+       return 0;
+}
+
+void atl1c_phy_disable(struct atl1c_hw *hw)
+{
+       AT_WRITE_REGW(hw, REG_GPHY_CTRL,
+                       GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
+}
+
+static void atl1c_phy_magic_data(struct atl1c_hw *hw)
+{
+       u16 data;
+
+       data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
+               ((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
+               ANA_INTERVAL_SEL_TIMER_SHIFT);
+
+       atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
+       atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
+
+       data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
+               ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
+               ANA_SERDES_EN_LCKDT;
+
+       atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
+       atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
+
+       data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
+               ((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
+               ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
+               ANA_BP_SMALL_BW;
+
+       atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
+       atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
+
+       data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
+               ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
+               ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
+               ANA_IECHO_ADJ_0_SHIFT);
+
+       atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
+       atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
+
+       data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
+               ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
+               ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
+
+       atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
+       atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
+
+       if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
+               atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
+               if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
+                       return;
+               data &= ~ANA_TOP_PS_EN;
+               atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
+
+               atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
+               if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
+                       return;
+               data &= ~ANA_PS_HIB_EN;
+               atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
+       }
+}
+
+int atl1c_phy_reset(struct atl1c_hw *hw)
+{
+       struct atl1c_adapter *adapter = hw->adapter;
+       struct pci_dev *pdev = adapter->pdev;
+       u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
+       u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
+       int err;
+
+       if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
+               phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
+
+       AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
+       AT_WRITE_FLUSH(hw);
+       msleep(40);
+       phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
+       AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
+       AT_WRITE_FLUSH(hw);
+       msleep(10);
+
+       /*Enable PHY LinkChange Interrupt */
+       err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
+       if (err) {
+               if (netif_msg_hw(adapter))
+                       dev_err(&pdev->dev,
+                               "Error enable PHY linkChange Interrupt\n");
+               return err;
+       }
+       if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
+               atl1c_phy_magic_data(hw);
+       return 0;
+}
+
+int atl1c_phy_init(struct atl1c_hw *hw)
+{
+       struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
+       struct pci_dev *pdev = adapter->pdev;
+       int ret_val;
+       u16 mii_bmcr_data = BMCR_RESET;
+       u16 phy_id1, phy_id2;
+
+       if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &phy_id1) != 0) ||
+               (atl1c_read_phy_reg(hw, MII_PHYSID2, &phy_id2) != 0)) {
+                       if (netif_msg_link(adapter))
+                               dev_err(&pdev->dev, "Error get phy ID\n");
+               return -1;
+       }
+       switch (hw->media_type) {
+       case MEDIA_TYPE_AUTO_SENSOR:
+               ret_val = atl1c_phy_setup_adv(hw);
+               if (ret_val) {
+                       if (netif_msg_link(adapter))
+                               dev_err(&pdev->dev,
+                                       "Error Setting up Auto-Negotiation\n");
+                       return ret_val;
+               }
+               mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
+               break;
+       case MEDIA_TYPE_100M_FULL:
+               mii_bmcr_data |= BMCR_SPEED_100 | BMCR_FULL_DUPLEX;
+               break;
+       case MEDIA_TYPE_100M_HALF:
+               mii_bmcr_data |= BMCR_SPEED_100;
+               break;
+       case MEDIA_TYPE_10M_FULL:
+               mii_bmcr_data |= BMCR_SPEED_10 | BMCR_FULL_DUPLEX;
+               break;
+       case MEDIA_TYPE_10M_HALF:
+               mii_bmcr_data |= BMCR_SPEED_10;
+               break;
+       default:
+               if (netif_msg_link(adapter))
+                       dev_err(&pdev->dev, "Wrong Media type %d\n",
+                               hw->media_type);
+               return -1;
+               break;
+       }
+
+       ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
+       if (ret_val)
+               return ret_val;
+       hw->phy_configured = true;
+
+       return 0;
+}
+
+/*
+ * Detects the current speed and duplex settings of the hardware.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * speed - Speed of the connection
+ * duplex - Duplex setting of the connection
+ */
+int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
+{
+       int err;
+       u16 phy_data;
+
+       /* Read   PHY Specific Status Register (17) */
+       err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
+       if (err)
+               return err;
+
+       if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED))
+               return -1;
+
+       switch (phy_data & GIGA_PSSR_SPEED) {
+       case GIGA_PSSR_1000MBS:
+               *speed = SPEED_1000;
+               break;
+       case GIGA_PSSR_100MBS:
+               *speed = SPEED_100;
+               break;
+       case  GIGA_PSSR_10MBS:
+               *speed = SPEED_10;
+               break;
+       default:
+               return -1;
+               break;
+       }
+
+       if (phy_data & GIGA_PSSR_DPLX)
+               *duplex = FULL_DUPLEX;
+       else
+               *duplex = HALF_DUPLEX;
+
+       return 0;
+}
+
+int atl1c_restart_autoneg(struct atl1c_hw *hw)
+{
+       int err = 0;
+       u16 mii_bmcr_data = BMCR_RESET;
+
+       err = atl1c_phy_setup_adv(hw);
+       if (err)
+               return err;
+       mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
+
+       return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
+}
diff --git a/drivers/net/atl1c/atl1c_hw.h b/drivers/net/atl1c/atl1c_hw.h
new file mode 100644 (file)
index 0000000..c2c738d
--- /dev/null
@@ -0,0 +1,859 @@
+/*
+ * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
+ *
+ * Derived from Intel e1000 driver
+ * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef _ATL1C_HW_H_
+#define _ATL1C_HW_H_
+
+#include <linux/types.h>
+#include <linux/mii.h>
+
+struct atl1c_adapter;
+struct atl1c_hw;
+
+/* function prototype */
+void atl1c_phy_disable(struct atl1c_hw *hw);
+void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
+int atl1c_phy_reset(struct atl1c_hw *hw);
+int atl1c_read_mac_addr(struct atl1c_hw *hw);
+int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
+u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
+void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
+int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
+int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
+bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
+int atl1c_phy_init(struct atl1c_hw *hw);
+int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
+int atl1c_restart_autoneg(struct atl1c_hw *hw);
+
+/* register definition */
+#define REG_DEVICE_CAP                 0x5C
+#define DEVICE_CAP_MAX_PAYLOAD_MASK     0x7
+#define DEVICE_CAP_MAX_PAYLOAD_SHIFT    0
+
+#define REG_DEVICE_CTRL                        0x60
+#define DEVICE_CTRL_MAX_PAYLOAD_MASK    0x7
+#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT   5
+#define DEVICE_CTRL_MAX_RREQ_SZ_MASK    0x7
+#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT   12
+
+#define REG_LINK_CTRL                  0x68
+#define LINK_CTRL_L0S_EN               0x01
+#define LINK_CTRL_L1_EN                        0x02
+
+#define REG_VPD_CAP                    0x6C
+#define VPD_CAP_ID_MASK                 0xff
+#define VPD_CAP_ID_SHIFT                0
+#define VPD_CAP_NEXT_PTR_MASK           0xFF
+#define VPD_CAP_NEXT_PTR_SHIFT          8
+#define VPD_CAP_VPD_ADDR_MASK           0x7FFF
+#define VPD_CAP_VPD_ADDR_SHIFT          16
+#define VPD_CAP_VPD_FLAG                0x80000000
+
+#define REG_VPD_DATA                   0x70
+
+#define REG_PCIE_UC_SEVERITY           0x10C
+#define PCIE_UC_SERVRITY_TRN           0x00000001
+#define PCIE_UC_SERVRITY_DLP           0x00000010
+#define PCIE_UC_SERVRITY_PSN_TLP       0x00001000
+#define PCIE_UC_SERVRITY_FCP           0x00002000
+#define PCIE_UC_SERVRITY_CPL_TO                0x00004000
+#define PCIE_UC_SERVRITY_CA            0x00008000
+#define PCIE_UC_SERVRITY_UC            0x00010000
+#define PCIE_UC_SERVRITY_ROV           0x00020000
+#define PCIE_UC_SERVRITY_MLFP          0x00040000
+#define PCIE_UC_SERVRITY_ECRC          0x00080000
+#define PCIE_UC_SERVRITY_UR            0x00100000
+
+#define REG_DEV_SERIALNUM_CTRL         0x200
+#define REG_DEV_MAC_SEL_MASK           0x0 /* 0:EUI; 1:MAC */
+#define REG_DEV_MAC_SEL_SHIFT          0
+#define REG_DEV_SERIAL_NUM_EN_MASK     0x1
+#define REG_DEV_SERIAL_NUM_EN_SHIFT    1
+
+#define REG_TWSI_CTRL                  0x218
+#define TWSI_CTRL_LD_OFFSET_MASK        0xFF
+#define TWSI_CTRL_LD_OFFSET_SHIFT       0
+#define TWSI_CTRL_LD_SLV_ADDR_MASK      0x7
+#define TWSI_CTRL_LD_SLV_ADDR_SHIFT     8
+#define TWSI_CTRL_SW_LDSTART            0x800
+#define TWSI_CTRL_HW_LDSTART            0x1000
+#define TWSI_CTRL_SMB_SLV_ADDR_MASK     0x7F
+#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT    15
+#define TWSI_CTRL_LD_EXIST              0x400000
+#define TWSI_CTRL_READ_FREQ_SEL_MASK    0x3
+#define TWSI_CTRL_READ_FREQ_SEL_SHIFT   23
+#define TWSI_CTRL_FREQ_SEL_100K         0
+#define TWSI_CTRL_FREQ_SEL_200K         1
+#define TWSI_CTRL_FREQ_SEL_300K         2
+#define TWSI_CTRL_FREQ_SEL_400K         3
+#define TWSI_CTRL_SMB_SLV_ADDR
+#define TWSI_CTRL_WRITE_FREQ_SEL_MASK   0x3
+#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT  24
+
+
+#define REG_PCIE_DEV_MISC_CTRL         0x21C
+#define PCIE_DEV_MISC_EXT_PIPE         0x2
+#define PCIE_DEV_MISC_RETRY_BUFDIS     0x1
+#define PCIE_DEV_MISC_SPIROM_EXIST     0x4
+#define PCIE_DEV_MISC_SERDES_ENDIAN            0x8
+#define PCIE_DEV_MISC_SERDES_SEL_DIN           0x10
+
+#define REG_PCIE_PHYMISC               0x1000
+#define PCIE_PHYMISC_FORCE_RCV_DET     0x4
+
+#define REG_TWSI_DEBUG                 0x1108
+#define TWSI_DEBUG_DEV_EXIST           0x20000000
+
+#define REG_EEPROM_CTRL                        0x12C0
+#define EEPROM_CTRL_DATA_HI_MASK       0xFFFF
+#define EEPROM_CTRL_DATA_HI_SHIFT      0
+#define EEPROM_CTRL_ADDR_MASK          0x3FF
+#define EEPROM_CTRL_ADDR_SHIFT         16
+#define EEPROM_CTRL_ACK                        0x40000000
+#define EEPROM_CTRL_RW                 0x80000000
+
+#define REG_EEPROM_DATA_LO             0x12C4
+
+#define REG_OTP_CTRL                   0x12F0
+#define OTP_CTRL_CLK_EN                        0x0002
+
+#define REG_PM_CTRL                    0x12F8
+#define PM_CTRL_SDES_EN                        0x00000001
+#define PM_CTRL_RBER_EN                        0x00000002
+#define PM_CTRL_CLK_REQ_EN             0x00000004
+#define PM_CTRL_ASPM_L1_EN             0x00000008
+#define PM_CTRL_SERDES_L1_EN           0x00000010
+#define PM_CTRL_SERDES_PLL_L1_EN       0x00000020
+#define PM_CTRL_SERDES_PD_EX_L1                0x00000040
+#define PM_CTRL_SERDES_BUDS_RX_L1_EN   0x00000080
+#define PM_CTRL_L0S_ENTRY_TIMER_MASK   0xF
+#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT  8
+#define PM_CTRL_ASPM_L0S_EN            0x00001000
+#define PM_CTRL_CLK_SWH_L1             0x00002000
+#define PM_CTRL_CLK_PWM_VER1_1         0x00004000
+#define PM_CTRL_PCIE_RECV              0x00008000
+#define PM_CTRL_L1_ENTRY_TIMER_MASK    0xF
+#define PM_CTRL_L1_ENTRY_TIMER_SHIFT   16
+#define PM_CTRL_PM_REQ_TIMER_MASK      0xF
+#define PM_CTRL_PM_REQ_TIMER_SHIFT     20
+#define PM_CTRL_LCKDET_TIMER_MASK      0x3F
+#define PM_CTRL_LCKDET_TIMER_SHIFT     24
+#define PM_CTRL_MAC_ASPM_CHK           0x40000000
+#define PM_CTRL_HOTRST                 0x80000000
+
+/* Selene Master Control Register */
+#define REG_MASTER_CTRL                        0x1400
+#define MASTER_CTRL_SOFT_RST            0x1
+#define MASTER_CTRL_TEST_MODE_MASK     0x3
+#define MASTER_CTRL_TEST_MODE_SHIFT    2
+#define MASTER_CTRL_BERT_START         0x10
+#define MASTER_CTRL_MTIMER_EN           0x100
+#define MASTER_CTRL_MANUAL_INT          0x200
+#define MASTER_CTRL_TX_ITIMER_EN       0x400
+#define MASTER_CTRL_RX_ITIMER_EN       0x800
+#define MASTER_CTRL_CLK_SEL_DIS                0x1000
+#define MASTER_CTRL_CLK_SWH_MODE       0x2000
+#define MASTER_CTRL_INT_RDCLR          0x4000
+#define MASTER_CTRL_REV_NUM_SHIFT      16
+#define MASTER_CTRL_REV_NUM_MASK       0xff
+#define MASTER_CTRL_DEV_ID_SHIFT       24
+#define MASTER_CTRL_DEV_ID_MASK                0x7f
+#define MASTER_CTRL_OTP_SEL            0x80000000
+
+/* Timer Initial Value Register */
+#define REG_MANUAL_TIMER_INIT          0x1404
+
+/* IRQ ModeratorTimer Initial Value Register */
+#define REG_IRQ_MODRT_TIMER_INIT       0x1408
+#define IRQ_MODRT_TIMER_MASK           0xffff
+#define IRQ_MODRT_TX_TIMER_SHIFT       0
+#define IRQ_MODRT_RX_TIMER_SHIFT       16
+
+#define REG_GPHY_CTRL                  0x140C
+#define GPHY_CTRL_EXT_RESET            0x1
+#define GPHY_CTRL_RTL_MODE             0x2
+#define GPHY_CTRL_LED_MODE             0x4
+#define GPHY_CTRL_ANEG_NOW             0x8
+#define GPHY_CTRL_REV_ANEG             0x10
+#define GPHY_CTRL_GATE_25M_EN          0x20
+#define GPHY_CTRL_LPW_EXIT             0x40
+#define GPHY_CTRL_PHY_IDDQ             0x80
+#define GPHY_CTRL_PHY_IDDQ_DIS         0x100
+#define GPHY_CTRL_GIGA_DIS             0x200
+#define GPHY_CTRL_HIB_EN               0x400
+#define GPHY_CTRL_HIB_PULSE            0x800
+#define GPHY_CTRL_SEL_ANA_RST          0x1000
+#define GPHY_CTRL_PHY_PLL_ON           0x2000
+#define GPHY_CTRL_PWDOWN_HW            0x4000
+#define GPHY_CTRL_PHY_PLL_BYPASS       0x8000
+
+#define GPHY_CTRL_DEFAULT (             \
+               GPHY_CTRL_SEL_ANA_RST   |\
+               GPHY_CTRL_HIB_PULSE     |\
+               GPHY_CTRL_HIB_EN)
+
+#define GPHY_CTRL_PW_WOL_DIS (          \
+               GPHY_CTRL_SEL_ANA_RST   |\
+               GPHY_CTRL_HIB_PULSE     |\
+               GPHY_CTRL_HIB_EN        |\
+               GPHY_CTRL_PWDOWN_HW     |\
+               GPHY_CTRL_PHY_IDDQ)
+
+/* Block IDLE Status Register */
+#define REG_IDLE_STATUS                0x1410
+#define IDLE_STATUS_MASK               0x00FF
+#define IDLE_STATUS_RXMAC_NO_IDLE              0x1
+#define IDLE_STATUS_TXMAC_NO_IDLE              0x2
+#define IDLE_STATUS_RXQ_NO_IDLE                0x4
+#define IDLE_STATUS_TXQ_NO_IDLE                0x8
+#define IDLE_STATUS_DMAR_NO_IDLE               0x10
+#define IDLE_STATUS_DMAW_NO_IDLE               0x20
+#define IDLE_STATUS_SMB_NO_IDLE                0x40
+#define IDLE_STATUS_CMB_NO_IDLE                0x80
+
+/* MDIO Control Register */
+#define REG_MDIO_CTRL                  0x1414
+#define MDIO_DATA_MASK                 0xffff  /* On MDIO write, the 16-bit
+                                                * control data to write to PHY
+                                                * MII management register */
+#define MDIO_DATA_SHIFT                0       /* On MDIO read, the 16-bit
+                                                * status data that was read
+                                                * from the PHY MII management register */
+#define MDIO_REG_ADDR_MASK             0x1f    /* MDIO register address */
+#define MDIO_REG_ADDR_SHIFT            16
+#define MDIO_RW                        0x200000  /* 1: read, 0: write */
+#define MDIO_SUP_PREAMBLE              0x400000  /* Suppress preamble */
+#define MDIO_START                     0x800000  /* Write 1 to initiate the MDIO
+                                                  * master. And this bit is self
+                                                  * cleared after one cycle */
+#define MDIO_CLK_SEL_SHIFT             24
+#define MDIO_CLK_25_4                  0
+#define MDIO_CLK_25_6                  2
+#define MDIO_CLK_25_8                  3
+#define MDIO_CLK_25_10                 4
+#define MDIO_CLK_25_14                 5
+#define MDIO_CLK_25_20                 6
+#define MDIO_CLK_25_28                 7
+#define MDIO_BUSY                      0x8000000
+#define MDIO_AP_EN                     0x10000000
+#define MDIO_WAIT_TIMES                10
+
+/* MII PHY Status Register */
+#define REG_PHY_STATUS                 0x1418
+#define PHY_GENERAL_STATUS_MASK                0xFFFF
+#define PHY_STATUS_RECV_ENABLE         0x0001
+#define PHY_OE_PWSP_STATUS_MASK                0x07FF
+#define PHY_OE_PWSP_STATUS_SHIFT       16
+#define PHY_STATUS_LPW_STATE           0x80000000
+/* BIST Control and Status Register0 (for the Packet Memory) */
+#define REG_BIST0_CTRL                 0x141c
+#define BIST0_NOW                      0x1
+#define BIST0_SRAM_FAIL                0x2 /* 1: The SRAM failure is
+                                            * un-repairable  because
+                                            * it has address decoder
+                                            * failure or more than 1 cell
+                                            * stuck-to-x failure */
+#define BIST0_FUSE_FLAG                0x4
+
+/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
+#define REG_BIST1_CTRL                 0x1420
+#define BIST1_NOW                      0x1
+#define BIST1_SRAM_FAIL                0x2
+#define BIST1_FUSE_FLAG                0x4
+
+/* SerDes Lock Detect Control and Status Register */
+#define REG_SERDES_LOCK                0x1424
+#define SERDES_LOCK_DETECT             0x1  /* SerDes lock detected. This signal
+                                             * comes from Analog SerDes */
+#define SERDES_LOCK_DETECT_EN          0x2  /* 1: Enable SerDes Lock detect function */
+
+/* MAC Control Register  */
+#define REG_MAC_CTRL                   0x1480
+#define MAC_CTRL_TX_EN                 0x1
+#define MAC_CTRL_RX_EN                 0x2
+#define MAC_CTRL_TX_FLOW               0x4
+#define MAC_CTRL_RX_FLOW               0x8
+#define MAC_CTRL_LOOPBACK              0x10
+#define MAC_CTRL_DUPLX                 0x20
+#define MAC_CTRL_ADD_CRC               0x40
+#define MAC_CTRL_PAD                   0x80
+#define MAC_CTRL_LENCHK                0x100
+#define MAC_CTRL_HUGE_EN               0x200
+#define MAC_CTRL_PRMLEN_SHIFT          10
+#define MAC_CTRL_PRMLEN_MASK           0xf
+#define MAC_CTRL_RMV_VLAN              0x4000
+#define MAC_CTRL_PROMIS_EN             0x8000
+#define MAC_CTRL_TX_PAUSE              0x10000
+#define MAC_CTRL_SCNT                  0x20000
+#define MAC_CTRL_SRST_TX               0x40000
+#define MAC_CTRL_TX_SIMURST            0x80000
+#define MAC_CTRL_SPEED_SHIFT           20
+#define MAC_CTRL_SPEED_MASK            0x3
+#define MAC_CTRL_DBG_TX_BKPRESURE      0x400000
+#define MAC_CTRL_TX_HUGE               0x800000
+#define MAC_CTRL_RX_CHKSUM_EN          0x1000000
+#define MAC_CTRL_MC_ALL_EN             0x2000000
+#define MAC_CTRL_BC_EN                 0x4000000
+#define MAC_CTRL_DBG                   0x8000000
+#define MAC_CTRL_SINGLE_PAUSE_EN       0x10000000
+
+/* MAC IPG/IFG Control Register  */
+#define REG_MAC_IPG_IFG                0x1484
+#define MAC_IPG_IFG_IPGT_SHIFT         0       /* Desired back to back
+                                                * inter-packet gap. The
+                                                * default is 96-bit time */
+#define MAC_IPG_IFG_IPGT_MASK          0x7f
+#define MAC_IPG_IFG_MIFG_SHIFT         8       /* Minimum number of IFG to
+                                                * enforce in between RX frames */
+#define MAC_IPG_IFG_MIFG_MASK          0xff    /* Frame gap below such IFP is dropped */
+#define MAC_IPG_IFG_IPGR1_SHIFT        16      /* 64bit Carrier-Sense window */
+#define MAC_IPG_IFG_IPGR1_MASK         0x7f
+#define MAC_IPG_IFG_IPGR2_SHIFT        24      /* 96-bit IPG window */
+#define MAC_IPG_IFG_IPGR2_MASK         0x7f
+
+/* MAC STATION ADDRESS  */
+#define REG_MAC_STA_ADDR               0x1488
+
+/* Hash table for multicast address */
+#define REG_RX_HASH_TABLE              0x1490
+
+/* MAC Half-Duplex Control Register */
+#define REG_MAC_HALF_DUPLX_CTRL        0x1498
+#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT  0      /* Collision Window */
+#define MAC_HALF_DUPLX_CTRL_LCOL_MASK   0x3ff
+#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
+#define MAC_HALF_DUPLX_CTRL_RETRY_MASK  0xf
+#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN  0x10000
+#define MAC_HALF_DUPLX_CTRL_NO_BACK_C   0x20000
+#define MAC_HALF_DUPLX_CTRL_NO_BACK_P   0x40000 /* No back-off on backpressure,
+                                                * immediately start the
+                                                * transmission after back pressure */
+#define MAC_HALF_DUPLX_CTRL_ABEBE        0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
+#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT  20      /* Maximum binary exponential number */
+#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK   0xf
+#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24      /* IPG to start JAM for collision based flow control in half-duplex */
+#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK  0xf     /* mode. In unit of 8-bit time */
+
+/* Maximum Frame Length Control Register   */
+#define REG_MTU                        0x149c
+
+/* Wake-On-Lan control register */
+#define REG_WOL_CTRL                   0x14a0
+#define WOL_PATTERN_EN                 0x00000001
+#define WOL_PATTERN_PME_EN              0x00000002
+#define WOL_MAGIC_EN                    0x00000004
+#define WOL_MAGIC_PME_EN                0x00000008
+#define WOL_LINK_CHG_EN                 0x00000010
+#define WOL_LINK_CHG_PME_EN             0x00000020
+#define WOL_PATTERN_ST                  0x00000100
+#define WOL_MAGIC_ST                    0x00000200
+#define WOL_LINKCHG_ST                  0x00000400
+#define WOL_CLK_SWITCH_EN               0x00008000
+#define WOL_PT0_EN                      0x00010000
+#define WOL_PT1_EN                      0x00020000
+#define WOL_PT2_EN                      0x00040000
+#define WOL_PT3_EN                      0x00080000
+#define WOL_PT4_EN                      0x00100000
+#define WOL_PT5_EN                      0x00200000
+#define WOL_PT6_EN                      0x00400000
+
+/* WOL Length ( 2 DWORD ) */
+#define REG_WOL_PATTERN_LEN            0x14a4
+#define WOL_PT_LEN_MASK                 0x7f
+#define WOL_PT0_LEN_SHIFT               0
+#define WOL_PT1_LEN_SHIFT               8
+#define WOL_PT2_LEN_SHIFT               16
+#define WOL_PT3_LEN_SHIFT               24
+#define WOL_PT4_LEN_SHIFT               0
+#define WOL_PT5_LEN_SHIFT               8
+#define WOL_PT6_LEN_SHIFT               16
+
+/* Internal SRAM Partition Register */
+#define RFDX_HEAD_ADDR_MASK            0x03FF
+#define RFDX_HARD_ADDR_SHIFT           0
+#define RFDX_TAIL_ADDR_MASK            0x03FF
+#define RFDX_TAIL_ADDR_SHIFT            16
+
+#define REG_SRAM_RFD0_INFO             0x1500
+#define REG_SRAM_RFD1_INFO             0x1504
+#define REG_SRAM_RFD2_INFO             0x1508
+#define        REG_SRAM_RFD3_INFO              0x150C
+
+#define REG_RFD_NIC_LEN                        0x1510 /* In 8-bytes */
+#define RFD_NIC_LEN_MASK               0x03FF
+
+#define REG_SRAM_TRD_ADDR              0x1518
+#define TPD_HEAD_ADDR_MASK             0x03FF
+#define TPD_HEAD_ADDR_SHIFT            0
+#define TPD_TAIL_ADDR_MASK             0x03FF
+#define TPD_TAIL_ADDR_SHIFT            16
+
+#define REG_SRAM_TRD_LEN               0x151C /* In 8-bytes */
+#define TPD_NIC_LEN_MASK               0x03FF
+
+#define REG_SRAM_RXF_ADDR              0x1520
+#define REG_SRAM_RXF_LEN               0x1524
+#define REG_SRAM_TXF_ADDR              0x1528
+#define REG_SRAM_TXF_LEN               0x152C
+#define REG_SRAM_TCPH_ADDR             0x1530
+#define REG_SRAM_PKTH_ADDR             0x1532
+
+/*
+ * Load Ptr Register
+ * Software sets this bit after the initialization of the head and tail */
+#define REG_LOAD_PTR                   0x1534
+
+/*
+ * addresses of all descriptors, as well as the following descriptor
+ * control register, which triggers each function block to load the head
+ * pointer to prepare for the operation. This bit is then self-cleared
+ * after one cycle.
+ */
+#define REG_RX_BASE_ADDR_HI            0x1540
+#define REG_TX_BASE_ADDR_HI            0x1544
+#define REG_SMB_BASE_ADDR_HI           0x1548
+#define REG_SMB_BASE_ADDR_LO           0x154C
+#define REG_RFD0_HEAD_ADDR_LO          0x1550
+#define REG_RFD1_HEAD_ADDR_LO          0x1554
+#define REG_RFD2_HEAD_ADDR_LO          0x1558
+#define REG_RFD3_HEAD_ADDR_LO          0x155C
+#define REG_RFD_RING_SIZE              0x1560
+#define RFD_RING_SIZE_MASK             0x0FFF
+#define REG_RX_BUF_SIZE                        0x1564
+#define RX_BUF_SIZE_MASK               0xFFFF
+#define REG_RRD0_HEAD_ADDR_LO          0x1568
+#define REG_RRD1_HEAD_ADDR_LO          0x156C
+#define REG_RRD2_HEAD_ADDR_LO          0x1570
+#define REG_RRD3_HEAD_ADDR_LO          0x1574
+#define REG_RRD_RING_SIZE              0x1578
+#define RRD_RING_SIZE_MASK             0x0FFF
+#define REG_HTPD_HEAD_ADDR_LO          0x157C
+#define REG_NTPD_HEAD_ADDR_LO          0x1580
+#define REG_TPD_RING_SIZE              0x1584
+#define TPD_RING_SIZE_MASK             0xFFFF
+#define REG_CMB_BASE_ADDR_LO           0x1588
+
+/* RSS about */
+#define REG_RSS_KEY0                    0x14B0
+#define REG_RSS_KEY1                    0x14B4
+#define REG_RSS_KEY2                    0x14B8
+#define REG_RSS_KEY3                    0x14BC
+#define REG_RSS_KEY4                    0x14C0
+#define REG_RSS_KEY5                    0x14C4
+#define REG_RSS_KEY6                    0x14C8
+#define REG_RSS_KEY7                    0x14CC
+#define REG_RSS_KEY8                    0x14D0
+#define REG_RSS_KEY9                    0x14D4
+#define REG_IDT_TABLE0                 0x14E0
+#define REG_IDT_TABLE1                  0x14E4
+#define REG_IDT_TABLE2                  0x14E8
+#define REG_IDT_TABLE3                  0x14EC
+#define REG_IDT_TABLE4                  0x14F0
+#define REG_IDT_TABLE5                  0x14F4
+#define REG_IDT_TABLE6                  0x14F8
+#define REG_IDT_TABLE7                  0x14FC
+#define REG_IDT_TABLE                   REG_IDT_TABLE0
+#define REG_RSS_HASH_VALUE              0x15B0
+#define REG_RSS_HASH_FLAG               0x15B4
+#define REG_BASE_CPU_NUMBER             0x15B8
+
+/* TXQ Control Register */
+#define REG_TXQ_CTRL                   0x1590
+#define        TXQ_NUM_TPD_BURST_MASK          0xF
+#define TXQ_NUM_TPD_BURST_SHIFT        0
+#define TXQ_CTRL_IP_OPTION_EN          0x10
+#define TXQ_CTRL_EN                     0x20
+#define TXQ_CTRL_ENH_MODE               0x40
+#define TXQ_CTRL_LS_8023_EN            0x80
+#define TXQ_TXF_BURST_NUM_SHIFT        16
+#define TXQ_TXF_BURST_NUM_MASK         0xFFFF
+
+/* Jumbo packet Threshold for task offload */
+#define REG_TX_TSO_OFFLOAD_THRESH      0x1594 /* In 8-bytes */
+#define TX_TSO_OFFLOAD_THRESH_MASK     0x07FF
+
+#define        REG_TXF_WATER_MARK              0x1598 /* In 8-bytes */
+#define TXF_WATER_MARK_MASK            0x0FFF
+#define TXF_LOW_WATER_MARK_SHIFT       0
+#define TXF_HIGH_WATER_MARK_SHIFT      16
+#define TXQ_CTRL_BURST_MODE_EN         0x80000000
+
+#define REG_THRUPUT_MON_CTRL           0x159C
+#define THRUPUT_MON_RATE_MASK          0x3
+#define THRUPUT_MON_RATE_SHIFT         0
+#define THRUPUT_MON_EN                 0x80
+
+/* RXQ Control Register */
+#define REG_RXQ_CTRL                   0x15A0
+#define ASPM_THRUPUT_LIMIT_MASK                0x3
+#define ASPM_THRUPUT_LIMIT_SHIFT       0
+#define ASPM_THRUPUT_LIMIT_NO          0x00
+#define ASPM_THRUPUT_LIMIT_1M          0x01
+#define ASPM_THRUPUT_LIMIT_10M         0x02
+#define ASPM_THRUPUT_LIMIT_100M                0x04
+#define RXQ1_CTRL_EN                   0x10
+#define RXQ2_CTRL_EN                   0x20
+#define RXQ3_CTRL_EN                   0x40
+#define IPV6_CHKSUM_CTRL_EN            0x80
+#define RSS_HASH_BITS_MASK             0x00FF
+#define RSS_HASH_BITS_SHIFT            8
+#define RSS_HASH_IPV4                  0x10000
+#define RSS_HASH_IPV4_TCP              0x20000
+#define RSS_HASH_IPV6                  0x40000
+#define RSS_HASH_IPV6_TCP              0x80000
+#define RXQ_RFD_BURST_NUM_MASK         0x003F
+#define RXQ_RFD_BURST_NUM_SHIFT                20
+#define RSS_MODE_MASK                  0x0003
+#define RSS_MODE_SHIFT                 26
+#define RSS_NIP_QUEUE_SEL_MASK         0x1
+#define RSS_NIP_QUEUE_SEL_SHIFT                28
+#define RRS_HASH_CTRL_EN               0x20000000
+#define RX_CUT_THRU_EN                 0x40000000
+#define RXQ_CTRL_EN                    0x80000000
+
+#define REG_RFD_FREE_THRESH            0x15A4
+#define RFD_FREE_THRESH_MASK           0x003F
+#define RFD_FREE_HI_THRESH_SHIFT       0
+#define RFD_FREE_LO_THRESH_SHIFT       6
+
+/* RXF flow control register */
+#define REG_RXQ_RXF_PAUSE_THRESH       0x15A8
+#define RXQ_RXF_PAUSE_TH_HI_SHIFT       0
+#define RXQ_RXF_PAUSE_TH_HI_MASK        0x0FFF
+#define RXQ_RXF_PAUSE_TH_LO_SHIFT       16
+#define RXQ_RXF_PAUSE_TH_LO_MASK        0x0FFF
+
+#define REG_RXD_DMA_CTRL               0x15AC
+#define RXD_DMA_THRESH_MASK            0x0FFF  /* In 8-bytes */
+#define RXD_DMA_THRESH_SHIFT           0
+#define RXD_DMA_DOWN_TIMER_MASK                0xFFFF
+#define RXD_DMA_DOWN_TIMER_SHIFT       16
+
+/* DMA Engine Control Register */
+#define REG_DMA_CTRL                   0x15C0
+#define DMA_CTRL_DMAR_IN_ORDER          0x1
+#define DMA_CTRL_DMAR_ENH_ORDER         0x2
+#define DMA_CTRL_DMAR_OUT_ORDER         0x4
+#define DMA_CTRL_RCB_VALUE              0x8
+#define DMA_CTRL_DMAR_BURST_LEN_MASK    0x0007
+#define DMA_CTRL_DMAR_BURST_LEN_SHIFT   4
+#define DMA_CTRL_DMAW_BURST_LEN_MASK    0x0007
+#define DMA_CTRL_DMAW_BURST_LEN_SHIFT   7
+#define DMA_CTRL_DMAR_REQ_PRI           0x400
+#define DMA_CTRL_DMAR_DLY_CNT_MASK      0x001F
+#define DMA_CTRL_DMAR_DLY_CNT_SHIFT     11
+#define DMA_CTRL_DMAW_DLY_CNT_MASK      0x000F
+#define DMA_CTRL_DMAW_DLY_CNT_SHIFT     16
+#define DMA_CTRL_CMB_EN                0x100000
+#define DMA_CTRL_SMB_EN                        0x200000
+#define DMA_CTRL_CMB_NOW               0x400000
+#define MAC_CTRL_SMB_DIS               0x1000000
+#define DMA_CTRL_SMB_NOW               0x80000000
+
+/* CMB/SMB Control Register */
+#define REG_SMB_STAT_TIMER             0x15C4  /* 2us resolution */
+#define SMB_STAT_TIMER_MASK            0xFFFFFF
+#define REG_CMB_TPD_THRESH             0x15C8
+#define CMB_TPD_THRESH_MASK            0xFFFF
+#define REG_CMB_TX_TIMER               0x15CC  /* 2us resolution */
+#define CMB_TX_TIMER_MASK              0xFFFF
+
+/* Mail box */
+#define MB_RFDX_PROD_IDX_MASK          0xFFFF
+#define REG_MB_RFD0_PROD_IDX           0x15E0
+#define REG_MB_RFD1_PROD_IDX           0x15E4
+#define REG_MB_RFD2_PROD_IDX           0x15E8
+#define REG_MB_RFD3_PROD_IDX           0x15EC
+
+#define MB_PRIO_PROD_IDX_MASK          0xFFFF
+#define REG_MB_PRIO_PROD_IDX           0x15F0
+#define MB_HTPD_PROD_IDX_SHIFT         0
+#define MB_NTPD_PROD_IDX_SHIFT         16
+
+#define MB_PRIO_CONS_IDX_MASK          0xFFFF
+#define REG_MB_PRIO_CONS_IDX           0x15F4
+#define MB_HTPD_CONS_IDX_SHIFT         0
+#define MB_NTPD_CONS_IDX_SHIFT         16
+
+#define REG_MB_RFD01_CONS_IDX          0x15F8
+#define MB_RFD0_CONS_IDX_MASK          0x0000FFFF
+#define MB_RFD1_CONS_IDX_MASK          0xFFFF0000
+#define REG_MB_RFD23_CONS_IDX          0x15FC
+#define MB_RFD2_CONS_IDX_MASK          0x0000FFFF
+#define MB_RFD3_CONS_IDX_MASK          0xFFFF0000
+
+/* Interrupt Status Register */
+#define REG_ISR                        0x1600
+#define ISR_SMB                                0x00000001
+#define ISR_TIMER                      0x00000002
+/*
+ * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
+ * in Table 51 Selene Master Control Register (Offset 0x1400).
+ */
+#define ISR_MANUAL                     0x00000004
+#define ISR_HW_RXF_OV                          0x00000008 /* RXF overflow interrupt */
+#define ISR_RFD0_UR                    0x00000010 /* RFD0 under run */
+#define ISR_RFD1_UR                    0x00000020
+#define ISR_RFD2_UR                    0x00000040
+#define ISR_RFD3_UR                    0x00000080
+#define ISR_TXF_UR                     0x00000100
+#define ISR_DMAR_TO_RST                        0x00000200
+#define ISR_DMAW_TO_RST                        0x00000400
+#define ISR_TX_CREDIT                  0x00000800
+#define ISR_GPHY                       0x00001000
+/* GPHY low power state interrupt */
+#define ISR_GPHY_LPW                           0x00002000
+#define ISR_TXQ_TO_RST                 0x00004000
+#define ISR_TX_PKT                     0x00008000
+#define ISR_RX_PKT_0                   0x00010000
+#define ISR_RX_PKT_1                   0x00020000
+#define ISR_RX_PKT_2                   0x00040000
+#define ISR_RX_PKT_3                   0x00080000
+#define ISR_MAC_RX                     0x00100000
+#define ISR_MAC_TX                     0x00200000
+#define ISR_UR_DETECTED                        0x00400000
+#define ISR_FERR_DETECTED              0x00800000
+#define ISR_NFERR_DETECTED             0x01000000
+#define ISR_CERR_DETECTED              0x02000000
+#define ISR_PHY_LINKDOWN               0x04000000
+#define ISR_DIS_INT                    0x80000000
+
+/* Interrupt Mask Register */
+#define REG_IMR                                0x1604
+
+#define IMR_NORMAL_MASK                (\
+               ISR_MANUAL      |\
+               ISR_HW_RXF_OV   |\
+               ISR_RFD0_UR     |\
+               ISR_TXF_UR      |\
+               ISR_DMAR_TO_RST |\
+               ISR_TXQ_TO_RST  |\
+               ISR_DMAW_TO_RST |\
+               ISR_GPHY        |\
+               ISR_TX_PKT      |\
+               ISR_RX_PKT_0    |\
+               ISR_GPHY_LPW    |\
+               ISR_PHY_LINKDOWN)
+
+#define ISR_RX_PKT     (\
+       ISR_RX_PKT_0    |\
+       ISR_RX_PKT_1    |\
+       ISR_RX_PKT_2    |\
+       ISR_RX_PKT_3)
+
+#define ISR_OVER       (\
+       ISR_RFD0_UR     |\
+       ISR_RFD1_UR     |\
+       ISR_RFD2_UR     |\
+       ISR_RFD3_UR     |\
+       ISR_HW_RXF_OV   |\
+       ISR_TXF_UR)
+
+#define ISR_ERROR      (\
+       ISR_DMAR_TO_RST |\
+       ISR_TXQ_TO_RST  |\
+       ISR_DMAW_TO_RST |\
+       ISR_PHY_LINKDOWN)
+
+#define REG_INT_RETRIG_TIMER           0x1608
+#define INT_RETRIG_TIMER_MASK          0xFFFF
+
+#define REG_HDS_CTRL                   0x160C
+#define HDS_CTRL_EN                    0x0001
+#define HDS_CTRL_BACKFILLSIZE_SHIFT    8
+#define HDS_CTRL_BACKFILLSIZE_MASK     0x0FFF
+#define HDS_CTRL_MAX_HDRSIZE_SHIFT     20
+#define HDS_CTRL_MAC_HDRSIZE_MASK      0x0FFF
+
+#define REG_MAC_RX_STATUS_BIN          0x1700
+#define REG_MAC_RX_STATUS_END          0x175c
+#define REG_MAC_TX_STATUS_BIN          0x1760
+#define REG_MAC_TX_STATUS_END          0x17c0
+
+/* DEBUG ADDR */
+#define REG_DEBUG_DATA0                0x1900
+#define REG_DEBUG_DATA1                0x1904
+
+/* PHY Control Register */
+#define MII_BMCR                       0x00
+#define BMCR_SPEED_SELECT_MSB          0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define BMCR_COLL_TEST_ENABLE          0x0080  /* Collision test enable */
+#define BMCR_FULL_DUPLEX               0x0100  /* FDX =1, half duplex =0 */
+#define BMCR_RESTART_AUTO_NEG          0x0200  /* Restart auto negotiation */
+#define BMCR_ISOLATE                   0x0400  /* Isolate PHY from MII */
+#define BMCR_POWER_DOWN                        0x0800  /* Power down */
+#define BMCR_AUTO_NEG_EN               0x1000  /* Auto Neg Enable */
+#define BMCR_SPEED_SELECT_LSB          0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define BMCR_LOOPBACK                  0x4000  /* 0 = normal, 1 = loopback */
+#define BMCR_RESET                     0x8000  /* 0 = normal, 1 = PHY reset */
+#define BMCR_SPEED_MASK                        0x2040
+#define BMCR_SPEED_1000                        0x0040
+#define BMCR_SPEED_100                 0x2000
+#define BMCR_SPEED_10                  0x0000
+
+/* PHY Status Register */
+#define MII_BMSR                       0x01
+#define BMMSR_EXTENDED_CAPS            0x0001  /* Extended register capabilities */
+#define BMSR_JABBER_DETECT             0x0002  /* Jabber Detected */
+#define BMSR_LINK_STATUS               0x0004  /* Link Status 1 = link */
+#define BMSR_AUTONEG_CAPS              0x0008  /* Auto Neg Capable */
+#define BMSR_REMOTE_FAULT              0x0010  /* Remote Fault Detect */
+#define BMSR_AUTONEG_COMPLETE          0x0020  /* Auto Neg Complete */
+#define BMSR_PREAMBLE_SUPPRESS         0x0040  /* Preamble may be suppressed */
+#define BMSR_EXTENDED_STATUS           0x0100  /* Ext. status info in Reg 0x0F */
+#define BMSR_100T2_HD_CAPS             0x0200  /* 100T2 Half Duplex Capable */
+#define BMSR_100T2_FD_CAPS             0x0400  /* 100T2 Full Duplex Capable */
+#define BMSR_10T_HD_CAPS               0x0800  /* 10T   Half Duplex Capable */
+#define BMSR_10T_FD_CAPS               0x1000  /* 10T   Full Duplex Capable */
+#define BMSR_100X_HD_CAPS              0x2000  /* 100X  Half Duplex Capable */
+#define BMMII_SR_100X_FD_CAPS          0x4000  /* 100X  Full Duplex Capable */
+#define BMMII_SR_100T4_CAPS            0x8000  /* 100T4 Capable */
+
+#define MII_PHYSID1                    0x02
+#define MII_PHYSID2                    0x03
+
+/* Autoneg Advertisement Register */
+#define MII_ADVERTISE                  0x04
+#define ADVERTISE_SPEED_MASK           0x01E0
+#define ADVERTISE_DEFAULT_CAP          0x0DE0
+
+/* 1000BASE-T Control Register */
+#define MII_GIGA_CR                    0x09
+#define GIGA_CR_1000T_REPEATER_DTE     0x0400  /* 1=Repeater/switch device port 0=DTE device */
+
+#define GIGA_CR_1000T_MS_VALUE         0x0800  /* 1=Configure PHY as Master 0=Configure PHY as Slave */
+#define GIGA_CR_1000T_MS_ENABLE                0x1000  /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
+#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000  /* Normal Operation */
+#define GIGA_CR_1000T_TEST_MODE_1      0x2000  /* Transmit Waveform test */
+#define GIGA_CR_1000T_TEST_MODE_2      0x4000  /* Master Transmit Jitter test */
+#define GIGA_CR_1000T_TEST_MODE_3      0x6000  /* Slave Transmit Jitter test */
+#define GIGA_CR_1000T_TEST_MODE_4      0x8000  /* Transmitter Distortion test */
+#define GIGA_CR_1000T_SPEED_MASK       0x0300
+#define GIGA_CR_1000T_DEFAULT_CAP      0x0300
+
+/* PHY Specific Status Register */
+#define MII_GIGA_PSSR                  0x11
+#define GIGA_PSSR_SPD_DPLX_RESOLVED    0x0800  /* 1=Speed & Duplex resolved */
+#define GIGA_PSSR_DPLX                 0x2000  /* 1=Duplex 0=Half Duplex */
+#define GIGA_PSSR_SPEED                        0xC000  /* Speed, bits 14:15 */
+#define GIGA_PSSR_10MBS                        0x0000  /* 00=10Mbs */
+#define GIGA_PSSR_100MBS               0x4000  /* 01=100Mbs */
+#define GIGA_PSSR_1000MBS              0x8000  /* 10=1000Mbs */
+
+/* PHY Interrupt Enable Register */
+#define MII_IER                                0x12
+#define IER_LINK_UP                    0x0400
+#define IER_LINK_DOWN                  0x0800
+
+/* PHY Interrupt Status Register */
+#define MII_ISR                                0x13
+#define ISR_LINK_UP                    0x0400
+#define ISR_LINK_DOWN                  0x0800
+
+/* Cable-Detect-Test Control Register */
+#define MII_CDTC                       0x16
+#define CDTC_EN_OFF                    0   /* sc */
+#define CDTC_EN_BITS                   1
+#define CDTC_PAIR_OFF                  8
+#define CDTC_PAIR_BIT                  2
+
+/* Cable-Detect-Test Status Register */
+#define MII_CDTS                       0x1C
+#define CDTS_STATUS_OFF                        8
+#define CDTS_STATUS_BITS               2
+#define CDTS_STATUS_NORMAL             0
+#define CDTS_STATUS_SHORT              1
+#define CDTS_STATUS_OPEN               2
+#define CDTS_STATUS_INVALID            3
+
+#define MII_DBG_ADDR                   0x1D
+#define MII_DBG_DATA                   0x1E
+
+#define MII_ANA_CTRL_0                 0x0
+#define ANA_RESTART_CAL                        0x0001
+#define ANA_MANUL_SWICH_ON_SHIFT       0x1
+#define ANA_MANUL_SWICH_ON_MASK                0xF
+#define ANA_MAN_ENABLE                 0x0020
+#define ANA_SEL_HSP                    0x0040
+#define ANA_EN_HB                      0x0080
+#define ANA_EN_HBIAS                   0x0100
+#define ANA_OEN_125M                   0x0200
+#define ANA_EN_LCKDT                   0x0400
+#define ANA_LCKDT_PHY                  0x0800
+#define ANA_AFE_MODE                   0x1000
+#define ANA_VCO_SLOW                   0x2000
+#define ANA_VCO_FAST                   0x4000
+#define ANA_SEL_CLK125M_DSP            0x8000
+
+#define MII_ANA_CTRL_4                 0x4
+#define ANA_IECHO_ADJ_MASK             0xF
+#define ANA_IECHO_ADJ_3_SHIFT          0
+#define ANA_IECHO_ADJ_2_SHIFT          4
+#define ANA_IECHO_ADJ_1_SHIFT          8
+#define ANA_IECHO_ADJ_0_SHIFT          12
+
+#define MII_ANA_CTRL_5                 0x5
+#define ANA_SERDES_CDR_BW_SHIFT                0
+#define ANA_SERDES_CDR_BW_MASK         0x3
+#define ANA_MS_PAD_DBG                 0x0004
+#define ANA_SPEEDUP_DBG                        0x0008
+#define ANA_SERDES_TH_LOS_SHIFT                4
+#define ANA_SERDES_TH_LOS_MASK         0x3
+#define ANA_SERDES_EN_DEEM             0x0040
+#define ANA_SERDES_TXELECIDLE          0x0080
+#define ANA_SERDES_BEACON              0x0100
+#define ANA_SERDES_HALFTXDR            0x0200
+#define ANA_SERDES_SEL_HSP             0x0400
+#define ANA_SERDES_EN_PLL              0x0800
+#define ANA_SERDES_EN                  0x1000
+#define ANA_SERDES_EN_LCKDT            0x2000
+
+#define MII_ANA_CTRL_11                        0xB
+#define ANA_PS_HIB_EN                  0x8000
+
+#define MII_ANA_CTRL_18                        0x12
+#define ANA_TEST_MODE_10BT_01SHIFT     0
+#define ANA_TEST_MODE_10BT_01MASK      0x3
+#define ANA_LOOP_SEL_10BT              0x0004
+#define ANA_RGMII_MODE_SW              0x0008
+#define ANA_EN_LONGECABLE              0x0010
+#define ANA_TEST_MODE_10BT_2           0x0020
+#define ANA_EN_10BT_IDLE               0x0400
+#define ANA_EN_MASK_TB                 0x0800
+#define ANA_TRIGGER_SEL_TIMER_SHIFT    12
+#define ANA_TRIGGER_SEL_TIMER_MASK     0x3
+#define ANA_INTERVAL_SEL_TIMER_SHIFT   14
+#define ANA_INTERVAL_SEL_TIMER_MASK    0x3
+
+#define MII_ANA_CTRL_41                        0x29
+#define ANA_TOP_PS_EN                  0x8000
+
+#define MII_ANA_CTRL_54                        0x36
+#define ANA_LONG_CABLE_TH_100_SHIFT    0
+#define ANA_LONG_CABLE_TH_100_MASK     0x3F
+#define ANA_DESERVED                   0x0040
+#define ANA_EN_LIT_CH                  0x0080
+#define ANA_SHORT_CABLE_TH_100_SHIFT   8
+#define ANA_SHORT_CABLE_TH_100_MASK    0x3F
+#define ANA_BP_BAD_LINK_ACCUM          0x4000
+#define ANA_BP_SMALL_BW                        0x8000
+
+#endif /*_ATL1C_HW_H_*/
diff --git a/drivers/net/atl1c/atl1c_main.c b/drivers/net/atl1c/atl1c_main.c
new file mode 100644 (file)
index 0000000..deb7b53
--- /dev/null
@@ -0,0 +1,2797 @@
+/*
+ * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
+ *
+ * Derived from Intel e1000 driver
+ * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#include "atl1c.h"
+
+#define ATL1C_DRV_VERSION "1.0.0.1-NAPI"
+char atl1c_driver_name[] = "atl1c";
+char atl1c_driver_version[] = ATL1C_DRV_VERSION;
+#define PCI_DEVICE_ID_ATTANSIC_L2C      0x1062
+#define PCI_DEVICE_ID_ATTANSIC_L1C      0x1063
+/*
+ * atl1c_pci_tbl - PCI Device ID Table
+ *
+ * Wildcard entries (PCI_ANY_ID) should come last
+ * Last entry must be all 0s
+ *
+ * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
+ *   Class, Class Mask, private data (not used) }
+ */
+static struct pci_device_id atl1c_pci_tbl[] = {
+       {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
+       {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
+       /* required last entry */
+       { 0 }
+};
+MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
+
+MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>");
+MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(ATL1C_DRV_VERSION);
+
+static int atl1c_stop_mac(struct atl1c_hw *hw);
+static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
+static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
+static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
+static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
+static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
+static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
+                  int *work_done, int work_to_do);
+
+static const u16 atl1c_pay_load_size[] = {
+       128, 256, 512, 1024, 2048, 4096,
+};
+
+static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] =
+{
+       REG_MB_RFD0_PROD_IDX,
+       REG_MB_RFD1_PROD_IDX,
+       REG_MB_RFD2_PROD_IDX,
+       REG_MB_RFD3_PROD_IDX
+};
+
+static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
+{
+       REG_RFD0_HEAD_ADDR_LO,
+       REG_RFD1_HEAD_ADDR_LO,
+       REG_RFD2_HEAD_ADDR_LO,
+       REG_RFD3_HEAD_ADDR_LO
+};
+
+static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
+{
+       REG_RRD0_HEAD_ADDR_LO,
+       REG_RRD1_HEAD_ADDR_LO,
+       REG_RRD2_HEAD_ADDR_LO,
+       REG_RRD3_HEAD_ADDR_LO
+};
+
+static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
+       NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
+
+/*
+ * atl1c_init_pcie - init PCIE module
+ */
+static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
+{
+       u32 data;
+       u32 pci_cmd;
+       struct pci_dev *pdev = hw->adapter->pdev;
+
+       AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
+       pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
+       pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+               PCI_COMMAND_IO);
+       AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
+
+       /*
+        * Clear any PowerSaveing Settings
+        */
+       pci_enable_wake(pdev, PCI_D3hot, 0);
+       pci_enable_wake(pdev, PCI_D3cold, 0);
+
+       /*
+        * Mask some pcie error bits
+        */
+       AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
+       data &= ~PCIE_UC_SERVRITY_DLP;
+       data &= ~PCIE_UC_SERVRITY_FCP;
+       AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
+
+       if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
+               atl1c_disable_l0s_l1(hw);
+       if (flag & ATL1C_PCIE_PHY_RESET)
+               AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
+       else
+               AT_WRITE_REG(hw, REG_GPHY_CTRL,
+                       GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
+
+       msleep(1);
+}
+
+/*
+ * atl1c_irq_enable - Enable default interrupt generation settings
+ * @adapter: board private structure
+ */
+static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
+{
+       if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
+               AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
+               AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
+               AT_WRITE_FLUSH(&adapter->hw);
+       }
+}
+
+/*
+ * atl1c_irq_disable - Mask off interrupt generation on the NIC
+ * @adapter: board private structure
+ */
+static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
+{
+       atomic_inc(&adapter->irq_sem);
+       AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
+       AT_WRITE_FLUSH(&adapter->hw);
+       synchronize_irq(adapter->pdev->irq);
+}
+
+/*
+ * atl1c_irq_reset - reset interrupt confiure on the NIC
+ * @adapter: board private structure
+ */
+static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
+{
+       atomic_set(&adapter->irq_sem, 1);
+       atl1c_irq_enable(adapter);
+}
+
+/*
+ * atl1c_phy_config - Timer Call-back
+ * @data: pointer to netdev cast into an unsigned long
+ */
+static void atl1c_phy_config(unsigned long data)
+{
+       struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
+       struct atl1c_hw *hw = &adapter->hw;
+       unsigned long flags;
+
+       spin_lock_irqsave(&adapter->mdio_lock, flags);
+       atl1c_restart_autoneg(hw);
+       spin_unlock_irqrestore(&adapter->mdio_lock, flags);
+}
+
+void atl1c_reinit_locked(struct atl1c_adapter *adapter)
+{
+
+       WARN_ON(in_interrupt());
+       atl1c_down(adapter);
+       atl1c_up(adapter);
+       clear_bit(__AT_RESETTING, &adapter->flags);
+}
+
+static void atl1c_reset_task(struct work_struct *work)
+{
+       struct atl1c_adapter *adapter;
+       struct net_device *netdev;
+
+       adapter = container_of(work, struct atl1c_adapter, reset_task);
+       netdev = adapter->netdev;
+
+       netif_device_detach(netdev);
+       atl1c_down(adapter);
+       atl1c_up(adapter);
+       netif_device_attach(netdev);
+}
+
+static void atl1c_check_link_status(struct atl1c_adapter *adapter)
+{
+       struct atl1c_hw *hw = &adapter->hw;
+       struct net_device *netdev = adapter->netdev;
+       struct pci_dev    *pdev   = adapter->pdev;
+       int err;
+       unsigned long flags;
+       u16 speed, duplex, phy_data;
+
+       spin_lock_irqsave(&adapter->mdio_lock, flags);
+       /* MII_BMSR must read twise */
+       atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
+       atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
+       spin_unlock_irqrestore(&adapter->mdio_lock, flags);
+
+       if ((phy_data & BMSR_LSTATUS) == 0) {
+               /* link down */
+               if (netif_carrier_ok(netdev)) {
+                       hw->hibernate = true;
+                       atl1c_set_aspm(hw, false);
+                       if (atl1c_stop_mac(hw) != 0)
+                               if (netif_msg_hw(adapter))
+                                       dev_warn(&pdev->dev,
+                                               "stop mac failed\n");
+               }
+               netif_carrier_off(netdev);
+       } else {
+               /* Link Up */
+               hw->hibernate = false;
+               spin_lock_irqsave(&adapter->mdio_lock, flags);
+               err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
+               spin_unlock_irqrestore(&adapter->mdio_lock, flags);
+               if (unlikely(err))
+                       return;
+               /* link result is our setting */
+               if (adapter->link_speed != speed ||
+                   adapter->link_duplex != duplex) {
+                       adapter->link_speed  = speed;
+                       adapter->link_duplex = duplex;
+                       atl1c_enable_tx_ctrl(hw);
+                       atl1c_enable_rx_ctrl(hw);
+                       atl1c_setup_mac_ctrl(adapter);
+                       atl1c_set_aspm(hw, true);
+                       if (netif_msg_link(adapter))
+                               dev_info(&pdev->dev,
+                                       "%s: %s NIC Link is Up<%d Mbps %s>\n",
+                                       atl1c_driver_name, netdev->name,
+                                       adapter->link_speed,
+                                       adapter->link_duplex == FULL_DUPLEX ?
+                                       "Full Duplex" : "Half Duplex");
+               }
+               if (!netif_carrier_ok(netdev))
+                       netif_carrier_on(netdev);
+       }
+}
+
+/*
+ * atl1c_link_chg_task - deal with link change event Out of interrupt context
+ * @netdev: network interface device structure
+ */
+static void atl1c_link_chg_task(struct work_struct *work)
+{
+       struct atl1c_adapter *adapter;
+
+       adapter = container_of(work, struct atl1c_adapter, link_chg_task);
+       atl1c_check_link_status(adapter);
+}
+
+static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
+{
+       struct net_device *netdev = adapter->netdev;
+       struct pci_dev    *pdev   = adapter->pdev;
+       u16 phy_data;
+       u16 link_up;
+
+       spin_lock(&adapter->mdio_lock);
+       atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
+       atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
+       spin_unlock(&adapter->mdio_lock);
+       link_up = phy_data & BMSR_LSTATUS;
+       /* notify upper layer link down ASAP */
+       if (!link_up) {
+               if (netif_carrier_ok(netdev)) {
+                       /* old link state: Up */
+                       netif_carrier_off(netdev);
+                       if (netif_msg_link(adapter))
+                               dev_info(&pdev->dev,
+                                       "%s: %s NIC Link is Down\n",
+                                       atl1c_driver_name, netdev->name);
+                       adapter->link_speed = SPEED_0;
+               }
+       }
+       schedule_work(&adapter->link_chg_task);
+}
+
+static void atl1c_del_timer(struct atl1c_adapter *adapter)
+{
+       del_timer_sync(&adapter->phy_config_timer);
+}
+
+static void atl1c_cancel_work(struct atl1c_adapter *adapter)
+{
+       cancel_work_sync(&adapter->reset_task);
+       cancel_work_sync(&adapter->link_chg_task);
+}
+
+/*
+ * atl1c_tx_timeout - Respond to a Tx Hang
+ * @netdev: network interface device structure
+ */
+static void atl1c_tx_timeout(struct net_device *netdev)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+
+       /* Do the reset outside of interrupt context */
+       schedule_work(&adapter->reset_task);
+}
+
+/*
+ * atl1c_set_multi - Multicast and Promiscuous mode set
+ * @netdev: network interface device structure
+ *
+ * The set_multi entry point is called whenever the multicast address
+ * list or the network interface flags are updated.  This routine is
+ * responsible for configuring the hardware for proper multicast,
+ * promiscuous mode, and all-multi behavior.
+ */
+static void atl1c_set_multi(struct net_device *netdev)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct atl1c_hw *hw = &adapter->hw;
+       struct dev_mc_list *mc_ptr;
+       u32 mac_ctrl_data;
+       u32 hash_value;
+
+       /* Check for Promiscuous and All Multicast modes */
+       AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
+
+       if (netdev->flags & IFF_PROMISC) {
+               mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
+       } else if (netdev->flags & IFF_ALLMULTI) {
+               mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
+               mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
+       } else {
+               mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
+       }
+
+       AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
+
+       /* clear the old settings from the multicast hash table */
+       AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
+       AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
+
+       /* comoute mc addresses' hash value ,and put it into hash table */
+       for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
+               hash_value = atl1c_hash_mc_addr(hw, mc_ptr->dmi_addr);
+               atl1c_hash_set(hw, hash_value);
+       }
+}
+
+static void atl1c_vlan_rx_register(struct net_device *netdev,
+                                  struct vlan_group *grp)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct pci_dev *pdev = adapter->pdev;
+       u32 mac_ctrl_data = 0;
+
+       if (netif_msg_pktdata(adapter))
+               dev_dbg(&pdev->dev, "atl1c_vlan_rx_register\n");
+
+       atl1c_irq_disable(adapter);
+
+       adapter->vlgrp = grp;
+       AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
+
+       if (grp) {
+               /* enable VLAN tag insert/strip */
+               mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
+       } else {
+               /* disable VLAN tag insert/strip */
+               mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
+       }
+
+       AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
+       atl1c_irq_enable(adapter);
+}
+
+static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
+{
+       struct pci_dev *pdev = adapter->pdev;
+
+       if (netif_msg_pktdata(adapter))
+               dev_dbg(&pdev->dev, "atl1c_restore_vlan !");
+       atl1c_vlan_rx_register(adapter->netdev, adapter->vlgrp);
+}
+/*
+ * atl1c_set_mac - Change the Ethernet Address of the NIC
+ * @netdev: network interface device structure
+ * @p: pointer to an address structure
+ *
+ * Returns 0 on success, negative on failure
+ */
+static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct sockaddr *addr = p;
+
+       if (!is_valid_ether_addr(addr->sa_data))
+               return -EADDRNOTAVAIL;
+
+       if (netif_running(netdev))
+               return -EBUSY;
+
+       memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+       memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
+
+       atl1c_hw_set_mac_addr(&adapter->hw);
+
+       return 0;
+}
+
+static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
+                               struct net_device *dev)
+{
+       int mtu = dev->mtu;
+
+       adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
+               roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
+}
+/*
+ * atl1c_change_mtu - Change the Maximum Transfer Unit
+ * @netdev: network interface device structure
+ * @new_mtu: new value for maximum frame size
+ *
+ * Returns 0 on success, negative on failure
+ */
+static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       int old_mtu   = netdev->mtu;
+       int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
+
+       if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
+                       (max_frame > MAX_JUMBO_FRAME_SIZE)) {
+               if (netif_msg_link(adapter))
+                       dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
+               return -EINVAL;
+       }
+       /* set MTU */
+       if (old_mtu != new_mtu && netif_running(netdev)) {
+               while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
+                       msleep(1);
+               netdev->mtu = new_mtu;
+               adapter->hw.max_frame_size = new_mtu;
+               atl1c_set_rxbufsize(adapter, netdev);
+               atl1c_down(adapter);
+               atl1c_up(adapter);
+               clear_bit(__AT_RESETTING, &adapter->flags);
+               if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
+                       u32 phy_data;
+
+                       AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
+                       phy_data |= 0x10000000;
+                       AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
+               }
+
+       }
+       return 0;
+}
+
+/*
+ *  caller should hold mdio_lock
+ */
+static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       u16 result;
+
+       atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
+       return result;
+}
+
+static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
+                            int reg_num, int val)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+
+       atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
+}
+
+/*
+ * atl1c_mii_ioctl -
+ * @netdev:
+ * @ifreq:
+ * @cmd:
+ */
+static int atl1c_mii_ioctl(struct net_device *netdev,
+                          struct ifreq *ifr, int cmd)
+{
+       struct atl1c_adapter *adapter = netdev_priv(netdev);
+       struct pci_dev *pdev = adapter->pdev;
+       struct mii_ioctl_data *data = if_mii(ifr);
+       unsigned long flags;
+       int retval = 0;
+
+       if (!netif_running(netdev))
+               return -EINVAL;
+
+       spin_lock_irqsave(&adapter->mdio_lock, flags);
+       switch (cmd) {
+       case SIOCGMIIPHY:
+               data->phy_id = 0;
+               break;
+
+       case SIOCGMIIREG:
+               if (!capable(CAP_NET_ADMIN)) {
+                       retval = -EPERM;
+                       goto out;
+               }
+               if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
+                                   &data->val_out)) {
+                       retval = -EIO;
+                       goto out;
+               }
+               break;
+
+       case SIOCSMIIREG:
+               if (!capable(CAP_NET_ADMIN)) {
+                       retval = -EPERM;
+                       goto out;
+               }
+               if (data->reg_num & ~(0x1F)) {
+                       retval = -EFAULT;
+                       goto out;
+               }
+
+               dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
+                               data->reg_num, data->val_in);
+               if (atl1c_write_phy_reg(&adapter->hw,
+                                    data->reg_num, data->val_in)) {
+                       retval = -EIO;
+                       goto out;
+               }
+               break;
+
+       default:
+               retval = -EOPNOTSUPP;
+               break;
+       }
+out:
+       spin_unlock_irqrestore(&adapter->mdio_lock, flags);
+       return retval;
+}
+
+/*
+ * atl1c_ioctl -
+ * @netdev:
+ * @ifreq:
+ * @cmd:
+ */
+static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+{
+       switch (cmd) {
+       case SIOCGMIIPHY:
+       case SIOCGMIIREG:
+       case SIOCSMIIREG:
+               return atl1c_mii_ioctl(netdev, ifr, cmd);
+       default:
+               return -EOPNOTSUPP;
+       }
+}
+
+/*
+ * atl1c_alloc_queues - Allocate memory for all rings
+ * @adapter: board private structure to initialize
+ *
+ */
+static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
+{
+       return 0;
+}
+
+static void atl1c_set_mac_type(struct atl1c_hw *hw)
+{
+       switch (hw->device_id) {
+       case PCI_DEVICE_ID_ATTANSIC_L2C:
+               hw->nic_type = athr_l2c;
+               break;
+
+       case PCI_DEVICE_ID_ATTANSIC_L1C:
+               hw->nic_type = athr_l1c;
+               break;
+
+       default:
+               break;
+       }
+}
+
+static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
+{
+       u32 phy_status_data;
+       u32 link_ctrl_data;
+
+       atl1c_set_mac_type(hw);
+       AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
+       AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
+
+       hw->ctrl_flags = ATL1C_INTR_CLEAR_ON_READ |
+                        ATL1C_INTR_MODRT_ENABLE  |
+                        ATL1C_RX_IPV6_CHKSUM     |
+                        ATL1C_TXQ_MODE_ENHANCE;
+       if (link_ctrl_data & LINK_CTRL_L0S_EN)
+               hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
+       if (link_ctrl_data & LINK_CTRL_L1_EN)
+               hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
+
+       if (hw->nic_type == athr_l1c) {
+               hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
+               hw->ctrl_flags |= ATL1C_LINK_CAP_1000M;
+       }
+       return 0;
+}
+/*
+ * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
+ * @adapter: board private structure to initialize
+ *
+ * atl1c_sw_init initializes the Adapter private data structure.
+ * Fields are initialized based on PCI device information and
+ * OS network device settings (MTU size).
+ */
+static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
+{
+       struct atl1c_hw *hw   = &adapter->hw;
+       struct pci_dev  *pdev = adapter->pdev;
+
+       adapter->wol = 0;
+       adapter->link_speed = SPEED_0;
+       adapter->link_duplex = FULL_DUPLEX;
+       adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
+       adapter->tpd_ring[0].count = 1024;
+       adapter->rfd_ring[0].count = 512;
+
+       hw->vendor_id = pdev->vendor;
+       hw->device_id = pdev->device;
+       hw->subsystem_vendor_id = pdev->subsystem_vendor;
+       hw->subsystem_id = pdev->subsystem_device;
+
+       /* before link up, we assume hibernate is true */
+       hw->hibernate = true;
+       hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
+       if (atl1c_setup_mac_funcs(hw) != 0) {
+               dev_err(&pdev->dev, "set mac function pointers failed\n");
+               return -1;
+       }
+       hw->intr_mask = IMR_NORMAL_MASK;
+       hw->phy_configured = false;
+       hw->preamble_len = 7;
+       hw->max_frame_size = adapter->netdev->mtu;
+       if (adapter->num_rx_queues < 2) {
+               hw->rss_type = atl1c_rss_disable;
+               hw->rss_mode = atl1c_rss_mode_disable;
+       } else {
+               hw->rss_type = atl1c_rss_ipv4;
+               hw->rss_mode = atl1c_rss_mul_que_mul_int;
+               hw->rss_hash_bits = 16;
+       }
+       hw->autoneg_advertised = ADVERTISED_Autoneg;
+       hw->indirect_tab = 0xE4E4E4E4;
+       hw->base_cpu = 0;
+
+       hw->ict = 50000;                /* 100ms */
+       hw->smb_timer = 200000;         /* 400ms */
+       hw->cmb_tpd = 4;
+       hw->cmb_tx_timer = 1;           /* 2 us  */
+       hw->rx_imt = 200;
+       hw->tx_imt = 1000;
+
+       hw->tpd_burst = 5;
+       hw->rfd_burst = 8;
+       hw->dma_order = atl1c_dma_ord_out;
+       hw->dmar_block = atl1c_dma_req_1024;
+       hw->dmaw_block = atl1c_dma_req_1024;
+       hw->dmar_dly_cnt = 15;
+       hw->dmaw_dly_cnt = 4;
+
+       if (atl1c_alloc_queues(adapter)) {
+               dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
+               return -ENOMEM;
+       }
+       /* TODO */
+       atl1c_set_rxbufsize(adapter, adapter->netdev);
+       atomic_set(&adapter->irq_sem, 1);
+       spin_lock_init(&adapter->mdio_lock);
+       spin_lock_init(&adapter->tx_loc