Merge tag 'v4.15-rc1' into drm-misc-fixes
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 27 Nov 2017 09:54:33 +0000 (10:54 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 27 Nov 2017 09:54:33 +0000 (10:54 +0100)
Linux 4.15-rc1

Pull in the merge window to resync. Dave didn't get his -fixes pull
landed in time, and now there's another rockchip fix pending, so
fast-forwarding isn't possible, hence backmerge.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
1  2 
drivers/gpu/drm/drm_edid.c
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
drivers/gpu/drm/vc4/vc4_hdmi.c
include/drm/drm_edid.h

index fc7946eb6665c4f07e796ea9c348ffa4c1cc81c8,2e8fb51282ef36813873a18017a69f0c5abc3c47..5dfe147638716730573d008edc65abfc92f6d75a
@@@ -82,6 -82,8 +82,8 @@@
  #define EDID_QUIRK_FORCE_6BPC                 (1 << 10)
  /* Force 10bpc */
  #define EDID_QUIRK_FORCE_10BPC                        (1 << 11)
+ /* Non desktop display (i.e. HMD) */
+ #define EDID_QUIRK_NON_DESKTOP                        (1 << 12)
  
  struct detailed_mode_closure {
        struct drm_connector *connector;
@@@ -157,6 -159,9 +159,9 @@@ static const struct edid_quirk 
  
        /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
        { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
+       /* HTC Vive VR Headset */
+       { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
  };
  
  /*
@@@ -1533,6 -1538,10 +1538,10 @@@ static void connector_bad_edid(struct d
   * level, drivers must make all reasonable efforts to expose it as an I2C
   * adapter and use drm_get_edid() instead of abusing this function.
   *
+  * The EDID may be overridden using debugfs override_edid or firmare EDID
+  * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
+  * order. Having either of them bypasses actual EDID reads.
+  *
   * Return: Pointer to valid EDID or NULL if we couldn't find any.
   */
  struct edid *drm_do_get_edid(struct drm_connector *connector,
  {
        int i, j = 0, valid_extensions = 0;
        u8 *edid, *new;
+       struct edid *override = NULL;
+       if (connector->override_edid)
+               override = drm_edid_duplicate((const struct edid *)
+                                             connector->edid_blob_ptr->data);
+       if (!override)
+               override = drm_load_edid_firmware(connector);
+       if (!IS_ERR_OR_NULL(override))
+               return override;
  
        if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
                return NULL;
@@@ -4378,7 -4398,7 +4398,7 @@@ static void drm_parse_cea_ext(struct dr
  }
  
  static void drm_add_display_info(struct drm_connector *connector,
-                                struct edid *edid)
+                                struct edid *edid, u32 quirks)
  {
        struct drm_display_info *info = &connector->display_info;
  
        info->max_tmds_clock = 0;
        info->dvi_dual = false;
  
+       info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
        if (edid->revision < 3)
                return;
  
@@@ -4612,7 -4634,7 +4634,7 @@@ int drm_add_edid_modes(struct drm_conne
         * To avoid multiple parsing of same block, lets parse that map
         * from sink info, before parsing CEA modes.
         */
-       drm_add_display_info(connector, edid);
+       drm_add_display_info(connector, edid, quirks);
  
        /*
         * EDID spec says modes should be preferred in this order:
@@@ -4809,8 -4831,7 +4831,8 @@@ voi
  drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
                                   const struct drm_display_mode *mode,
                                   enum hdmi_quantization_range rgb_quant_range,
 -                                 bool rgb_quant_range_selectable)
 +                                 bool rgb_quant_range_selectable,
 +                                 bool is_hdmi2_sink)
  {
        /*
         * CEA-861:
         *  YQ-field to match the RGB Quantization Range being transmitted
         *  (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
         *  set YQ=1) and the Sink shall ignore the YQ-field."
 +       *
 +       * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
 +       * by non-zero YQ when receiving RGB. There doesn't seem to be any
 +       * good way to tell which version of CEA-861 the sink supports, so
 +       * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
 +       * on on CEA-861-F.
         */
 -      if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
 +      if (!is_hdmi2_sink ||
 +          rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
                frame->ycc_quantization_range =
                        HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
        else
index 3fed1d3ecdedfdd5b51d13d42924a21d2299fde3,5132dc8147884f9ace0af2615f7047f63b15a9a2..4dea833f9d1b78c17239eeade593a72c88fbc166
@@@ -70,7 -70,7 +70,7 @@@ static struct intel_hdmi *intel_attache
        return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  }
  
- static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
+ static u32 g4x_infoframe_index(unsigned int type)
  {
        switch (type) {
        case HDMI_INFOFRAME_TYPE_AVI:
@@@ -85,7 -85,7 +85,7 @@@
        }
  }
  
- static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
+ static u32 g4x_infoframe_enable(unsigned int type)
  {
        switch (type) {
        case HDMI_INFOFRAME_TYPE_AVI:
        }
  }
  
- static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
+ static u32 hsw_infoframe_enable(unsigned int type)
  {
        switch (type) {
+       case DP_SDP_VSC:
+               return VIDEO_DIP_ENABLE_VSC_HSW;
        case HDMI_INFOFRAME_TYPE_AVI:
                return VIDEO_DIP_ENABLE_AVI_HSW;
        case HDMI_INFOFRAME_TYPE_SPD:
  static i915_reg_t
  hsw_dip_data_reg(struct drm_i915_private *dev_priv,
                 enum transcoder cpu_transcoder,
-                enum hdmi_infoframe_type type,
+                unsigned int type,
                 int i)
  {
        switch (type) {
+       case DP_SDP_VSC:
+               return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
        case HDMI_INFOFRAME_TYPE_AVI:
                return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
        case HDMI_INFOFRAME_TYPE_SPD:
  
  static void g4x_write_infoframe(struct drm_encoder *encoder,
                                const struct intel_crtc_state *crtc_state,
-                               enum hdmi_infoframe_type type,
+                               unsigned int type,
                                const void *frame, ssize_t len)
  {
        const uint32_t *data = frame;
@@@ -191,7 -195,7 +195,7 @@@ static bool g4x_infoframe_enabled(struc
  
  static void ibx_write_infoframe(struct drm_encoder *encoder,
                                const struct intel_crtc_state *crtc_state,
-                               enum hdmi_infoframe_type type,
+                               unsigned int type,
                                const void *frame, ssize_t len)
  {
        const uint32_t *data = frame;
@@@ -251,7 -255,7 +255,7 @@@ static bool ibx_infoframe_enabled(struc
  
  static void cpt_write_infoframe(struct drm_encoder *encoder,
                                const struct intel_crtc_state *crtc_state,
-                               enum hdmi_infoframe_type type,
+                               unsigned int type,
                                const void *frame, ssize_t len)
  {
        const uint32_t *data = frame;
@@@ -309,7 -313,7 +313,7 @@@ static bool cpt_infoframe_enabled(struc
  
  static void vlv_write_infoframe(struct drm_encoder *encoder,
                                const struct intel_crtc_state *crtc_state,
-                               enum hdmi_infoframe_type type,
+                               unsigned int type,
                                const void *frame, ssize_t len)
  {
        const uint32_t *data = frame;
@@@ -368,7 -372,7 +372,7 @@@ static bool vlv_infoframe_enabled(struc
  
  static void hsw_write_infoframe(struct drm_encoder *encoder,
                                const struct intel_crtc_state *crtc_state,
-                               enum hdmi_infoframe_type type,
+                               unsigned int type,
                                const void *frame, ssize_t len)
  {
        const uint32_t *data = frame;
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
        i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
        i915_reg_t data_reg;
+       int data_size = type == DP_SDP_VSC ?
+               VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
        int i;
        u32 val = I915_READ(ctl_reg);
  
                data++;
        }
        /* Write every possible data byte to force correct ECC calculation. */
-       for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
+       for (; i < data_size; i += 4)
                I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
                                            type, i >> 2), 0);
        mmiowb();
@@@ -434,7 -440,7 +440,7 @@@ static void intel_write_infoframe(struc
                                  const struct intel_crtc_state *crtc_state,
                                  union hdmi_infoframe *frame)
  {
-       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+       struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
        uint8_t buffer[VIDEO_DIP_DATA_SIZE];
        ssize_t len;
  
        buffer[3] = 0;
        len++;
  
-       intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
+       intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
  }
  
  static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
                                           crtc_state->limited_color_range ?
                                           HDMI_QUANTIZATION_RANGE_LIMITED :
                                           HDMI_QUANTIZATION_RANGE_FULL,
 -                                         intel_hdmi->rgb_quant_range_selectable);
 +                                         intel_hdmi->rgb_quant_range_selectable,
 +                                         is_hdmi2_sink);
  
        /* TODO: handle pixel repetition for YCBCR420 outputs */
        intel_write_infoframe(encoder, crtc_state, &frame);
@@@ -946,6 -951,7 +952,7 @@@ static void intel_hdmi_get_config(struc
                                  struct intel_crtc_state *pipe_config)
  {
        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+       struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        u32 tmp, flags = 0;
        if (tmp & HDMI_MODE_SELECT_HDMI)
                pipe_config->has_hdmi_sink = true;
  
-       if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
+       if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
                pipe_config->has_infoframe = true;
  
        if (tmp & SDVO_AUDIO_ENABLE)
  }
  
  static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
-                                   struct intel_crtc_state *pipe_config,
-                                   struct drm_connector_state *conn_state)
+                                   const struct intel_crtc_state *pipe_config,
+                                   const struct drm_connector_state *conn_state)
  {
        struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
  
  }
  
  static void g4x_enable_hdmi(struct intel_encoder *encoder,
-                           struct intel_crtc_state *pipe_config,
-                           struct drm_connector_state *conn_state)
+                           const struct intel_crtc_state *pipe_config,
+                           const struct drm_connector_state *conn_state)
  {
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
  }
  
  static void ibx_enable_hdmi(struct intel_encoder *encoder,
-                           struct intel_crtc_state *pipe_config,
-                           struct drm_connector_state *conn_state)
+                           const struct intel_crtc_state *pipe_config,
+                           const struct drm_connector_state *conn_state)
  {
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
  }
  
  static void cpt_enable_hdmi(struct intel_encoder *encoder,
-                           struct intel_crtc_state *pipe_config,
-                           struct drm_connector_state *conn_state)
+                           const struct intel_crtc_state *pipe_config,
+                           const struct drm_connector_state *conn_state)
  {
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
  }
  
  static void vlv_enable_hdmi(struct intel_encoder *encoder,
-                           struct intel_crtc_state *pipe_config,
-                           struct drm_connector_state *conn_state)
+                           const struct intel_crtc_state *pipe_config,
+                           const struct drm_connector_state *conn_state)
  {
  }
  
  static void intel_disable_hdmi(struct intel_encoder *encoder,
-                              struct intel_crtc_state *old_crtc_state,
-                              struct drm_connector_state *old_conn_state)
+                              const struct intel_crtc_state *old_crtc_state,
+                              const struct drm_connector_state *old_conn_state)
  {
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
        struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+       struct intel_digital_port *intel_dig_port =
+               hdmi_to_dig_port(intel_hdmi);
        struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
        u32 temp;
  
                intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
        }
  
-       intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
+       intel_dig_port->set_infoframes(&encoder->base, false,
+                                      old_crtc_state, old_conn_state);
  
        intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
  }
  
  static void g4x_disable_hdmi(struct intel_encoder *encoder,
-                            struct intel_crtc_state *old_crtc_state,
-                            struct drm_connector_state *old_conn_state)
+                            const struct intel_crtc_state *old_crtc_state,
+                            const struct drm_connector_state *old_conn_state)
  {
        if (old_crtc_state->has_audio)
                intel_audio_codec_disable(encoder);
  }
  
  static void pch_disable_hdmi(struct intel_encoder *encoder,
-                            struct intel_crtc_state *old_crtc_state,
-                            struct drm_connector_state *old_conn_state)
+                            const struct intel_crtc_state *old_crtc_state,
+                            const struct drm_connector_state *old_conn_state)
  {
        if (old_crtc_state->has_audio)
                intel_audio_codec_disable(encoder);
  }
  
  static void pch_post_disable_hdmi(struct intel_encoder *encoder,
-                                 struct intel_crtc_state *old_crtc_state,
-                                 struct drm_connector_state *old_conn_state)
+                                 const struct intel_crtc_state *old_crtc_state,
+                                 const struct drm_connector_state *old_conn_state)
  {
        intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
  }
@@@ -1315,7 -1324,7 +1325,7 @@@ intel_hdmi_mode_valid(struct drm_connec
        return status;
  }
  
- static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
+ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
  {
        struct drm_i915_private *dev_priv =
                to_i915(crtc_state->base.crtc->dev);
@@@ -1643,24 -1652,24 +1653,24 @@@ static int intel_hdmi_get_modes(struct 
  }
  
  static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
-                                 struct intel_crtc_state *pipe_config,
-                                 struct drm_connector_state *conn_state)
+                                 const struct intel_crtc_state *pipe_config,
+                                 const struct drm_connector_state *conn_state)
  {
-       struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
+       struct intel_digital_port *intel_dig_port =
+               enc_to_dig_port(&encoder->base);
  
        intel_hdmi_prepare(encoder, pipe_config);
  
-       intel_hdmi->set_infoframes(&encoder->base,
-                                  pipe_config->has_hdmi_sink,
-                                  pipe_config, conn_state);
+       intel_dig_port->set_infoframes(&encoder->base,
+                                      pipe_config->has_infoframe,
+                                      pipe_config, conn_state);
  }
  
  static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
-                               struct intel_crtc_state *pipe_config,
-                               struct drm_connector_state *conn_state)
+                               const struct intel_crtc_state *pipe_config,
+                               const struct drm_connector_state *conn_state)
  {
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-       struct intel_hdmi *intel_hdmi = &dport->hdmi;
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
  
        vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
                                 0x2b247878);
  
-       intel_hdmi->set_infoframes(&encoder->base,
-                                  pipe_config->has_hdmi_sink,
-                                  pipe_config, conn_state);
+       dport->set_infoframes(&encoder->base,
+                             pipe_config->has_infoframe,
+                             pipe_config, conn_state);
  
        g4x_enable_hdmi(encoder, pipe_config, conn_state);
  
  }
  
  static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
-                                   struct intel_crtc_state *pipe_config,
-                                   struct drm_connector_state *conn_state)
+                                   const struct intel_crtc_state *pipe_config,
+                                   const struct drm_connector_state *conn_state)
  {
        intel_hdmi_prepare(encoder, pipe_config);
  
  }
  
  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
-                                   struct intel_crtc_state *pipe_config,
-                                   struct drm_connector_state *conn_state)
+                                   const struct intel_crtc_state *pipe_config,
+                                   const struct drm_connector_state *conn_state)
  {
        intel_hdmi_prepare(encoder, pipe_config);
  
  }
  
  static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
-                                     struct intel_crtc_state *old_crtc_state,
-                                     struct drm_connector_state *old_conn_state)
+                                     const struct intel_crtc_state *old_crtc_state,
+                                     const struct drm_connector_state *old_conn_state)
  {
        chv_phy_post_pll_disable(encoder);
  }
  
  static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
-                                 struct intel_crtc_state *old_crtc_state,
-                                 struct drm_connector_state *old_conn_state)
+                                 const struct intel_crtc_state *old_crtc_state,
+                                 const struct drm_connector_state *old_conn_state)
  {
        /* Reset lanes to avoid HDMI flicker (VLV w/a) */
        vlv_phy_reset_lanes(encoder);
  }
  
  static void chv_hdmi_post_disable(struct intel_encoder *encoder,
-                                 struct intel_crtc_state *old_crtc_state,
-                                 struct drm_connector_state *old_conn_state)
+                                 const struct intel_crtc_state *old_crtc_state,
+                                 const struct drm_connector_state *old_conn_state)
  {
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
  }
  
  static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
-                               struct intel_crtc_state *pipe_config,
-                               struct drm_connector_state *conn_state)
+                               const struct intel_crtc_state *pipe_config,
+                               const struct drm_connector_state *conn_state)
  {
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
-       struct intel_hdmi *intel_hdmi = &dport->hdmi;
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = to_i915(dev);
  
        /* Use 800mV-0dB */
        chv_set_phy_signal_level(encoder, 128, 102, false);
  
-       intel_hdmi->set_infoframes(&encoder->base,
-                                  pipe_config->has_hdmi_sink,
-                                  pipe_config, conn_state);
+       dport->set_infoframes(&encoder->base,
+                             pipe_config->has_infoframe,
+                             pipe_config, conn_state);
  
        g4x_enable_hdmi(encoder, pipe_config, conn_state);
  
@@@ -1959,6 -1967,34 +1968,34 @@@ static u8 intel_hdmi_ddc_pin(struct drm
        return ddc_pin;
  }
  
+ void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
+ {
+       struct drm_i915_private *dev_priv =
+               to_i915(intel_dig_port->base.base.dev);
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+               intel_dig_port->write_infoframe = vlv_write_infoframe;
+               intel_dig_port->set_infoframes = vlv_set_infoframes;
+               intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
+       } else if (IS_G4X(dev_priv)) {
+               intel_dig_port->write_infoframe = g4x_write_infoframe;
+               intel_dig_port->set_infoframes = g4x_set_infoframes;
+               intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
+       } else if (HAS_DDI(dev_priv)) {
+               intel_dig_port->write_infoframe = hsw_write_infoframe;
+               intel_dig_port->set_infoframes = hsw_set_infoframes;
+               intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
+       } else if (HAS_PCH_IBX(dev_priv)) {
+               intel_dig_port->write_infoframe = ibx_write_infoframe;
+               intel_dig_port->set_infoframes = ibx_set_infoframes;
+               intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
+       } else {
+               intel_dig_port->write_infoframe = cpt_write_infoframe;
+               intel_dig_port->set_infoframes = cpt_set_infoframes;
+               intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
+       }
+ }
  void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
                               struct intel_connector *intel_connector)
  {
                return;
        intel_encoder->hpd_pin = intel_hpd_pin(port);
  
-       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-               intel_hdmi->write_infoframe = vlv_write_infoframe;
-               intel_hdmi->set_infoframes = vlv_set_infoframes;
-               intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
-       } else if (IS_G4X(dev_priv)) {
-               intel_hdmi->write_infoframe = g4x_write_infoframe;
-               intel_hdmi->set_infoframes = g4x_set_infoframes;
-               intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
-       } else if (HAS_DDI(dev_priv)) {
-               intel_hdmi->write_infoframe = hsw_write_infoframe;
-               intel_hdmi->set_infoframes = hsw_set_infoframes;
-               intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
-       } else if (HAS_PCH_IBX(dev_priv)) {
-               intel_hdmi->write_infoframe = ibx_write_infoframe;
-               intel_hdmi->set_infoframes = ibx_set_infoframes;
-               intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
-       } else {
-               intel_hdmi->write_infoframe = cpt_write_infoframe;
-               intel_hdmi->set_infoframes = cpt_set_infoframes;
-               intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
-       }
        if (HAS_DDI(dev_priv))
                intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
        else
@@@ -2114,5 -2128,7 +2129,7 @@@ void intel_hdmi_init(struct drm_i915_pr
        intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
        intel_dig_port->max_lanes = 4;
  
+       intel_infoframe_init(intel_dig_port);
        intel_hdmi_init_connector(intel_dig_port, intel_connector);
  }
index f7fc652b00270302cffdf07740d5652e1f1ef3f4,b15755b6129c2b3aa37e016f5d11f97da6427ba8..b1fe0639227e4bc499fb581ca494217f084a7c6f
@@@ -430,9 -430,9 +430,9 @@@ static int dw_mipi_dsi_phy_init(struct 
  
        testdin = max_mbps_to_testdin(dsi->lane_mbps);
        if (testdin < 0) {
-               dev_err(dsi->dev,
-                       "failed to get testdin for %dmbps lane clock\n",
-                       dsi->lane_mbps);
+               DRM_DEV_ERROR(dsi->dev,
+                             "failed to get testdin for %dmbps lane clock\n",
+                             dsi->lane_mbps);
                return testdin;
        }
  
  
        ret = clk_prepare_enable(dsi->phy_cfg_clk);
        if (ret) {
-               dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
+               DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
                return ret;
        }
  
        ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
                                 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
        if (ret < 0) {
-               dev_err(dsi->dev, "failed to wait for phy lock state\n");
+               DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");
                goto phy_init_end;
        }
  
                                 val, val & STOP_STATE_CLK_LANE, 1000,
                                 PHY_STATUS_TIMEOUT_US);
        if (ret < 0)
-               dev_err(dsi->dev,
-                       "failed to wait for phy clk lane stop state\n");
+               DRM_DEV_ERROR(dsi->dev,
+                             "failed to wait for phy clk lane stop state\n");
  
  phy_init_end:
        clk_disable_unprepare(dsi->phy_cfg_clk);
@@@ -529,8 -529,9 +529,9 @@@ static int dw_mipi_dsi_get_lane_bps(str
  
        bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
        if (bpp < 0) {
-               dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
-                       dsi->format);
+               DRM_DEV_ERROR(dsi->dev,
+                             "failed to get bpp for pixel format %d\n",
+                             dsi->format);
                return bpp;
        }
  
                if (tmp < max_mbps)
                        target_mbps = tmp;
                else
-                       dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
+                       DRM_DEV_ERROR(dsi->dev,
+                                     "DPHY clock frequency is out of range\n");
        }
  
        pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
@@@ -582,8 -584,9 +584,9 @@@ static int dw_mipi_dsi_host_attach(stru
        struct dw_mipi_dsi *dsi = host_to_dsi(host);
  
        if (device->lanes > dsi->pdata->max_data_lanes) {
-               dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
-                       device->lanes);
+               DRM_DEV_ERROR(dsi->dev,
+                             "the number of data lanes(%u) is too many\n",
+                             device->lanes);
                return -EINVAL;
        }
  
@@@ -632,7 -635,8 +635,8 @@@ static int dw_mipi_dsi_gen_pkt_hdr_writ
                                 val, !(val & GEN_CMD_FULL), 1000,
                                 CMD_PKT_STATUS_TIMEOUT_US);
        if (ret < 0) {
-               dev_err(dsi->dev, "failed to get available command FIFO\n");
+               DRM_DEV_ERROR(dsi->dev,
+                             "failed to get available command FIFO\n");
                return ret;
        }
  
                                 val, (val & mask) == mask,
                                 1000, CMD_PKT_STATUS_TIMEOUT_US);
        if (ret < 0) {
-               dev_err(dsi->dev, "failed to write command FIFO\n");
+               DRM_DEV_ERROR(dsi->dev, "failed to write command FIFO\n");
                return ret;
        }
  
@@@ -663,8 -667,9 +667,9 @@@ static int dw_mipi_dsi_dcs_short_write(
                data |= tx_buf[1] << 8;
  
        if (msg->tx_len > 2) {
-               dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
-                       msg->tx_len);
+               DRM_DEV_ERROR(dsi->dev,
+                             "too long tx buf length %zu for short write\n",
+                             msg->tx_len);
                return -EINVAL;
        }
  
@@@ -682,8 -687,9 +687,9 @@@ static int dw_mipi_dsi_dcs_long_write(s
        u32 val;
  
        if (msg->tx_len < 3) {
-               dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
-                       msg->tx_len);
+               DRM_DEV_ERROR(dsi->dev,
+                             "wrong tx buf length %zu for long write\n",
+                             msg->tx_len);
                return -EINVAL;
        }
  
                                         val, !(val & GEN_PLD_W_FULL), 1000,
                                         CMD_PKT_STATUS_TIMEOUT_US);
                if (ret < 0) {
-                       dev_err(dsi->dev,
-                               "failed to get available write payload FIFO\n");
+                       DRM_DEV_ERROR(dsi->dev,
+                                     "failed to get available write payload FIFO\n");
                        return ret;
                }
        }
@@@ -731,8 -737,8 +737,8 @@@ static ssize_t dw_mipi_dsi_host_transfe
                ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
                break;
        default:
-               dev_err(dsi->dev, "unsupported message type 0x%02x\n",
-                       msg->type);
+               DRM_DEV_ERROR(dsi->dev, "unsupported message type 0x%02x\n",
+                             msg->type);
                ret = -EINVAL;
        }
  
@@@ -935,7 -941,7 +941,7 @@@ static void dw_mipi_dsi_encoder_disable
                return;
  
        if (clk_prepare_enable(dsi->pclk)) {
-               dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
+               DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
                return;
        }
  
@@@ -967,7 -973,7 +973,7 @@@ static void dw_mipi_dsi_encoder_enable(
                return;
  
        if (clk_prepare_enable(dsi->pclk)) {
-               dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
+               DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
                return;
        }
  
         */
        ret = clk_prepare_enable(dsi->grf_clk);
        if (ret) {
-               dev_err(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
+               DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
                return;
        }
  
  
        dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
        if (drm_panel_prepare(dsi->panel))
-               dev_err(dsi->dev, "failed to prepare panel\n");
+               DRM_DEV_ERROR(dsi->dev, "failed to prepare panel\n");
  
        dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
        drm_panel_enable(dsi->panel);
                val = pdata->dsi0_en_bit << 16;
  
        regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
-       dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
+       DRM_DEV_DEBUG(dsi->dev,
+                     "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
        dsi->dpms_mode = DRM_MODE_DPMS_ON;
  
        clk_disable_unprepare(dsi->grf_clk);
@@@ -1111,7 -1118,7 +1118,7 @@@ static int dw_mipi_dsi_register(struct 
        ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
                               DRM_MODE_ENCODER_DSI, NULL);
        if (ret) {
-               dev_err(dev, "Failed to initialize encoder with drm\n");
+               DRM_DEV_ERROR(dev, "Failed to initialize encoder with drm\n");
                return ret;
        }
  
@@@ -1133,7 -1140,7 +1140,7 @@@ static int rockchip_mipi_parse_dt(struc
  
        dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
        if (IS_ERR(dsi->grf_regmap)) {
-               dev_err(dsi->dev, "Unable to get rockchip,grf\n");
+               DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
                return PTR_ERR(dsi->grf_regmap);
        }
  
@@@ -1205,14 -1212,15 +1212,15 @@@ static int dw_mipi_dsi_bind(struct devi
        dsi->pllref_clk = devm_clk_get(dev, "ref");
        if (IS_ERR(dsi->pllref_clk)) {
                ret = PTR_ERR(dsi->pllref_clk);
-               dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
+               DRM_DEV_ERROR(dev,
+                             "Unable to get pll reference clock: %d\n", ret);
                return ret;
        }
  
        dsi->pclk = devm_clk_get(dev, "pclk");
        if (IS_ERR(dsi->pclk)) {
                ret = PTR_ERR(dsi->pclk);
-               dev_err(dev, "Unable to get pclk: %d\n", ret);
+               DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
                return ret;
        }
  
                if (ret == -ENOENT) {
                        apb_rst = NULL;
                } else {
-                       dev_err(dev, "Unable to get reset control: %d\n", ret);
+                       DRM_DEV_ERROR(dev,
+                                     "Unable to get reset control: %d\n", ret);
                        return ret;
                }
        }
        if (apb_rst) {
                ret = clk_prepare_enable(dsi->pclk);
                if (ret) {
-                       dev_err(dev, "%s: Failed to enable pclk\n", __func__);
+                       DRM_DEV_ERROR(dev, "Failed to enable pclk\n");
                        return ret;
                }
  
                dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
                if (IS_ERR(dsi->phy_cfg_clk)) {
                        ret = PTR_ERR(dsi->phy_cfg_clk);
-                       dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
+                       DRM_DEV_ERROR(dev,
+                                     "Unable to get phy_cfg_clk: %d\n", ret);
                        return ret;
                }
        }
                dsi->grf_clk = devm_clk_get(dev, "grf");
                if (IS_ERR(dsi->grf_clk)) {
                        ret = PTR_ERR(dsi->grf_clk);
-                       dev_err(dev, "Unable to get grf_clk: %d\n", ret);
+                       DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
                        return ret;
                }
        }
  
        ret = clk_prepare_enable(dsi->pllref_clk);
        if (ret) {
-               dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
+               DRM_DEV_ERROR(dev, "Failed to enable pllref_clk\n");
                return ret;
        }
  
        ret = dw_mipi_dsi_register(drm, dsi);
        if (ret) {
-               dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
+               DRM_DEV_ERROR(dev, "Failed to register mipi_dsi: %d\n", ret);
                goto err_pllref;
        }
  
 -      pm_runtime_enable(dev);
 -
        dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
        dsi->dsi_host.dev = dev;
        ret = mipi_dsi_host_register(&dsi->dsi_host);
        if (ret) {
-               dev_err(dev, "Failed to register MIPI host: %d\n", ret);
+               DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
                goto err_cleanup;
        }
  
        }
  
        dev_set_drvdata(dev, dsi);
 +      pm_runtime_enable(dev);
        return 0;
  
  err_mipi_dsi_host:
index 8f71157a2b063b07a3d3c195ae5049a0ddcac03e,fa37a1c07cf695900b0cb5b681f727169af51a62..0b2088264039131f05c2f09bc9ba84d2d3793e39
@@@ -309,16 -309,13 +309,13 @@@ static const struct drm_connector_helpe
  static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
                                                     struct drm_encoder *encoder)
  {
-       struct drm_connector *connector = NULL;
+       struct drm_connector *connector;
        struct vc4_hdmi_connector *hdmi_connector;
-       int ret = 0;
  
        hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
                                      GFP_KERNEL);
-       if (!hdmi_connector) {
-               ret = -ENOMEM;
-               goto fail;
-       }
+       if (!hdmi_connector)
+               return ERR_PTR(-ENOMEM);
        connector = &hdmi_connector->base;
  
        hdmi_connector->encoder = encoder;
        drm_mode_connector_attach_encoder(connector, encoder);
  
        return connector;
-  fail:
-       if (connector)
-               vc4_hdmi_connector_destroy(connector);
-       return ERR_PTR(ret);
  }
  
  static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
@@@ -433,8 -424,7 +424,8 @@@ static void vc4_hdmi_set_avi_infoframe(
                                           vc4_encoder->limited_rgb_range ?
                                           HDMI_QUANTIZATION_RANGE_LIMITED :
                                           HDMI_QUANTIZATION_RANGE_FULL,
 -                                         vc4_encoder->rgb_range_selectable);
 +                                         vc4_encoder->rgb_range_selectable,
 +                                         false);
  
        vc4_hdmi_write_infoframe(encoder, &frame);
  }
diff --combined include/drm/drm_edid.h
index a992434ded999d1a6b77cf34dd26a2c0f5a8fbd9,6f35909b8add3221fe8ad4b4c108e5a1498c7f08..2ec41d032e560f0fa4d04ef8d23d6b3442529473
@@@ -341,6 -341,8 +341,8 @@@ int drm_av_sync_delay(struct drm_connec
  
  #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
  struct edid *drm_load_edid_firmware(struct drm_connector *connector);
+ int __drm_set_edid_firmware_path(const char *path);
+ int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
  #else
  static inline struct edid *
  drm_load_edid_firmware(struct drm_connector *connector)
@@@ -360,8 -362,7 +362,8 @@@ voi
  drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
                                   const struct drm_display_mode *mode,
                                   enum hdmi_quantization_range rgb_quant_range,
 -                                 bool rgb_quant_range_selectable);
 +                                 bool rgb_quant_range_selectable,
 +                                 bool is_hdmi2_sink);
  
  /**
   * drm_eld_mnl - Get ELD monitor name length in bytes.