clk: imx8mq: add GPIO clocks to clock tree
authorAnson Huang <anson.huang@nxp.com>
Wed, 27 Feb 2019 01:28:26 +0000 (01:28 +0000)
committerStephen Boyd <sboyd@kernel.org>
Thu, 28 Feb 2019 18:28:28 +0000 (10:28 -0800)
i.MX8MQ has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/imx/clk-imx8mq.c
include/dt-bindings/clock/imx8mq-clock.h

index 081dc2d7c99c7bb44c733bd91805efc022d545f8..a9b3888aef0c207bb97ffa4191131bda3425565f 100644 (file)
@@ -473,6 +473,11 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
        clks[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
        clks[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
        clks[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
+       clks[IMX8MQ_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
+       clks[IMX8MQ_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
+       clks[IMX8MQ_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
+       clks[IMX8MQ_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
+       clks[IMX8MQ_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
        clks[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
        clks[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
        clks[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
index 491e39c146be898fbe02aeecef7599bd84e898b4..b58cc643c9c9e94360c1ab0fde1fc0e6a2d57d43 100644 (file)
 #define IMX8MQ_CLK_CLKO1                       268
 #define IMX8MQ_CLK_ARM                         269
 
-#define IMX8MQ_CLK_END                         270
+#define IMX8MQ_CLK_GPIO1_ROOT                  270
+#define IMX8MQ_CLK_GPIO2_ROOT                  271
+#define IMX8MQ_CLK_GPIO3_ROOT                  272
+#define IMX8MQ_CLK_GPIO4_ROOT                  273
+#define IMX8MQ_CLK_GPIO5_ROOT                  274
+
+#define IMX8MQ_CLK_END                         275
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */