Merge tag 'gvt-next-2017-12-14' of https://github.com/intel/gvt-linux into drm-intel...
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 14 Dec 2017 18:57:39 +0000 (10:57 -0800)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 14 Dec 2017 18:57:41 +0000 (10:57 -0800)
gvt-next-2017-12-14:

- fixes for two coverity scan errors (Colin)
- mmio switch code refine (Changbin)
- more virtual display dmabuf fixes (Tina/Gustavo)
- misc cleanups (Pei)

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171214033434.jlppjlyal5d67ya7@zhen-hp.sh.intel.com
1  2 
drivers/gpu/drm/i915/gvt/Makefile
drivers/gpu/drm/i915/gvt/gvt.h
drivers/gpu/drm/i915/gvt/handlers.c
drivers/gpu/drm/i915/gvt/mmio_context.c

index 883189694eb64e5d8bb501a33aaa9c29ca8ab1cf,0ee9c6250e90dc76982faa718d0157d7f88bd497..347116faa558f2fb0f148ad5f67132577501f460
@@@ -1,8 -1,7 +1,8 @@@
 +# SPDX-License-Identifier: GPL-2.0
  GVT_DIR := gvt
  GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
        interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
-       execlist.o scheduler.o sched_policy.o render.o cmd_parser.o debugfs.o \
+       execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o debugfs.o \
        fb_decoder.o dmabuf.o
  
  ccflags-y                             += -I$(src) -I$(src)/$(GVT_DIR)
index 103910a24e4b275dccc1b4a0f0a425a90e4a7b84,b4747c270dcb334ff58361b8e4fed8eae23c9d15..1e9f11c8b7bbf432170b90a41b15d3133a9d6e21
@@@ -44,7 -44,7 +44,7 @@@
  #include "execlist.h"
  #include "scheduler.h"
  #include "sched_policy.h"
- #include "render.h"
+ #include "mmio_context.h"
  #include "cmd_parser.h"
  #include "fb_decoder.h"
  #include "dmabuf.h"
@@@ -310,6 -310,8 +310,8 @@@ struct intel_gvt 
        wait_queue_head_t service_thread_wq;
        unsigned long service_request;
  
+       struct engine_mmio *engine_mmio_list;
        struct dentry *debugfs_root;
  };
  
@@@ -348,7 -350,7 +350,7 @@@ int intel_gvt_load_firmware(struct inte
  
  /* Aperture/GM space definitions for GVT device */
  #define gvt_aperture_sz(gvt)    (gvt->dev_priv->ggtt.mappable_end)
 -#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
 +#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)
  
  #define gvt_ggtt_gm_sz(gvt)     (gvt->dev_priv->ggtt.base.total)
  #define gvt_ggtt_sz(gvt) \
index 94fc04210bac96ed27cbfe701867f1f5a1e6513d,6f95bc04f0f0f2d801f838dfb7244dfaa897f92f..c982867e7c2b11924df8539a96f57e12d1cb5c6e
@@@ -174,8 -174,10 +174,10 @@@ void enter_failsafe_mode(struct intel_v
                break;
        case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
                pr_err("Graphics resource is not enough for the guest\n");
+               break;
        case GVT_FAILSAFE_GUEST_ERR:
                pr_err("GVT Internal error  for the guest\n");
+               break;
        default:
                break;
        }
@@@ -1396,7 -1398,7 +1398,7 @@@ static int hws_pga_write(struct intel_v
         * update the VM CSB status correctly. Here listed registers can
         * support BDW, SKL or other platforms with same HWSP registers.
         */
-       if (unlikely(ring_id < 0 || ring_id > I915_NUM_ENGINES)) {
+       if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
                gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n",
                             vgpu->id, offset);
                return -EINVAL;
@@@ -1420,6 -1422,40 +1422,6 @@@ static int skl_power_well_ctl_write(str
        return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
  }
  
 -static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
 -              void *p_data, unsigned int bytes)
 -{
 -      struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 -      u32 v = *(u32 *)p_data;
 -
 -      if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
 -              return intel_vgpu_default_mmio_write(vgpu,
 -                              offset, p_data, bytes);
 -
 -      switch (offset) {
 -      case 0x4ddc:
 -              /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
 -              vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
 -              break;
 -      case 0x42080:
 -              /* bypass WaCompressedResourceDisplayNewHashMode */
 -              vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
 -              break;
 -      case 0xe194:
 -              /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
 -              vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
 -              break;
 -      case 0x7014:
 -              /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
 -              vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
 -              break;
 -      default:
 -              return -EINVAL;
 -      }
 -
 -      return 0;
 -}
 -
  static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
                void *p_data, unsigned int bytes)
  {
@@@ -1471,7 -1507,7 +1473,7 @@@ static int elsp_mmio_write(struct intel
        u32 data = *(u32 *)p_data;
        int ret = 0;
  
-       if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
+       if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
                return -EINVAL;
  
        execlist = &vgpu->submission.execlist[ring_id];
@@@ -1706,8 -1742,8 +1708,8 @@@ static int init_generic_mmio_info(struc
        MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
                NULL, NULL);
 -      MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
 -               skl_misc_ctl_write);
 +      MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
 +               NULL, NULL);
        MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
@@@ -2599,7 -2635,8 +2601,7 @@@ static int init_broadwell_mmio_info(str
        MMIO_D(0x6e570, D_BDW_PLUS);
        MMIO_D(0x65f10, D_BDW_PLUS);
  
 -      MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
 -               skl_misc_ctl_write);
 +      MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
        MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
@@@ -2649,8 -2686,8 +2651,8 @@@ static int init_skl_mmio_info(struct in
        MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
        MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
        MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
 -      MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write);
 -      MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write);
 +      MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, NULL);
 +      MMIO_DH(0x42080, D_SKL_PLUS, NULL, NULL);
        MMIO_D(0x45504, D_SKL_PLUS);
        MMIO_D(0x45520, D_SKL_PLUS);
        MMIO_D(0x46000, D_SKL_PLUS);
index dac12c25f349d91becd352050c63e301b527726f,4c8e1285c6072241b658f67f9c6cdb3c480b8adc..8a52b56f0e8601d886364c62f5aa66371ba41eb3
  #include "gvt.h"
  #include "trace.h"
  
- struct render_mmio {
-       int ring_id;
-       i915_reg_t reg;
-       u32 mask;
-       bool in_context;
-       u32 value;
- };
- static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = {
-       {RCS, _MMIO(0x229c), 0xffff, false},
-       {RCS, _MMIO(0x2248), 0x0, false},
-       {RCS, _MMIO(0x2098), 0x0, false},
-       {RCS, _MMIO(0x20c0), 0xffff, true},
-       {RCS, _MMIO(0x24d0), 0, false},
-       {RCS, _MMIO(0x24d4), 0, false},
-       {RCS, _MMIO(0x24d8), 0, false},
-       {RCS, _MMIO(0x24dc), 0, false},
-       {RCS, _MMIO(0x24e0), 0, false},
-       {RCS, _MMIO(0x24e4), 0, false},
-       {RCS, _MMIO(0x24e8), 0, false},
-       {RCS, _MMIO(0x24ec), 0, false},
-       {RCS, _MMIO(0x24f0), 0, false},
-       {RCS, _MMIO(0x24f4), 0, false},
-       {RCS, _MMIO(0x24f8), 0, false},
-       {RCS, _MMIO(0x24fc), 0, false},
-       {RCS, _MMIO(0x7004), 0xffff, true},
-       {RCS, _MMIO(0x7008), 0xffff, true},
-       {RCS, _MMIO(0x7000), 0xffff, true},
-       {RCS, _MMIO(0x7010), 0xffff, true},
-       {RCS, _MMIO(0x7300), 0xffff, true},
-       {RCS, _MMIO(0x83a4), 0xffff, true},
-       {BCS, _MMIO(0x2229c), 0xffff, false},
-       {BCS, _MMIO(0x2209c), 0xffff, false},
-       {BCS, _MMIO(0x220c0), 0xffff, false},
-       {BCS, _MMIO(0x22098), 0x0, false},
-       {BCS, _MMIO(0x22028), 0x0, false},
+ /**
+  * Defined in Intel Open Source PRM.
+  * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
+  */
+ #define TRVATTL3PTRDW(i)      _MMIO(0x4de0 + (i)*4)
+ #define TRNULLDETCT           _MMIO(0x4de8)
+ #define TRINVTILEDETCT                _MMIO(0x4dec)
+ #define TRVADR                        _MMIO(0x4df0)
+ #define TRTTE                 _MMIO(0x4df4)
+ #define RING_EXCC(base)               _MMIO((base) + 0x28)
+ #define RING_GFX_MODE(base)   _MMIO((base) + 0x29c)
+ #define VF_GUARDBAND          _MMIO(0x83a4)
+ /* Raw offset is appened to each line for convenience. */
+ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
+       {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+       {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
+       {RCS, HWSTAM, 0x0, false}, /* 0x2098 */
+       {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
+       {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
+       {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
+       {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
+       {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
+       {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
+       {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
+       {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
+       {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
+       {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
+       {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
+       {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
+       { /* Terminated */ }
  };
  
- static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = {
-       {RCS, _MMIO(0x229c), 0xffff, false},
-       {RCS, _MMIO(0x2248), 0x0, false},
-       {RCS, _MMIO(0x2098), 0x0, false},
-       {RCS, _MMIO(0x20c0), 0xffff, true},
-       {RCS, _MMIO(0x24d0), 0, false},
-       {RCS, _MMIO(0x24d4), 0, false},
-       {RCS, _MMIO(0x24d8), 0, false},
-       {RCS, _MMIO(0x24dc), 0, false},
-       {RCS, _MMIO(0x24e0), 0, false},
-       {RCS, _MMIO(0x24e4), 0, false},
-       {RCS, _MMIO(0x24e8), 0, false},
-       {RCS, _MMIO(0x24ec), 0, false},
-       {RCS, _MMIO(0x24f0), 0, false},
-       {RCS, _MMIO(0x24f4), 0, false},
-       {RCS, _MMIO(0x24f8), 0, false},
-       {RCS, _MMIO(0x24fc), 0, false},
-       {RCS, _MMIO(0x7004), 0xffff, true},
-       {RCS, _MMIO(0x7008), 0xffff, true},
-       {RCS, _MMIO(0x7000), 0xffff, true},
-       {RCS, _MMIO(0x7010), 0xffff, true},
-       {RCS, _MMIO(0x7300), 0xffff, true},
-       {RCS, _MMIO(0x83a4), 0xffff, true},
-       {RCS, _MMIO(0x40e0), 0, false},
-       {RCS, _MMIO(0x40e4), 0, false},
-       {RCS, _MMIO(0x2580), 0xffff, true},
-       {RCS, _MMIO(0x7014), 0xffff, true},
-       {RCS, _MMIO(0x20ec), 0xffff, false},
-       {RCS, _MMIO(0xb118), 0, false},
-       {RCS, _MMIO(0xe100), 0xffff, true},
-       {RCS, _MMIO(0xe180), 0xffff, true},
-       {RCS, _MMIO(0xe184), 0xffff, true},
-       {RCS, _MMIO(0xe188), 0xffff, true},
-       {RCS, _MMIO(0xe194), 0xffff, true},
-       {RCS, _MMIO(0x4de0), 0, false},
-       {RCS, _MMIO(0x4de4), 0, false},
-       {RCS, _MMIO(0x4de8), 0, false},
-       {RCS, _MMIO(0x4dec), 0, false},
-       {RCS, _MMIO(0x4df0), 0, false},
-       {RCS, _MMIO(0x4df4), 0, false},
-       {BCS, _MMIO(0x2229c), 0xffff, false},
-       {BCS, _MMIO(0x2209c), 0xffff, false},
-       {BCS, _MMIO(0x220c0), 0xffff, false},
-       {BCS, _MMIO(0x22098), 0x0, false},
-       {BCS, _MMIO(0x22028), 0x0, false},
-       {VCS2, _MMIO(0x1c028), 0xffff, false},
-       {VECS, _MMIO(0x1a028), 0xffff, false},
-       {RCS, _MMIO(0x7304), 0xffff, true},
-       {RCS, _MMIO(0x2248), 0x0, false},
-       {RCS, _MMIO(0x940c), 0x0, false},
-       {RCS, _MMIO(0x4ab8), 0x0, false},
-       {RCS, _MMIO(0x4ab0), 0x0, false},
-       {RCS, _MMIO(0x20d4), 0x0, false},
-       {RCS, _MMIO(0xb004), 0x0, false},
-       {RCS, _MMIO(0x20a0), 0x0, false},
-       {RCS, _MMIO(0x20e4), 0xffff, false},
+ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
+       {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+       {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
+       {RCS, HWSTAM, 0x0, false}, /* 0x2098 */
+       {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
+       {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
+       {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
+       {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
+       {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
+       {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
+       {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
+       {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
+       {RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
+       {RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
+       {RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
+       {RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
+       {RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
+       {RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
+       {RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
+       {RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
+       {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
+       {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
+       {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
+       {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
+       {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
+       {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
+       {RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
+       {RCS, TRVADR, 0, false}, /* 0x4df0 */
+       {RCS, TRTTE, 0, false}, /* 0x4df4 */
+       {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
+       {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
+       {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
+       {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
+       {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
+       {VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
+       {VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
+       {RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
+       {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
+       {RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
+       {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
+       {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
+       {RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
+       {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
+       {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
+       {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
+       { /* Terminated */ }
  };
  
  static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
@@@ -267,22 -275,14 +275,14 @@@ static void switch_mmio_to_vgpu(struct 
        u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
        u32 inhibit_mask =
                _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
-       i915_reg_t last_reg = _MMIO(0);
-       struct render_mmio *mmio;
+       struct engine_mmio *mmio;
        u32 v;
-       int i, array_size;
  
-       if (IS_SKYLAKE(vgpu->gvt->dev_priv)
-               || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
-               mmio = gen9_render_mmio_list;
-               array_size = ARRAY_SIZE(gen9_render_mmio_list);
+       if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
                load_mocs(vgpu, ring_id);
-       } else {
-               mmio = gen8_render_mmio_list;
-               array_size = ARRAY_SIZE(gen8_render_mmio_list);
-       }
  
-       for (i = 0; i < array_size; i++, mmio++) {
+       mmio = vgpu->gvt->engine_mmio_list;
+       while (i915_mmio_reg_offset((mmio++)->reg)) {
                if (mmio->ring_id != ring_id)
                        continue;
  
                 * write.
                 */
                if (mmio->in_context &&
 -                              ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
 -                              i915_modparams.enable_execlists)
 +                  (ctx_ctrl & inhibit_mask) != inhibit_mask)
                        continue;
  
                if (mmio->mask)
                        v = vgpu_vreg(vgpu, mmio->reg);
  
                I915_WRITE_FW(mmio->reg, v);
-               last_reg = mmio->reg;
  
                trace_render_mmio(vgpu->id, "load",
                                  i915_mmio_reg_offset(mmio->reg),
                                  mmio->value, v);
        }
  
-       /* Make sure the swiched MMIOs has taken effect. */
-       if (likely(INTEL_GVT_MMIO_OFFSET(last_reg)))
-               I915_READ_FW(last_reg);
        handle_tlb_pending_event(vgpu, ring_id);
  }
  
  static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
  {
        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
-       struct render_mmio *mmio;
-       i915_reg_t last_reg = _MMIO(0);
+       struct engine_mmio *mmio;
        u32 v;
-       int i, array_size;
  
-       if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
-               mmio = gen9_render_mmio_list;
-               array_size = ARRAY_SIZE(gen9_render_mmio_list);
+       if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
                restore_mocs(vgpu, ring_id);
-       } else {
-               mmio = gen8_render_mmio_list;
-               array_size = ARRAY_SIZE(gen8_render_mmio_list);
-       }
  
-       for (i = 0; i < array_size; i++, mmio++) {
+       mmio = vgpu->gvt->engine_mmio_list;
+       while (i915_mmio_reg_offset((mmio++)->reg)) {
                if (mmio->ring_id != ring_id)
                        continue;
  
                        continue;
  
                I915_WRITE_FW(mmio->reg, v);
-               last_reg = mmio->reg;
  
                trace_render_mmio(vgpu->id, "restore",
                                  i915_mmio_reg_offset(mmio->reg),
                                  mmio->value, v);
        }
-       /* Make sure the swiched MMIOs has taken effect. */
-       if (likely(INTEL_GVT_MMIO_OFFSET(last_reg)))
-               I915_READ_FW(last_reg);
  }
  
  /**
@@@ -404,3 -388,16 +387,16 @@@ void intel_gvt_switch_mmio(struct intel
  
        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  }
+ /**
+  * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
+  * @gvt: GVT device
+  *
+  */
+ void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
+ {
+       if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv))
+               gvt->engine_mmio_list = gen9_engine_mmio_list;
+       else
+               gvt->engine_mmio_list = gen8_engine_mmio_list;
+ }