Merge tag 'mmc-v4.14-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 7 Oct 2017 17:03:03 +0000 (10:03 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 7 Oct 2017 17:03:03 +0000 (10:03 -0700)
Pull MMC fixes from Ulf Hansson:
 "MMC core:

   - Fix driver strength selection when selecting hs400es

   - Delete bounce buffer handling:

     This change fixes a problem related to how bounce buffers are being
     allocated. However, instead of trying to fix that, let's just
     remove the mmc bounce buffer code altogether, as it has practically
     no use.

  MMC host:

   - meson-gx: A couple of fixes related to clock/phase/tuning

   - sdhci-xenon: Fix clock resource by adding an optional bus clock"

* tag 'mmc-v4.14-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: sdhci-xenon: Fix clock resource by adding an optional bus clock
  mmc: meson-gx: include tx phase in the tuning process
  mmc: meson-gx: fix rx phase reset
  mmc: meson-gx: make sure the clock is rounded down
  mmc: Delete bounce buffer handling
  mmc: core: add driver strength selection when selecting hs400es

395 files changed:
.mailmap
Documentation/ABI/testing/sysfs-power
Documentation/core-api/workqueue.rst
Documentation/device-mapper/dm-raid.txt
Documentation/devicetree/bindings/net/marvell-pp2.txt
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt [new file with mode: 0644]
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
Documentation/driver-model/driver.txt
Documentation/filesystems/overlayfs.txt
Documentation/filesystems/sysfs.txt
MAINTAINERS
arch/alpha/include/asm/mmu_context.h
arch/arc/Kconfig
arch/arc/Makefile
arch/arc/boot/dts/axs10x_mb.dtsi
arch/arc/boot/dts/hsdk.dts
arch/arc/configs/axs101_defconfig
arch/arc/configs/axs103_defconfig
arch/arc/configs/axs103_smp_defconfig
arch/arc/configs/haps_hs_smp_defconfig
arch/arc/configs/hsdk_defconfig
arch/arc/configs/vdk_hs38_defconfig
arch/arc/configs/vdk_hs38_smp_defconfig
arch/arc/include/asm/arcregs.h
arch/arc/kernel/setup.c
arch/arc/plat-axs10x/axs10x.c
arch/arc/plat-hsdk/Kconfig
arch/arc/plat-hsdk/platform.c
arch/arm/boot/dts/am33xx.dtsi
arch/arm/boot/dts/am43x-epos-evm.dts
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
arch/arm/boot/dts/da850-evm.dts
arch/arm/boot/dts/dra7xx-clocks.dtsi
arch/arm/boot/dts/omap3-n900.dts
arch/arm/boot/dts/stm32429i-eval.dts
arch/arm/boot/dts/stm32f4-pinctrl.dtsi [new file with mode: 0644]
arch/arm/boot/dts/stm32f429-disco.dts
arch/arm/boot/dts/stm32f429-pinctrl.dtsi [new file with mode: 0644]
arch/arm/boot/dts/stm32f429.dtsi
arch/arm/boot/dts/stm32f469-disco.dts
arch/arm/boot/dts/stm32f469-pinctrl.dtsi [new file with mode: 0644]
arch/arm/configs/gemini_defconfig
arch/arm/configs/pxa_defconfig
arch/arm/configs/viper_defconfig
arch/arm/configs/zeus_defconfig
arch/arm/mach-at91/pm.c
arch/arm/mach-omap2/hsmmc.c
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
arch/arm64/boot/dts/rockchip/rk3368.dtsi
arch/arm64/boot/dts/rockchip/rk3399.dtsi
arch/arm64/include/asm/memory.h
arch/arm64/kernel/armv8_deprecated.c
arch/arm64/kernel/cpufeature.c
arch/arm64/kernel/fpsimd.c
arch/arm64/mm/fault.c
arch/m32r/Kconfig
arch/m32r/kernel/traps.c
arch/parisc/kernel/process.c
arch/powerpc/kernel/dt_cpu_ftrs.c
arch/powerpc/kernel/mce_power.c
arch/powerpc/kernel/setup-common.c
arch/powerpc/kernel/watchdog.c
arch/powerpc/kvm/book3s_xive.c
arch/powerpc/kvm/book3s_xive.h
arch/powerpc/mm/pgtable_32.c
arch/powerpc/platforms/powernv/setup.c
arch/powerpc/sysdev/fsl_rio.c
arch/powerpc/sysdev/fsl_rmu.c
arch/powerpc/sysdev/xive/common.c
arch/powerpc/sysdev/xive/spapr.c
arch/sh/include/cpu-sh2a/cpu/sh7264.h
arch/sh/include/cpu-sh2a/cpu/sh7269.h
arch/sh/include/cpu-sh4/cpu/sh7722.h
arch/sh/include/cpu-sh4/cpu/sh7757.h
arch/x86/events/intel/core.c
arch/x86/include/asm/kvm_para.h
arch/x86/kernel/kvm.c
arch/x86/kvm/Kconfig
arch/x86/kvm/emulate.c
arch/x86/kvm/mmu.c
arch/x86/net/bpf_jit_comp.c
block/blk-mq-debugfs.c
block/blk-throttle.c
block/bsg-lib.c
drivers/acpi/arm64/iort.c
drivers/android/binder.c
drivers/android/binder_alloc.c
drivers/ata/ahci.c
drivers/ata/ata_piix.c
drivers/ata/libata-core.c
drivers/auxdisplay/charlcd.c
drivers/auxdisplay/panel.c
drivers/base/arch_topology.c
drivers/base/platform.c
drivers/block/Kconfig
drivers/block/nbd.c
drivers/block/zram/zram_drv.c
drivers/clk/clk-bulk.c
drivers/clk/rockchip/clk-rk3128.c
drivers/clk/samsung/clk-exynos4.c
drivers/fpga/altera-cvp.c
drivers/gpu/drm/i915/intel_audio.c
drivers/gpu/drm/i915/intel_bios.c
drivers/gpu/drm/i915/intel_csr.c
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dpio_phy.c
drivers/gpu/drm/i915/intel_modes.c
drivers/gpu/drm/i915/intel_runtime_pm.c
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
drivers/hid/hid-ids.h
drivers/hid/hid-multitouch.c
drivers/hid/hid-rmi.c
drivers/hid/hidraw.c
drivers/hid/i2c-hid/i2c-hid.c
drivers/hid/usbhid/hid-quirks.c
drivers/hid/wacom_sys.c
drivers/hid/wacom_wac.c
drivers/hv/channel_mgmt.c
drivers/hv/hv_fcopy.c
drivers/hwmon/xgene-hwmon.c
drivers/hwtracing/intel_th/pci.c
drivers/hwtracing/stm/core.c
drivers/i2c/busses/i2c-img-scb.c
drivers/ide/ide-probe.c
drivers/ide/ide-scan-pci.c
drivers/ide/setup-pci.c
drivers/iio/adc/ad7793.c
drivers/iio/adc/ad_sigma_delta.c
drivers/iio/adc/mcp320x.c
drivers/iio/adc/stm32-adc.c
drivers/iio/adc/ti-ads1015.c
drivers/iio/adc/twl4030-madc.c
drivers/iio/common/st_sensors/st_sensors_core.c
drivers/iio/industrialio-core.c
drivers/iio/magnetometer/st_magn_core.c
drivers/iio/pressure/bmp280-core.c
drivers/iio/trigger/stm32-timer-trigger.c
drivers/infiniband/core/iwpm_msg.c
drivers/infiniband/core/iwpm_util.c
drivers/infiniband/hw/i40iw/i40iw_ctrl.c
drivers/infiniband/hw/i40iw/i40iw_p.h
drivers/infiniband/hw/i40iw/i40iw_puda.c
drivers/infiniband/hw/i40iw/i40iw_verbs.c
drivers/infiniband/hw/mlx5/main.c
drivers/infiniband/hw/qedr/qedr.h
drivers/infiniband/hw/qedr/qedr_cm.c
drivers/md/bcache/closure.c
drivers/md/dm-core.h
drivers/md/dm-crypt.c
drivers/md/dm-ioctl.c
drivers/md/dm-raid.c
drivers/md/dm.c
drivers/media/rc/ir-sharp-decoder.c
drivers/misc/cxl/cxllib.c
drivers/net/dsa/mv88e6xxx/chip.c
drivers/net/ethernet/aquantia/atlantic/aq_cfg.h
drivers/net/ethernet/aquantia/atlantic/aq_nic.c
drivers/net/ethernet/aquantia/atlantic/aq_nic.h
drivers/net/ethernet/aquantia/atlantic/aq_ring.c
drivers/net/ethernet/aquantia/atlantic/aq_ring.h
drivers/net/ethernet/aquantia/atlantic/aq_vec.c
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
drivers/net/ethernet/broadcom/cnic.c
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
drivers/net/ethernet/marvell/mvpp2.c
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h
drivers/net/ethernet/mellanox/mlx5/core/en_fs.c
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c
drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.h
drivers/net/ethernet/mellanox/mlx5/core/fpga/core.c
drivers/net/ethernet/mellanox/mlx5/core/fs_cmd.c
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
drivers/net/ethernet/mellanox/mlx5/core/sriov.c
drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
drivers/net/ethernet/qualcomm/emac/emac-mac.c
drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c
drivers/net/ethernet/rocker/rocker_tlv.h
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
drivers/net/ppp/ppp_generic.c
drivers/net/tun.c
drivers/net/usb/cdc_ether.c
drivers/net/usb/r8152.c
drivers/net/usb/rndis_host.c
drivers/net/wireless/ath/ath10k/pci.c
drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c
drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwil_types.h
drivers/net/wireless/intel/iwlwifi/mvm/d3.c
drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c
drivers/net/wireless/intel/iwlwifi/mvm/rs.c
drivers/net/wireless/intel/iwlwifi/mvm/rxmq.c
drivers/net/wireless/intel/iwlwifi/mvm/scan.c
drivers/net/wireless/intel/iwlwifi/mvm/sta.c
drivers/net/wireless/intel/iwlwifi/mvm/sta.h
drivers/net/wireless/intel/iwlwifi/mvm/tt.c
drivers/net/wireless/intel/iwlwifi/mvm/tx.c
drivers/net/wireless/quantenna/qtnfmac/cfg80211.c
drivers/net/wireless/quantenna/qtnfmac/cfg80211.h
drivers/net/wireless/quantenna/qtnfmac/event.c
drivers/net/wireless/quantenna/qtnfmac/pearl/pcie.c
drivers/net/wireless/quantenna/qtnfmac/pearl/pcie_bus_priv.h
drivers/nvme/host/core.c
drivers/nvme/host/pci.c
drivers/nvmem/core.c
drivers/rapidio/devices/tsi721.c
drivers/rapidio/rio-access.c
drivers/reset/Kconfig
drivers/reset/Makefile
drivers/reset/reset-hsdk.c [moved from drivers/reset/reset-hsdk-v1.c with 72% similarity]
drivers/staging/iio/adc/ad7192.c
drivers/staging/mt29f_spinand/mt29f_spinand.c
drivers/staging/pi433/rf69.c
drivers/staging/rtl8723bs/core/rtw_mlme.c
drivers/staging/rtl8723bs/os_dep/rtw_proc.c
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx.c
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_func_88xx.c
drivers/staging/speakup/main.c
drivers/staging/unisys/visorbus/visorchipset.c
drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
drivers/tty/mxser.c
drivers/tty/serial/bcm63xx_uart.c
drivers/tty/serial/fsl_lpuart.c
drivers/tty/serial/sccnxp.c
drivers/usb/class/cdc-wdm.c
drivers/usb/core/config.c
drivers/usb/core/devio.c
drivers/usb/core/hub.c
drivers/usb/core/message.c
drivers/usb/dwc3/dwc3-of-simple.c
drivers/usb/dwc3/ep0.c
drivers/usb/gadget/function/f_fs.c
drivers/usb/gadget/function/f_mass_storage.c
drivers/usb/gadget/function/f_mass_storage.h
drivers/usb/gadget/function/f_printer.c
drivers/usb/gadget/function/u_fs.h
drivers/usb/gadget/legacy/inode.c
drivers/usb/gadget/legacy/mass_storage.c
drivers/usb/gadget/udc/Kconfig
drivers/usb/gadget/udc/atmel_usba_udc.c
drivers/usb/gadget/udc/core.c
drivers/usb/gadget/udc/dummy_hcd.c
drivers/usb/gadget/udc/renesas_usb3.c
drivers/usb/host/pci-quirks.c
drivers/usb/host/xhci-hub.c
drivers/usb/host/xhci-pci.c
drivers/usb/host/xhci-plat.c
drivers/usb/host/xhci.c
drivers/usb/host/xhci.h
drivers/usb/renesas_usbhs/fifo.c
drivers/usb/storage/transport.c
drivers/usb/storage/uas-detect.h
drivers/usb/storage/uas.c
drivers/usb/storage/unusual_devs.h
drivers/uwb/hwa-rc.c
drivers/uwb/uwbd.c
fs/binfmt_misc.c
fs/binfmt_script.c
fs/btrfs/ctree.h
fs/btrfs/extent_io.c
fs/ceph/mds_client.c
fs/ceph/snap.c
fs/exec.c
fs/namespace.c
fs/overlayfs/copy_up.c
fs/overlayfs/dir.c
fs/overlayfs/namei.c
fs/overlayfs/overlayfs.h
fs/overlayfs/ovl_entry.h
fs/overlayfs/readdir.c
fs/overlayfs/super.c
fs/overlayfs/util.c
fs/userfaultfd.c
fs/xattr.c
fs/xfs/xfs_bmap_util.c
fs/xfs/xfs_reflink.c
include/asm-generic/percpu.h
include/dt-bindings/reset/snps,hsdk-reset.h [new file with mode: 0644]
include/dt-bindings/reset/snps,hsdk-v1-reset.h [deleted file]
include/linux/binfmts.h
include/linux/bitfield.h
include/linux/device.h
include/linux/fs.h
include/linux/iio/adc/ad_sigma_delta.h
include/linux/mlx5/device.h
include/linux/mlx5/driver.h
include/linux/mlx5/mlx5_ifc.h
include/linux/mm.h
include/linux/mmu_notifier.h
include/linux/mmzone.h
include/linux/nmi.h
include/linux/sched/mm.h
include/linux/smpboot.h
include/net/netlink.h
include/net/protocol.h
include/net/route.h
include/net/tcp.h
include/net/udp.h
include/sound/hda_verbs.h
include/uapi/linux/bpf.h
include/uapi/linux/dm-ioctl.h
include/uapi/linux/usb/ch9.h
kernel/bpf/core.c
kernel/cgroup/cgroup.c
kernel/cpu.c
kernel/fork.c
kernel/kcmp.c
kernel/memremap.c
kernel/params.c
kernel/power/suspend.c
kernel/rcu/tree.c
kernel/smpboot.c
kernel/sysctl.c
kernel/trace/ftrace.c
kernel/watchdog.c
kernel/watchdog_hld.c
lib/idr.c
lib/kobject_uevent.c
lib/lz4/lz4_decompress.c
lib/ratelimit.c
mm/compaction.c
mm/filemap.c
mm/ksm.c
mm/list_lru.c
mm/madvise.c
mm/memcontrol.c
mm/memory.c
mm/memory_hotplug.c
mm/oom_kill.c
mm/page_alloc.c
mm/percpu-stats.c
mm/percpu.c
mm/rodata_test.c
mm/slab_common.c
mm/swap.c
mm/swap_state.c
mm/z3fold.c
net/8021q/vlan_core.c
net/core/filter.c
net/core/rtnetlink.c
net/core/sock.c
net/dsa/slave.c
net/ipv4/inetpeer.c
net/ipv4/ip_gre.c
net/ipv4/ip_input.c
net/ipv4/ip_vti.c
net/ipv4/route.c
net/ipv4/tcp_ipv4.c
net/ipv4/udp.c
net/ipv6/ip6_gre.c
net/ipv6/ip6_tunnel.c
net/ipv6/ip6_vti.c
net/l2tp/l2tp_core.c
net/l2tp/l2tp_core.h
net/l2tp/l2tp_eth.c
net/l2tp/l2tp_ppp.c
net/netlink/af_netlink.c
net/packet/af_packet.c
net/sctp/sctp_diag.c
net/tipc/msg.c
scripts/checkpatch.pl
scripts/spelling.txt
security/smack/smack_lsm.c
sound/core/compress_offload.c
sound/core/pcm_compat.c
sound/pci/asihpi/hpioctl.c
sound/pci/echoaudio/echoaudio.c
sound/pci/hda/patch_hdmi.c
sound/usb/card.c
sound/usb/quirks.c
sound/usb/usx2y/usb_stream.c

index 5273cfd70ad62996ba8374698fb5e22e91d33f45..c7b10caecc4ee24a17f14be238c301391451f0b3 100644 (file)
--- a/.mailmap
+++ b/.mailmap
@@ -68,6 +68,8 @@ Jacob Shin <Jacob.Shin@amd.com>
 James Bottomley <jejb@mulgrave.(none)>
 James Bottomley <jejb@titanic.il.steeleye.com>
 James E Wilson <wilson@specifix.com>
+James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
+James Hogan <jhogan@kernel.org> <james@albanarts.com>
 James Ketrenos <jketreno@io.(none)>
 Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
 <javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
index 713cab1d5f12dca9baaa68f9ca053a4ab90d7ab0..a1d1612f36519f832c2d307293527083cf025271 100644 (file)
@@ -127,7 +127,7 @@ Description:
 
 What;          /sys/power/pm_trace_dev_match
 Date:          October 2010
-Contact:       James Hogan <james@albanarts.com>
+Contact:       James Hogan <jhogan@kernel.org>
 Description:
                The /sys/power/pm_trace_dev_match file contains the name of the
                device associated with the last PM event point saved in the RTC
index 3943b5bfa8cffacc8b760db0f94dfce636cb957f..00a5ba51e63fb79803e01539cc9f40dcd757c9e4 100644 (file)
@@ -39,8 +39,8 @@ up.
 Although MT wq wasted a lot of resource, the level of concurrency
 provided was unsatisfactory.  The limitation was common to both ST and
 MT wq albeit less severe on MT.  Each wq maintained its own separate
-worker pool.  A MT wq could provide only one execution context per CPU
-while a ST wq one for the whole system.  Work items had to compete for
+worker pool.  An MT wq could provide only one execution context per CPU
+while an ST wq one for the whole system.  Work items had to compete for
 those very limited execution contexts leading to various problems
 including proneness to deadlocks around the single execution context.
 
@@ -151,7 +151,7 @@ Application Programming Interface (API)
 
 ``alloc_workqueue()`` allocates a wq.  The original
 ``create_*workqueue()`` functions are deprecated and scheduled for
-removal.  ``alloc_workqueue()`` takes three arguments - @``name``,
+removal.  ``alloc_workqueue()`` takes three arguments - ``@name``,
 ``@flags`` and ``@max_active``.  ``@name`` is the name of the wq and
 also used as the name of the rescuer thread if there is one.
 
@@ -197,7 +197,7 @@ resources, scheduled and executed.
   served by worker threads with elevated nice level.
 
   Note that normal and highpri worker-pools don't interact with
-  each other.  Each maintain its separate pool of workers and
+  each other.  Each maintains its separate pool of workers and
   implements concurrency management among its workers.
 
 ``WQ_CPU_INTENSIVE``
@@ -249,8 +249,8 @@ unbound worker-pools and only one work item could be active at any given
 time thus achieving the same ordering property as ST wq.
 
 In the current implementation the above configuration only guarantees
-ST behavior within a given NUMA node. Instead alloc_ordered_queue should
-be used to achieve system wide ST behavior.
+ST behavior within a given NUMA node. Instead ``alloc_ordered_queue()`` should
+be used to achieve system-wide ST behavior.
 
 
 Example Execution Scenarios
index 4a0a7469fdd7bbcd93e26ea5ae9c11e4285f7c7f..32df07e29f6860d4c1de9e3c3c63d2b4d0fc454f 100644 (file)
@@ -344,3 +344,4 @@ Version History
        (wrong raid10_copies/raid10_format sequence)
 1.11.1  Add raid4/5/6 journal write-back support via journal_mode option
 1.12.1  fix for MD deadlock between mddev_suspend() and md_write_start() available
+1.13.0  Fix dev_health status at end of "recover" (was 'a', now 'A')
index 7e2dad08a12e92c1baa0290116cbd032f5bb1e88..1814fa13f6ab8078a52a32fa2a55156124d696bb 100644 (file)
@@ -21,8 +21,9 @@ Required properties:
        - main controller clock (for both armada-375-pp2 and armada-7k-pp2)
        - GOP clock (for both armada-375-pp2 and armada-7k-pp2)
        - MG clock (only for armada-7k-pp2)
-- clock-names: names of used clocks, must be "pp_clk", "gop_clk" and
-  "mg_clk" (the latter only for armada-7k-pp2).
+       - AXI clock (only for armada-7k-pp2)
+- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
+  and "axi_clk" (the 2 latter only for armada-7k-pp2).
 
 The ethernet ports are represented by subnodes. At least one port is
 required.
@@ -78,8 +79,9 @@ Example for marvell,armada-7k-pp2:
 cpm_ethernet: ethernet@0 {
        compatible = "marvell,armada-7k-pp22";
        reg = <0x0 0x100000>, <0x129000 0xb000>;
-       clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
-       clock-names = "pp_clk", "gop_clk", "gp_clk";
+       clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
+                <&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
+       clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
 
        eth0: eth0 {
                interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
index 6af8eed1adeb1429cf9bdda435ac4e7ab27c5c21..9c16ee2965a2ce756acc23d6956fedc38157144b 100644 (file)
@@ -4,6 +4,7 @@ The device node has following properties.
 
 Required properties:
  - compatible: should be "rockchip,<name>-gamc"
+   "rockchip,rk3128-gmac": found on RK312x SoCs
    "rockchip,rk3228-gmac": found on RK322x SoCs
    "rockchip,rk3288-gmac": found on RK3288 SoCs
    "rockchip,rk3328-gmac": found on RK3328 SoCs
diff --git a/Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt b/Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt
new file mode 100644 (file)
index 0000000..830069b
--- /dev/null
@@ -0,0 +1,28 @@
+Binding for the Synopsys HSDK reset controller
+
+This binding uses the common reset binding[1].
+
+[1] Documentation/devicetree/bindings/reset/reset.txt
+
+Required properties:
+- compatible: should be "snps,hsdk-reset".
+- reg: should always contain 2 pairs address - length: first for reset
+  configuration register and second for corresponding SW reset and status bits
+  register.
+- #reset-cells: from common reset binding; Should always be set to 1.
+
+Example:
+       reset: reset@880 {
+               compatible = "snps,hsdk-reset";
+               #reset-cells = <1>;
+               reg = <0x8A0 0x4>, <0xFF0 0x4>;
+       };
+
+Specifying reset lines connected to IP modules:
+       ethernet@.... {
+               ....
+               resets = <&reset HSDK_V1_ETH_RESET>;
+               ....
+       };
+
+The index could be found in <dt-bindings/reset/snps,hsdk-reset.h>
index 4fc96946f81d6afc781f7007eaa9dd945f52ed52..cf504d0380aeb9d0749cc2ab1f90e2f35a781146 100644 (file)
@@ -41,6 +41,8 @@ Required properties:
     - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
     - "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
     - "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
+    - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
+    - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
     - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
     - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
     - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
index 4421135826a2e5fb8526288afa06473cb2137027..d661e6f7e6a0cb6b161e30ab1ad800bc8bd581f6 100644 (file)
@@ -196,12 +196,13 @@ struct driver_attribute {
 };
 
 Device drivers can export attributes via their sysfs directories. 
-Drivers can declare attributes using a DRIVER_ATTR macro that works
-identically to the DEVICE_ATTR macro. 
+Drivers can declare attributes using a DRIVER_ATTR_RW and DRIVER_ATTR_RO
+macro that works identically to the DEVICE_ATTR_RW and DEVICE_ATTR_RO
+macros.
 
 Example:
 
-DRIVER_ATTR(debug,0644,show_debug,store_debug);
+DRIVER_ATTR_RW(debug);
 
 This is equivalent to declaring:
 
index 36f528a7fdd64d18c7ee7b3a50849b45bc046ef3..8caa60734647f70a777b8a568ba9f2dd99182fb8 100644 (file)
@@ -210,8 +210,11 @@ path as another overlay mount and it may use a lower layer path that is
 beneath or above the path of another overlay lower layer path.
 
 Using an upper layer path and/or a workdir path that are already used by
-another overlay mount is not allowed and will fail with EBUSY.  Using
+another overlay mount is not allowed and may fail with EBUSY.  Using
 partially overlapping paths is not allowed but will not fail with EBUSY.
+If files are accessed from two overlayfs mounts which share or overlap the
+upper layer and/or workdir path the behavior of the overlay is undefined,
+though it will not result in a crash or deadlock.
 
 Mounting an overlay using an upper layer path, where the upper layer path
 was previously used by another mounted overlay in combination with a
index 24da7b32c489fd65408dbd8b33f7bc0402ddba0b..9a3658cc399ed459f1e21d613dbf8e5b1b2bc647 100644 (file)
@@ -366,7 +366,8 @@ struct driver_attribute {
 
 Declaring:
 
-DRIVER_ATTR(_name, _mode, _show, _store)
+DRIVER_ATTR_RO(_name)
+DRIVER_ATTR_RW(_name)
 
 Creation/Removal:
 
index 65b0c88d5ee0d292914b85c9ba45b1fee5f466ff..2d3d750b19c0cddf8af39786faed78709f7bbba1 100644 (file)
@@ -5259,7 +5259,8 @@ S:        Maintained
 F:     drivers/iommu/exynos-iommu.c
 
 EZchip NPS platform support
-M:     Noam Camus <noamc@ezchip.com>
+M:     Elad Kanfi <eladkan@mellanox.com>
+M:     Vineet Gupta <vgupta@synopsys.com>
 S:     Supported
 F:     arch/arc/plat-eznps
 F:     arch/arc/boot/dts/eznps.dts
@@ -6738,7 +6739,7 @@ F:        Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
 F:     drivers/auxdisplay/img-ascii-lcd.c
 
 IMGTEC IR DECODER DRIVER
-M:     James Hogan <james.hogan@imgtec.com>
+M:     James Hogan <jhogan@kernel.org>
 S:     Maintained
 F:     drivers/media/rc/img-ir/
 
@@ -7562,7 +7563,7 @@ F:        arch/arm64/include/asm/kvm*
 F:     arch/arm64/kvm/
 
 KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
-M:     James Hogan <james.hogan@imgtec.com>
+M:     James Hogan <jhogan@kernel.org>
 L:     linux-mips@linux-mips.org
 S:     Supported
 F:     arch/mips/include/uapi/asm/kvm*
@@ -8264,6 +8265,12 @@ L:       libertas-dev@lists.infradead.org
 S:     Orphan
 F:     drivers/net/wireless/marvell/libertas/
 
+MARVELL MACCHIATOBIN SUPPORT
+M:     Russell King <rmk@armlinux.org.uk>
+L:     linux-arm-kernel@lists.infradead.org
+S:     Maintained
+F:     arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+
 MARVELL MV643XX ETHERNET DRIVER
 M:     Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 L:     netdev@vger.kernel.org
@@ -8885,7 +8892,7 @@ F:        Documentation/devicetree/bindings/media/meson-ao-cec.txt
 T:     git git://linuxtv.org/media_tree.git
 
 METAG ARCHITECTURE
-M:     James Hogan <james.hogan@imgtec.com>
+M:     James Hogan <jhogan@kernel.org>
 L:     linux-metag@vger.kernel.org
 T:     git git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag.git
 S:     Odd Fixes
@@ -9354,7 +9361,7 @@ NETWORK BLOCK DEVICE (NBD)
 M:     Josef Bacik <jbacik@fb.com>
 S:     Maintained
 L:     linux-block@vger.kernel.org
-L:     nbd-general@lists.sourceforge.net
+L:     nbd@other.debian.org
 F:     Documentation/blockdev/nbd.txt
 F:     drivers/block/nbd.c
 F:     include/uapi/linux/nbd.h
@@ -12931,9 +12938,9 @@ F:      drivers/mmc/host/dw_mmc*
 SYNOPSYS HSDK RESET CONTROLLER DRIVER
 M:     Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:     Supported
-F:     drivers/reset/reset-hsdk-v1.c
-F:     include/dt-bindings/reset/snps,hsdk-v1-reset.h
-F:     Documentation/devicetree/bindings/reset/snps,hsdk-v1-reset.txt
+F:     drivers/reset/reset-hsdk.c
+F:     include/dt-bindings/reset/snps,hsdk-reset.h
+F:     Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt
 
 SYSTEM CONFIGURATION (SYSCON)
 M:     Lee Jones <lee.jones@linaro.org>
index 384bd47b5187179f4e40ee63399117c14f40eb0d..45c020a0fe76114688c4a77f1a1f574049821341 100644 (file)
@@ -8,6 +8,7 @@
  */
 
 #include <linux/mm_types.h>
+#include <linux/sched.h>
 
 #include <asm/machvec.h>
 #include <asm/compiler.h>
index a598641eed98ef4d60dc65a25a4279a70be7e134..c84e67fdea095cbed225edac052f4ce07007abb9 100644 (file)
@@ -24,7 +24,7 @@ config ARC
        select GENERIC_SMP_IDLE_THREAD
        select HAVE_ARCH_KGDB
        select HAVE_ARCH_TRACEHOOK
-       select HAVE_FUTEX_CMPXCHG
+       select HAVE_FUTEX_CMPXCHG if FUTEX
        select HAVE_IOREMAP_PROT
        select HAVE_KPROBES
        select HAVE_KRETPROBES
index 3a4b52b7e09d61456daf12335e7e5b7c75ec7077..d37f49d6a27f40f65d3e34bd3e2df5343a97d1e4 100644 (file)
@@ -6,8 +6,6 @@
 # published by the Free Software Foundation.
 #
 
-UTS_MACHINE := arc
-
 ifeq ($(CROSS_COMPILE),)
 ifndef CONFIG_CPU_BIG_ENDIAN
 CROSS_COMPILE := arc-linux-
index 2367a67c5f10bd3e99ce757dafed25dfa95ecb35..e114000a84f56c9e07ddd3a2e623c4dfeb3df6a2 100644 (file)
 
                        mmcclk: mmcclk {
                                compatible = "fixed-clock";
-                               clock-frequency = <50000000>;
+                               /*
+                                * DW sdio controller has external ciu clock divider
+                                * controlled via register in SDIO IP. It divides
+                                * sdio_ref_clk (which comes from CGU) by 16 for
+                                * default. So default mmcclk clock (which comes
+                                * to sdk_in) is 25000000 Hz.
+                                */
+                               clock-frequency = <25000000>;
                                #clock-cells = <0>;
                        };
 
index 229d13adbce426c1690684f7e8dcb344a001429d..8adde1b492f14e833279ff75f448b7c0bb350781 100644 (file)
@@ -12,6 +12,7 @@
 /dts-v1/;
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/reset/snps,hsdk-reset.h>
 
 / {
        model = "snps,hsdk";
                };
        };
 
-       core_clk: core-clk {
+       input_clk: input-clk {
                #clock-cells = <0>;
                compatible = "fixed-clock";
-               clock-frequency = <500000000>;
+               clock-frequency = <33333333>;
        };
 
        cpu_intc: cpu-interrupt-controller {
 
                ranges = <0x00000000 0xf0000000 0x10000000>;
 
+               cgu_rst: reset-controller@8a0 {
+                       compatible = "snps,hsdk-reset";
+                       #reset-cells = <1>;
+                       reg = <0x8A0 0x4>, <0xFF0 0x4>;
+               };
+
+               core_clk: core-clk@0 {
+                       compatible = "snps,hsdk-core-pll-clock";
+                       reg = <0x00 0x10>, <0x14B8 0x4>;
+                       #clock-cells = <0>;
+                       clocks = <&input_clk>;
+               };
+
                serial: serial@5000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x5000 0x100>;
 
                mmcclk_ciu: mmcclk-ciu {
                        compatible = "fixed-clock";
-                       clock-frequency = <100000000>;
+                       /*
+                        * DW sdio controller has external ciu clock divider
+                        * controlled via register in SDIO IP. Due to its
+                        * unexpected default value (it should devide by 1
+                        * but it devides by 8) SDIO IP uses wrong clock and
+                        * works unstable (see STAR 9001204800)
+                        * So add temporary fix and change clock frequency
+                        * from 100000000 to 12500000 Hz until we fix dw sdio
+                        * driver itself.
+                        */
+                       clock-frequency = <12500000>;
                        #clock-cells = <0>;
                };
 
                        clocks = <&gmacclk>;
                        clock-names = "stmmaceth";
                        phy-handle = <&phy0>;
+                       resets = <&cgu_rst HSDK_ETH_RESET>;
+                       reset-names = "stmmaceth";
 
                        mdio {
                                #address-cells = <1>;
index 6980b966a36403b6170130fa1389ea9fb66095b8..ec7c849a5c8e9887fbd60acf176f194cc0c4ba03 100644 (file)
@@ -105,7 +105,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
index 2233f5777a71f82cb5defb9ae99bbfc11772fdac..63d3cf69e0b02efe45fca035649951836fc1e948 100644 (file)
@@ -104,7 +104,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
index 30a3d4cf53d20af6f202a61e3f5a980e7f1e7c2e..f613ecac14a750e6008dc817d3a06727a4631989 100644 (file)
@@ -107,7 +107,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
index 821a2e562f3f12422844556630d7136ad63097a8..3507be2af6fe3684f4acca6de7009903da82b97e 100644 (file)
@@ -84,5 +84,5 @@ CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 # CONFIG_DEBUG_PREEMPT is not set
index 9a3fcf44638820d905895b2bf0ba5a6f18511f4c..15f0f6b5fec1ae6f8e0c1bfb4fa6c970915e1713 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_HSDK=y
 CONFIG_EXT3_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
@@ -72,7 +73,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
index c0d6a010751a9f80e4139fa6a9b833de4b24b6a8..4fcf4f2503f61a9e802b82e2cbb4aad9617725d8 100644 (file)
@@ -94,7 +94,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_SHIRQ=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
index 5c0971787acf4c18066c4bc537f36c1dae37232f..7b71464f6c2f2904e18893d8ba80c65471fc4ef5 100644 (file)
@@ -98,7 +98,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_SHIRQ=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
index ba8e802dba80bd0776508ff70945e6e8b54ea43e..b1c56d35f2a938e59c9677454499aeecb1da4f7e 100644 (file)
@@ -98,6 +98,7 @@
 
 /* Auxiliary registers */
 #define AUX_IDENTITY           4
+#define AUX_EXEC_CTRL          8
 #define AUX_INTR_VEC_BASE      0x25
 #define AUX_VOL                        0x5e
 
@@ -135,12 +136,12 @@ struct bcr_identity {
 #endif
 };
 
-struct bcr_isa {
+struct bcr_isa_arcv2 {
 #ifdef CONFIG_CPU_BIG_ENDIAN
        unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
-                    pad1:11, atomic1:1, ver:8;
+                    pad1:12, ver:8;
 #else
-       unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
+       unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
                     ldd:1, pad2:4, div_rem:4;
 #endif
 };
@@ -263,13 +264,13 @@ struct cpuinfo_arc {
        struct cpuinfo_arc_mmu mmu;
        struct cpuinfo_arc_bpu bpu;
        struct bcr_identity core;
-       struct bcr_isa isa;
+       struct bcr_isa_arcv2 isa;
        const char *details, *name;
        unsigned int vec_base;
        struct cpuinfo_arc_ccm iccm, dccm;
        struct {
                unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
-                            fpu_sp:1, fpu_dp:1, pad2:6,
+                            fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
                             debug:1, ap:1, smart:1, rtt:1, pad3:4,
                             timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
        } extn;
index 877cec8f5ea21256e233f4f353882ff02097537a..fb83844daeea3550aacd27de2525711a6aa5fddc 100644 (file)
@@ -51,6 +51,7 @@ static const struct id_to_str arc_cpu_rel[] = {
        { 0x51, "R2.0" },
        { 0x52, "R2.1" },
        { 0x53, "R3.0" },
+       { 0x54, "R4.0" },
 #endif
        { 0x00, NULL   }
 };
@@ -62,6 +63,7 @@ static const struct id_to_str arc_cpu_nm[] = {
 #else
        { 0x40, "ARC EM"  },
        { 0x50, "ARC HS38"  },
+       { 0x54, "ARC HS48"  },
 #endif
        { 0x00, "Unknown"   }
 };
@@ -119,11 +121,11 @@ static void read_arc_build_cfg_regs(void)
        struct bcr_generic bcr;
        struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
        const struct id_to_str *tbl;
+       struct bcr_isa_arcv2 isa;
 
        FIX_PTR(cpu);
 
        READ_BCR(AUX_IDENTITY, cpu->core);
-       READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
 
        for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
                if (cpu->core.family == tbl->id) {
@@ -133,7 +135,7 @@ static void read_arc_build_cfg_regs(void)
        }
 
        for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
-               if ((cpu->core.family & 0xF0) == tbl->id)
+               if ((cpu->core.family & 0xF4) == tbl->id)
                        break;
        }
        cpu->name = tbl->str;
@@ -192,6 +194,14 @@ static void read_arc_build_cfg_regs(void)
                cpu->bpu.full = bpu.ft;
                cpu->bpu.num_cache = 256 << bpu.bce;
                cpu->bpu.num_pred = 2048 << bpu.pte;
+
+               if (cpu->core.family >= 0x54) {
+                       unsigned int exec_ctrl;
+
+                       READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
+                       cpu->extn.dual_iss_exist = 1;
+                       cpu->extn.dual_iss_enb = exec_ctrl & 1;
+               }
        }
 
        READ_BCR(ARC_REG_AP_BCR, bcr);
@@ -205,18 +215,25 @@ static void read_arc_build_cfg_regs(void)
 
        cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
 
+       READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
+
        /* some hacks for lack of feature BCR info in old ARC700 cores */
        if (is_isa_arcompact()) {
-               if (!cpu->isa.ver)      /* ISA BCR absent, use Kconfig info */
+               if (!isa.ver)   /* ISA BCR absent, use Kconfig info */
                        cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
-               else
-                       cpu->isa.atomic = cpu->isa.atomic1;
+               else {
+                       /* ARC700_BUILD only has 2 bits of isa info */
+                       struct bcr_generic bcr = *(struct bcr_generic *)&isa;
+                       cpu->isa.atomic = bcr.info & 1;
+               }
 
                cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 
                 /* there's no direct way to distinguish 750 vs. 770 */
                if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
                        cpu->name = "ARC750";
+       } else {
+               cpu->isa = isa;
        }
 }
 
@@ -232,10 +249,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
                       "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
                       core->family, core->cpu_id, core->chip_id);
 
-       n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",
+       n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
                       cpu_id, cpu->name, cpu->details,
                       is_isa_arcompact() ? "ARCompact" : "ARCv2",
-                      IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
+                      IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
+                      IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
 
        n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
                       IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
index f1ac6790da5fe64782b59b720bf3ea80d999bff1..cf14ebc36916a2a0eca39728c0cc0f315d58bbeb 100644 (file)
@@ -111,6 +111,13 @@ static void __init axs10x_early_init(void)
 
        axs10x_enable_gpio_intc_wire();
 
+       /*
+        * Reset ethernet IP core.
+        * TODO: get rid of this quirk after axs10x reset driver (or simple
+        * reset driver) will be available in upstream.
+        */
+       iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
+
        scnprintf(mb, 32, "MainBoard v%d", mb_rev);
        axs10x_print_board_ver(CREG_MB_VER, mb);
 }
index 5a6ed5afb009a160e617a5e2fd81f1be6f56fcd3..bd08de4be75e7edc4ce8875c8af7f1723f0f5b01 100644 (file)
@@ -6,4 +6,5 @@
 #
 
 menuconfig ARC_SOC_HSDK
-       bool "ARC HS Development Kit SOC"
+       bool "ARC HS Development Kit SOC"
+       select CLK_HSDK
index a2e7fd17e36d36a4e0f29c183834ae349e5a8786..744e62e5878898b21f49c58c588ddb167523cc60 100644 (file)
@@ -38,6 +38,42 @@ static void __init hsdk_init_per_cpu(unsigned int cpu)
 #define CREG_PAE               (CREG_BASE + 0x180)
 #define CREG_PAE_UPDATE                (CREG_BASE + 0x194)
 
+#define CREG_CORE_IF_CLK_DIV   (CREG_BASE + 0x4B8)
+#define CREG_CORE_IF_CLK_DIV_2 0x1
+#define CGU_BASE               ARC_PERIPHERAL_BASE
+#define CGU_PLL_STATUS         (ARC_PERIPHERAL_BASE + 0x4)
+#define CGU_PLL_CTRL           (ARC_PERIPHERAL_BASE + 0x0)
+#define CGU_PLL_STATUS_LOCK    BIT(0)
+#define CGU_PLL_STATUS_ERR     BIT(1)
+#define CGU_PLL_CTRL_1GHZ      0x3A10
+#define HSDK_PLL_LOCK_TIMEOUT  500
+
+#define HSDK_PLL_LOCKED() \
+       !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
+
+#define HSDK_PLL_ERR() \
+       !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
+
+static void __init hsdk_set_cpu_freq_1ghz(void)
+{
+       u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
+
+       /*
+        * As we set cpu clock which exceeds 500MHz, the divider for the interface
+        * clock must be programmed to div-by-2.
+        */
+       iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
+
+       /* Set cpu clock to 1GHz */
+       iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
+
+       while (!HSDK_PLL_LOCKED() && timeout--)
+               cpu_relax();
+
+       if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
+               pr_err("Failed to setup CPU frequency to 1GHz!");
+}
+
 static void __init hsdk_init_early(void)
 {
        /*
@@ -52,6 +88,12 @@ static void __init hsdk_init_early(void)
 
        /* Really apply settings made above */
        writel(1, (void __iomem *) CREG_PAE_UPDATE);
+
+       /*
+        * Setup CPU frequency to 1GHz.
+        * TODO: remove it after smart hsdk pll driver will be introduced.
+        */
+       hsdk_set_cpu_freq_1ghz();
 }
 
 static const char *hsdk_compat[] __initconst = {
index 7d7ca054c557b4b66e5da847c53e6c20fd36cd5b..e58fab8aec5df2a885ea8c04f9eefda09cf2d307 100644 (file)
@@ -36,6 +36,8 @@
                phy1 = &usb1_phy;
                ethernet0 = &cpsw_emac0;
                ethernet1 = &cpsw_emac1;
+               spi0 = &spi0;
+               spi1 = &spi1;
        };
 
        cpus {
index 9d276af7c539f3dd1cb382f12d4bca7d9bd2fb3d..081fa68b6f98049ad2edb1c9c6d579c0958a7a2d 100644 (file)
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
        status = "okay";
+       slaves = <1>;
 };
 
 &davinci_mdio {
        phy-mode = "rmii";
 };
 
-&cpsw_emac1 {
-       phy_id = <&davinci_mdio>, <1>;
-       phy-mode = "rmii";
-};
-
 &phy_sel {
        rmii-clock-ext;
 };
index 9c9088c99cc4cdb36d963c61e648216ee7fc4c4c..60cb084a8d927e40303a377a40fd283d2eb29f45 100644 (file)
 
                usb1: ohci@00400000 {
                        num-ports = <3>;
-                       atmel,vbus-gpio = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
+                       atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */
+                                          &pioA PIN_PA27 GPIO_ACTIVE_HIGH
+                                          0
+                                         >;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_usb_default>;
                        status = "okay";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_mikrobus2_uart>;
                                atmel,use-dma-rx;
-                               atmel-use-dma-tx;
+                               atmel,use-dma-tx;
                                status = "okay";
                        };
 
                        uart4: serial@fc00c000 {
                                atmel,use-dma-rx;
                                atmel,use-dma-tx;
-                               pinctrl-name = "default";
+                               pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_mikrobus1_uart>;
                                status = "okay";
                        };
                                };
 
                                pinctrl_led_gpio_default: led_gpio_default {
-                                       pinmux = <PIN_PA27__GPIO>,
+                                       pinmux = <PIN_PA10__GPIO>,
                                                 <PIN_PB1__GPIO>,
                                                 <PIN_PA31__GPIO>;
                                        bias-pull-up;
                                };
 
                                pinctrl_usb_default: usb_default {
-                                       pinmux = <PIN_PA10__GPIO>,
+                                       pinmux = <PIN_PA27__GPIO>,
                                                 <PIN_PD19__GPIO>;
                                        bias-disable;
                                };
 
                red {
                        label = "red";
-                       gpios = <&pioA PIN_PA27 GPIO_ACTIVE_LOW>;
+                       gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
                };
 
                green {
                        label = "green";
-                       gpios = <&pioA PIN_PB1 GPIO_ACTIVE_LOW>;
+                       gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
                };
 
                blue {
                        label = "blue";
-                       gpios = <&pioA PIN_PA31 GPIO_ACTIVE_LOW>;
+                       gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                };
        };
index 67e72bc72e805be995b0d44fa68f74e29161b140..c75507922f7d7998ee0e45bb875b8b6495b3d8d7 100644 (file)
        compatible = "ti,da850-evm", "ti,da850";
        model = "DA850/AM1808/OMAP-L138 EVM";
 
+       aliases {
+               serial0 = &serial0;
+               serial1 = &serial1;
+               serial2 = &serial2;
+               ethernet0 = &eth0;
+       };
+
        soc@1c00000 {
                pmx_core: pinmux@14120 {
                        status = "okay";
index cf229dfabf6173872d23ea380a436109b5424caf..e62b62875cbad7ed97dd7f23c0f290a38839d3be 100644 (file)
                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x1868>;
+               assigned-clocks = <&mcasp3_ahclkx_mux>;
+               assigned-clock-parents = <&abe_24m_fclk>;
        };
 
        mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
index 26c20e1167b9531ca1fde008787a714856b67c62..4acd32a1c4ef7c8801bbd516f2f317d50db21218 100644 (file)
                io-channel-names = "temp", "bsi", "vbat";
        };
 
-       rear_camera: camera@0 {
-               compatible = "linux,camera";
-
-               module {
-                       model = "TCM8341MD";
-                       sensor = <&cam1>;
-               };
-       };
-
        pwm9: dmtimer-pwm {
                compatible = "ti,omap-dmtimer-pwm";
                #pwm-cells = <3>;
                                clock-lanes = <1>;
                                data-lanes = <0>;
                                lane-polarity = <0 0>;
-                               clock-inv = <0>;
                                /* Select strobe = <1> for back camera, <0> for front camera */
                                strobe = <1>;
-                               crc = <0>;
                        };
                };
        };
index 97b1c2321ba9dd4f7791213b47beaeb740d6542f..293ecb95722715d6ec4dc36da07496134f51a631 100644 (file)
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include "stm32f429-pinctrl.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 
        stmpe1600: stmpe1600@42 {
                compatible = "st,stmpe1600";
                reg = <0x42>;
-               irq-gpio = <&gpioi 8 0>;
-               irq-trigger = <3>;
                interrupts = <8 3>;
-               interrupt-parent = <&exti>;
+               interrupt-parent = <&gpioi>;
                interrupt-controller;
                wakeup-source;
 
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..7f3560c
--- /dev/null
@@ -0,0 +1,343 @@
+/*
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
+
+/ {
+       soc {
+               pinctrl: pin-controller {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x40020000 0x3000>;
+                       interrupt-parent = <&exti>;
+                       st,syscfg = <&syscfg 0x8>;
+                       pins-are-numbered;
+
+                       gpioa: gpio@40020000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x0 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
+                               st,bank-name = "GPIOA";
+                       };
+
+                       gpiob: gpio@40020400 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x400 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
+                               st,bank-name = "GPIOB";
+                       };
+
+                       gpioc: gpio@40020800 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x800 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
+                               st,bank-name = "GPIOC";
+                       };
+
+                       gpiod: gpio@40020c00 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0xc00 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
+                               st,bank-name = "GPIOD";
+                       };
+
+                       gpioe: gpio@40021000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x1000 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
+                               st,bank-name = "GPIOE";
+                       };
+
+                       gpiof: gpio@40021400 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x1400 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
+                               st,bank-name = "GPIOF";
+                       };
+
+                       gpiog: gpio@40021800 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x1800 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
+                               st,bank-name = "GPIOG";
+                       };
+
+                       gpioh: gpio@40021c00 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x1c00 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
+                               st,bank-name = "GPIOH";
+                       };
+
+                       gpioi: gpio@40022000 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x2000 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
+                               st,bank-name = "GPIOI";
+                       };
+
+                       gpioj: gpio@40022400 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x2400 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
+                               st,bank-name = "GPIOJ";
+                       };
+
+                       gpiok: gpio@40022800 {
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               reg = <0x2800 0x400>;
+                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
+                               st,bank-name = "GPIOK";
+                       };
+
+                       usart1_pins_a: usart1@0 {
+                               pins1 {
+                                       pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <0>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
+                                       bias-disable;
+                               };
+                       };
+
+                       usart3_pins_a: usart3@0 {
+                               pins1 {
+                                       pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <0>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
+                                       bias-disable;
+                               };
+                       };
+
+                       usbotg_fs_pins_a: usbotg_fs@0 {
+                               pins {
+                                       pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
+                                                <STM32F429_PA11_FUNC_OTG_FS_DM>,
+                                                <STM32F429_PA12_FUNC_OTG_FS_DP>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                       };
+
+                       usbotg_fs_pins_b: usbotg_fs@1 {
+                               pins {
+                                       pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
+                                                <STM32F429_PB14_FUNC_OTG_HS_DM>,
+                                                <STM32F429_PB15_FUNC_OTG_HS_DP>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                       };
+
+                       usbotg_hs_pins_a: usbotg_hs@0 {
+                               pins {
+                                       pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
+                                                <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
+                                                <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
+                                                <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
+                                                <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
+                                                <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
+                                                <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
+                                                <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
+                                                <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
+                                                <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
+                                                <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
+                                                <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <2>;
+                               };
+                       };
+
+                       ethernet_mii: mii@0 {
+                               pins {
+                                       pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+                                                <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+                                                <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
+                                                <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
+                                                <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
+                                                <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+                                                <STM32F429_PA2_FUNC_ETH_MDIO>,
+                                                <STM32F429_PC1_FUNC_ETH_MDC>,
+                                                <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+                                                <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+                                                <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+                                                <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
+                                                <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
+                                                <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
+                                       slew-rate = <2>;
+                               };
+                       };
+
+                       adc3_in8_pin: adc@200 {
+                               pins {
+                                       pinmux = <STM32F429_PF10_FUNC_ANALOG>;
+                               };
+                       };
+
+                       pwm1_pins: pwm@1 {
+                               pins {
+                                       pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
+                                                <STM32F429_PB13_FUNC_TIM1_CH1N>,
+                                                <STM32F429_PB12_FUNC_TIM1_BKIN>;
+                               };
+                       };
+
+                       pwm3_pins: pwm@3 {
+                               pins {
+                                       pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
+                                                <STM32F429_PB5_FUNC_TIM3_CH2>;
+                               };
+                       };
+
+                       i2c1_pins: i2c1@0 {
+                               pins {
+                                       pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
+                                                <STM32F429_PB6_FUNC_I2C1_SCL>;
+                                       bias-disable;
+                                       drive-open-drain;
+                                       slew-rate = <3>;
+                               };
+                       };
+
+                       ltdc_pins: ltdc@0 {
+                               pins {
+                                       pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
+                                                <STM32F429_PI13_FUNC_LCD_VSYNC>,
+                                                <STM32F429_PI14_FUNC_LCD_CLK>,
+                                                <STM32F429_PI15_FUNC_LCD_R0>,
+                                                <STM32F429_PJ0_FUNC_LCD_R1>,
+                                                <STM32F429_PJ1_FUNC_LCD_R2>,
+                                                <STM32F429_PJ2_FUNC_LCD_R3>,
+                                                <STM32F429_PJ3_FUNC_LCD_R4>,
+                                                <STM32F429_PJ4_FUNC_LCD_R5>,
+                                                <STM32F429_PJ5_FUNC_LCD_R6>,
+                                                <STM32F429_PJ6_FUNC_LCD_R7>,
+                                                <STM32F429_PJ7_FUNC_LCD_G0>,
+                                                <STM32F429_PJ8_FUNC_LCD_G1>,
+                                                <STM32F429_PJ9_FUNC_LCD_G2>,
+                                                <STM32F429_PJ10_FUNC_LCD_G3>,
+                                                <STM32F429_PJ11_FUNC_LCD_G4>,
+                                                <STM32F429_PJ12_FUNC_LCD_B0>,
+                                                <STM32F429_PJ13_FUNC_LCD_B1>,
+                                                <STM32F429_PJ14_FUNC_LCD_B2>,
+                                                <STM32F429_PJ15_FUNC_LCD_B3>,
+                                                <STM32F429_PK0_FUNC_LCD_G5>,
+                                                <STM32F429_PK1_FUNC_LCD_G6>,
+                                                <STM32F429_PK2_FUNC_LCD_G7>,
+                                                <STM32F429_PK3_FUNC_LCD_B4>,
+                                                <STM32F429_PK4_FUNC_LCD_B5>,
+                                                <STM32F429_PK5_FUNC_LCD_B6>,
+                                                <STM32F429_PK6_FUNC_LCD_B7>,
+                                                <STM32F429_PK7_FUNC_LCD_DE>;
+                                       slew-rate = <2>;
+                               };
+                       };
+
+                       dcmi_pins: dcmi@0 {
+                               pins {
+                                       pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
+                                                <STM32F429_PB7_FUNC_DCMI_VSYNC>,
+                                                <STM32F429_PA6_FUNC_DCMI_PIXCLK>,
+                                                <STM32F429_PC6_FUNC_DCMI_D0>,
+                                                <STM32F429_PC7_FUNC_DCMI_D1>,
+                                                <STM32F429_PC8_FUNC_DCMI_D2>,
+                                                <STM32F429_PC9_FUNC_DCMI_D3>,
+                                                <STM32F429_PC11_FUNC_DCMI_D4>,
+                                                <STM32F429_PD3_FUNC_DCMI_D5>,
+                                                <STM32F429_PB8_FUNC_DCMI_D6>,
+                                                <STM32F429_PE6_FUNC_DCMI_D7>,
+                                                <STM32F429_PC10_FUNC_DCMI_D8>,
+                                                <STM32F429_PC12_FUNC_DCMI_D9>,
+                                                <STM32F429_PD6_FUNC_DCMI_D10>,
+                                                <STM32F429_PD2_FUNC_DCMI_D11>;
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <3>;
+                               };
+                       };
+               };
+       };
+};
index c66d617e4245b4c7b83f45e2266480c1ac64759d..5ceb2cf3777ff425a41a59da6dc90fe08adc257e 100644 (file)
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include "stm32f429-pinctrl.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {
diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..3e7a17d
--- /dev/null
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+       soc {
+               pinctrl: pin-controller {
+                       compatible = "st,stm32f429-pinctrl";
+
+                       gpioa: gpio@40020000 {
+                               gpio-ranges = <&pinctrl 0 0 16>;
+                       };
+
+                       gpiob: gpio@40020400 {
+                               gpio-ranges = <&pinctrl 0 16 16>;
+                       };
+
+                       gpioc: gpio@40020800 {
+                               gpio-ranges = <&pinctrl 0 32 16>;
+                       };
+
+                       gpiod: gpio@40020c00 {
+                               gpio-ranges = <&pinctrl 0 48 16>;
+                       };
+
+                       gpioe: gpio@40021000 {
+                               gpio-ranges = <&pinctrl 0 64 16>;
+                       };
+
+                       gpiof: gpio@40021400 {
+                               gpio-ranges = <&pinctrl 0 80 16>;
+                       };
+
+                       gpiog: gpio@40021800 {
+                               gpio-ranges = <&pinctrl 0 96 16>;
+                       };
+
+                       gpioh: gpio@40021c00 {
+                               gpio-ranges = <&pinctrl 0 112 16>;
+                       };
+
+                       gpioi: gpio@40022000 {
+                               gpio-ranges = <&pinctrl 0 128 16>;
+                       };
+
+                       gpioj: gpio@40022400 {
+                               gpio-ranges = <&pinctrl 0 144 16>;
+                       };
+
+                       gpiok: gpio@40022800 {
+                               gpio-ranges = <&pinctrl 0 160 8>;
+                       };
+               };
+       };
+};
index dd7e99b1f43bc78111f0de584849367a8f07cf8a..5b36eb114ddc953067904afbd08497b2286c3785 100644 (file)
@@ -47,7 +47,6 @@
 
 #include "skeleton.dtsi"
 #include "armv7-m.dtsi"
-#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
 #include <dt-bindings/clock/stm32fx-clock.h>
 #include <dt-bindings/mfd/stm32f4-rcc.h>
 
                        status = "disabled";
                };
 
-               pinctrl: pin-controller {
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       compatible = "st,stm32f429-pinctrl";
-                       ranges = <0 0x40020000 0x3000>;
-                       interrupt-parent = <&exti>;
-                       st,syscfg = <&syscfg 0x8>;
-                       pins-are-numbered;
-
-                       gpioa: gpio@40020000 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x0 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
-                               st,bank-name = "GPIOA";
-                       };
-
-                       gpiob: gpio@40020400 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x400 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
-                               st,bank-name = "GPIOB";
-                       };
-
-                       gpioc: gpio@40020800 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x800 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
-                               st,bank-name = "GPIOC";
-                       };
-
-                       gpiod: gpio@40020c00 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0xc00 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
-                               st,bank-name = "GPIOD";
-                       };
-
-                       gpioe: gpio@40021000 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x1000 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
-                               st,bank-name = "GPIOE";
-                       };
-
-                       gpiof: gpio@40021400 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x1400 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
-                               st,bank-name = "GPIOF";
-                       };
-
-                       gpiog: gpio@40021800 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x1800 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
-                               st,bank-name = "GPIOG";
-                       };
-
-                       gpioh: gpio@40021c00 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x1c00 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
-                               st,bank-name = "GPIOH";
-                       };
-
-                       gpioi: gpio@40022000 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x2000 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
-                               st,bank-name = "GPIOI";
-                       };
-
-                       gpioj: gpio@40022400 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x2400 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
-                               st,bank-name = "GPIOJ";
-                       };
-
-                       gpiok: gpio@40022800 {
-                               gpio-controller;
-                               #gpio-cells = <2>;
-                               interrupt-controller;
-                               #interrupt-cells = <2>;
-                               reg = <0x2800 0x400>;
-                               clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
-                               st,bank-name = "GPIOK";
-                       };
-
-                       usart1_pins_a: usart1@0 {
-                               pins1 {
-                                       pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
-                                       bias-disable;
-                                       drive-push-pull;
-                                       slew-rate = <0>;
-                               };
-                               pins2 {
-                                       pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
-                                       bias-disable;
-                               };
-                       };
-
-                       usart3_pins_a: usart3@0 {
-                               pins1 {
-                                       pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
-                                       bias-disable;
-                                       drive-push-pull;
-                                       slew-rate = <0>;
-                               };
-                               pins2 {
-                                       pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
-                                       bias-disable;
-                               };
-                       };
-
-                       usbotg_fs_pins_a: usbotg_fs@0 {
-                               pins {
-                                       pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
-                                                <STM32F429_PA11_FUNC_OTG_FS_DM>,
-                                                <STM32F429_PA12_FUNC_OTG_FS_DP>;
-                                       bias-disable;
-                                       drive-push-pull;
-                                       slew-rate = <2>;
-                               };
-                       };
-
-                       usbotg_fs_pins_b: usbotg_fs@1 {
-                               pins {
-                                       pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
-                                                <STM32F429_PB14_FUNC_OTG_HS_DM>,
-                                                <STM32F429_PB15_FUNC_OTG_HS_DP>;
-                                       bias-disable;
-                                       drive-push-pull;
-                                       slew-rate = <2>;
-                               };
-                       };
-
-                       usbotg_hs_pins_a: usbotg_hs@0 {
-                               pins {
-                                       pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
-                                                <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
-                                                <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
-                                                <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
-                                                <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
-                                                <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
-                                                <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
-                                                <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
-                                                <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
-                                                <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
-                                                <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
-                                                <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
-                                       bias-disable;
-                                       drive-push-pull;
-                                       slew-rate = <2>;
-                               };
-                       };
-
-                       ethernet_mii: mii@0 {
-                               pins {
-                                       pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
-                                                <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
-                                                <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
-                                                <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
-                                                <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
-                                                <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
-                                                <STM32F429_PA2_FUNC_ETH_MDIO>,
-                                                <STM32F429_PC1_FUNC_ETH_MDC>,
-                                                <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
-                                                <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
-                                                <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
-                                                <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
-                                                <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
-                                                <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
-                                       slew-rate = <2>;
-                               };
-                       };
-
-                       adc3_in8_pin: adc@200 {
-                               pins {
-                                       pinmux = <STM32F429_PF10_FUNC_ANALOG>;
-                               };
-                       };
-
-                       pwm1_pins: pwm@1 {
-                               pins {
-                                       pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
-                                                <STM32F429_PB13_FUNC_TIM1_CH1N>,
-                                                <STM32F429_PB12_FUNC_TIM1_BKIN>;
-                               };
-                       };
-
-                       pwm3_pins: pwm@3 {
-                               pins {
-                                       pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
-                                                <STM32F429_PB5_FUNC_TIM3_CH2>;
-                               };
-                       };
-
-                       i2c1_pins: i2c1@0 {
-                               pins {
-                                       pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
-                                                <STM32F429_PB6_FUNC_I2C1_SCL>;
-                                       bias-disable;
-                                       drive-open-drain;
-                                       slew-rate = <3>;
-                               };
-                       };
-
-                       ltdc_pins: ltdc@0 {
-                               pins {
-                                       pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
-                                                <STM32F429_PI13_FUNC_LCD_VSYNC>,
-                                                <STM32F429_PI14_FUNC_LCD_CLK>,
-                                                <STM32F429_PI15_FUNC_LCD_R0>,
-                                                <STM32F429_PJ0_FUNC_LCD_R1>,
-                                                <STM32F429_PJ1_FUNC_LCD_R2>,
-                                                <STM32F429_PJ2_FUNC_LCD_R3>,
-                                                <STM32F429_PJ3_FUNC_LCD_R4>,
-                                                <STM32F429_PJ4_FUNC_LCD_R5>,
-                                                <STM32F429_PJ5_FUNC_LCD_R6>,
-                                                <STM32F429_PJ6_FUNC_LCD_R7>,
-                                                <STM32F429_PJ7_FUNC_LCD_G0>,
-                                                <STM32F429_PJ8_FUNC_LCD_G1>,
-                                                <STM32F429_PJ9_FUNC_LCD_G2>,
-                                                <STM32F429_PJ10_FUNC_LCD_G3>,
-                                                <STM32F429_PJ11_FUNC_LCD_G4>,
-                                                <STM32F429_PJ12_FUNC_LCD_B0>,
-                                                <STM32F429_PJ13_FUNC_LCD_B1>,
-                                                <STM32F429_PJ14_FUNC_LCD_B2>,
-                                                <STM32F429_PJ15_FUNC_LCD_B3>,
-                                                <STM32F429_PK0_FUNC_LCD_G5>,
-                                                <STM32F429_PK1_FUNC_LCD_G6>,
-                                                <STM32F429_PK2_FUNC_LCD_G7>,
-                                                <STM32F429_PK3_FUNC_LCD_B4>,
-                                                <STM32F429_PK4_FUNC_LCD_B5>,
-                                                <STM32F429_PK5_FUNC_LCD_B6>,
-                                                <STM32F429_PK6_FUNC_LCD_B7>,
-                                                <STM32F429_PK7_FUNC_LCD_DE>;
-                                       slew-rate = <2>;
-                               };
-                       };
-
-                       dcmi_pins: dcmi@0 {
-                               pins {
-                                       pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
-                                                <STM32F429_PB7_FUNC_DCMI_VSYNC>,
-                                                <STM32F429_PA6_FUNC_DCMI_PIXCLK>,
-                                                <STM32F429_PC6_FUNC_DCMI_D0>,
-                                                <STM32F429_PC7_FUNC_DCMI_D1>,
-                                                <STM32F429_PC8_FUNC_DCMI_D2>,
-                                                <STM32F429_PC9_FUNC_DCMI_D3>,
-                                                <STM32F429_PC11_FUNC_DCMI_D4>,
-                                                <STM32F429_PD3_FUNC_DCMI_D5>,
-                                                <STM32F429_PB8_FUNC_DCMI_D6>,
-                                                <STM32F429_PE6_FUNC_DCMI_D7>,
-                                                <STM32F429_PC10_FUNC_DCMI_D8>,
-                                                <STM32F429_PC12_FUNC_DCMI_D9>,
-                                                <STM32F429_PD6_FUNC_DCMI_D10>,
-                                                <STM32F429_PD2_FUNC_DCMI_D11>;
-                                       bias-disable;
-                                       drive-push-pull;
-                                       slew-rate = <3>;
-                               };
-                       };
-               };
-
                crc: crc@40023000 {
                        compatible = "st,stm32f4-crc";
                        reg = <0x40023000 0x400>;
index 6ae1f037f3f0e5065eb80a6159a8bfb1d5eb3ba1..c18acbe4cf4e2448b085331fca86a72710eeb613 100644 (file)
@@ -47,6 +47,7 @@
 
 /dts-v1/;
 #include "stm32f429.dtsi"
+#include "stm32f469-pinctrl.dtsi"
 
 / {
        model = "STMicroelectronics STM32F469i-DISCO board";
diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi
new file mode 100644 (file)
index 0000000..fff5426
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+       soc {
+               pinctrl: pin-controller {
+                       compatible = "st,stm32f469-pinctrl";
+
+                       gpioa: gpio@40020000 {
+                               gpio-ranges = <&pinctrl 0 0 16>;
+                       };
+
+                       gpiob: gpio@40020400 {
+                               gpio-ranges = <&pinctrl 0 16 16>;
+                       };
+
+                       gpioc: gpio@40020800 {
+                               gpio-ranges = <&pinctrl 0 32 16>;
+                       };
+
+                       gpiod: gpio@40020c00 {
+                               gpio-ranges = <&pinctrl 0 48 16>;
+                       };
+
+                       gpioe: gpio@40021000 {
+                               gpio-ranges = <&pinctrl 0 64 16>;
+                       };
+
+                       gpiof: gpio@40021400 {
+                               gpio-ranges = <&pinctrl 0 80 16>;
+                       };
+
+                       gpiog: gpio@40021800 {
+                               gpio-ranges = <&pinctrl 0 96 16>;
+                       };
+
+                       gpioh: gpio@40021c00 {
+                               gpio-ranges = <&pinctrl 0 112 16>;
+                       };
+
+                       gpioi: gpio@40022000 {
+                               gpio-ranges = <&pinctrl 0 128 16>;
+                       };
+
+                       gpioj: gpio@40022400 {
+                               gpio-ranges = <&pinctrl 0 144 6>,
+                                             <&pinctrl 12 156 4>;
+                       };
+
+                       gpiok: gpio@40022800 {
+                               gpio-ranges = <&pinctrl 3 163 5>;
+                       };
+               };
+       };
+};
index d2d75fa664a64338bc6bf0af3c3c65e3de0926f4..2a63fa10c813042bf2b98261964c7b6cd9f03790 100644 (file)
@@ -32,6 +32,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
+CONFIG_PATA_FTIDE010=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
@@ -55,8 +56,8 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_GEMINI=y
 CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
 # CONFIG_DNOTIFY is not set
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
index 64e3a2a8cedec353203694d6f9f74b4fa09f962f..d5e1370ec303d5440c4572262f6918d4a047a170 100644 (file)
@@ -471,7 +471,7 @@ CONFIG_LCD_PLATFORM=m
 CONFIG_LCD_TOSA=m
 CONFIG_BACKLIGHT_PWM=m
 CONFIG_BACKLIGHT_TOSA=m
-CONFIG_FRAMEBUFFER_CONSOLE=m
+CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_LOGO=y
 CONFIG_SOUND=m
index 44d4fa57ba0a346cde5f53d099a3be61b42d841a..070e5074f1ee5b118ed35612c9cd09d65f611255 100644 (file)
@@ -113,7 +113,7 @@ CONFIG_FB_PXA_PARAMETERS=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_PWM=m
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=m
+CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_SOUND=m
 CONFIG_SND=m
index 8d4c0c926c344d9f654a87d179488eb5bfff7096..09e7050d56532dabd512cc99e1038a6dae525d69 100644 (file)
@@ -112,7 +112,7 @@ CONFIG_FB_PXA=m
 CONFIG_FB_PXA_PARAMETERS=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=m
+CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_SOUND=m
 CONFIG_SND=m
index 5036f996e694a533d66f82743b901385ae048007..849014c01cf4d62a465ec6e54b829d4ff45f05a6 100644 (file)
@@ -533,8 +533,8 @@ static void __init at91_pm_backup_init(void)
        }
 
        pm_bu->suspended = 0;
-       pm_bu->canary = virt_to_phys(&canary);
-       pm_bu->resume = virt_to_phys(cpu_resume);
+       pm_bu->canary = __pa_symbol(&canary);
+       pm_bu->resume = __pa_symbol(cpu_resume);
 
        return;
 
index 5b614388d72f4b7ca8be1c851f1369f719ce2c29..6d28aa20a7d32c4142dba9a52cbaa06fc6c387f1 100644 (file)
@@ -58,10 +58,10 @@ void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
        struct platform_device *pdev;
        int res;
 
-       if (omap_hsmmc_done != 1)
+       if (omap_hsmmc_done)
                return;
 
-       omap_hsmmc_done++;
+       omap_hsmmc_done = 1;
 
        for (; c->mmc; c++) {
                pdev = c->pdev;
index f040244c57e73f381c0004e730ff1664f9300e00..2f4f7002f38d0138e9d8cb9cb2d3cb9d97237675 100644 (file)
@@ -839,6 +839,7 @@ static struct omap_hwmod dra7xx_gpio1_hwmod = {
        .name           = "gpio1",
        .class          = &dra7xx_gpio_hwmod_class,
        .clkdm_name     = "wkupaon_clkdm",
+       .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
        .main_clk       = "wkupaon_iclk_mux",
        .prcm = {
                .omap4 = {
index c89010e564888ee76f0f2764a10592fb59ab7672..4157987f4a3d2515053c1b5a49031c32f7f3b652 100644 (file)
 &sd_emmc_a {
        status = "okay";
        pinctrl-0 = <&sdio_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
        #address-cells = <1>;
        #size-cells = <0>;
 
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index 9697a7a794644bdfd5e7dbedfa6f71dcd8451e24..4b17a76959b2f6bff6275013d95b74c091032c51 100644 (file)
 
                states = <3300000 0>,
                         <1800000 1>;
+
+               regulator-settling-time-up-us = <100>;
+               regulator-settling-time-down-us = <5000>;
        };
 
        wifi_32k: wifi-32k {
 &sd_emmc_a {
        status = "okay";
        pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
        #address-cells = <1>;
        #size-cells = <0>;
 
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
-       max-frequency = <100000000>;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       max-frequency = <200000000>;
        disable-wp;
 
        cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
 &sd_emmc_c {
        status = "disabled";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        max-frequency = <200000000>;
        non-removable;
        disable-wp;
index 9c59c3c6d1b6a5d2e3d8cd9d234caef971b352c3..38dfdde5c1473c71f5eb04ed779d1537d386fe31 100644 (file)
@@ -51,7 +51,7 @@
 / {
        compatible = "nexbox,a95x", "amlogic,meson-gxbb";
        model = "NEXBOX A95X";
-       
+
        aliases {
                serial0 = &uart_AO;
        };
 &sd_emmc_a {
        status = "okay";
        pinctrl-0 = <&sdio_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
        #address-cells = <1>;
        #size-cells = <0>;
 
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index d147c853ab054d86affa734311ae2c9df713ea58..1ffa1c238a725348cdcc10be5afe35be7dac1d60 100644 (file)
@@ -50,7 +50,7 @@
 / {
        compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
        model = "Hardkernel ODROID-C2";
-       
+
        aliases {
                serial0 = &uart_AO;
        };
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        max-frequency = <200000000>;
        non-removable;
        disable-wp;
index 81ffc689a5bf42532f25706545b1f84cb5dcdbac..23c08c3afd0ab499255ff4502bc9a472aa9d4548 100644 (file)
 &sd_emmc_a {
        status = "okay";
        pinctrl-0 = <&sdio_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
        #address-cells = <1>;
        #size-cells = <0>;
 
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
        max-frequency = <100000000>;
        disable-wp;
 
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index 346753fb632431f1c2e2af4d9c72b740a3f8c3b8..f2bc6dea1fc62235987f28d6ff1871913ee5753d 100644 (file)
 &sd_emmc_a {
        status = "okay";
        pinctrl-0 = <&sdio_pins &sdio_irq_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
        #address-cells = <1>;
        #size-cells = <0>;
 
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index 52f1687e7a099af5789ed97e3597b727a8ee4d82..af834cdbba791ab4432065eea6b855396e1937f9 100644 (file)
                        };
                };
 
+               emmc_clk_gate_pins: emmc_clk_gate {
+                       mux {
+                               groups = "BOOT_8";
+                               function = "gpio_periphs";
+                       };
+                       cfg-pull-down {
+                               pins = "BOOT_8";
+                               bias-pull-down;
+                       };
+               };
+
                nor_pins: nor {
                        mux {
                                groups = "nor_d",
                        };
                };
 
+               sdcard_clk_gate_pins: sdcard_clk_gate {
+                       mux {
+                               groups = "CARD_2";
+                               function = "gpio_periphs";
+                       };
+                       cfg-pull-down {
+                               pins = "CARD_2";
+                               bias-pull-down;
+                       };
+               };
+
                sdio_pins: sdio {
                        mux {
                                groups = "sdio_d0",
                        };
                };
 
+               sdio_clk_gate_pins: sdio_clk_gate {
+                       mux {
+                               groups = "GPIOX_4";
+                               function = "gpio_periphs";
+                       };
+                       cfg-pull-down {
+                               pins = "GPIOX_4";
+                               bias-pull-down;
+                       };
+               };
+
                sdio_irq_pins: sdio_irq {
                        mux {
                                groups = "sdio_irq";
 
 &sd_emmc_a {
        clocks = <&clkc CLKID_SD_EMMC_A>,
-                <&xtal>,
+                <&clkc CLKID_SD_EMMC_A_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_b {
        clocks = <&clkc CLKID_SD_EMMC_B>,
-                <&xtal>,
+                <&clkc CLKID_SD_EMMC_B_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_c {
        clocks = <&clkc CLKID_SD_EMMC_C>,
-                <&xtal>,
+                <&clkc CLKID_SD_EMMC_C_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
index 2a5804ce7f4bd6bbfe1285f3cc40786778576a09..977b4240f3c1b0de15e0b32c70aafce1123acd01 100644 (file)
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <100000000>;
        non-removable;
index 69ca14ac10fa097633562cb96db4f088e543ebd9..64c54c92e214d686154de4b237f71a5212c5eb20 100644 (file)
@@ -91,6 +91,9 @@
 
                states = <3300000 0>,
                         <1800000 1>;
+
+               regulator-settling-time-up-us = <200>;
+               regulator-settling-time-down-us = <50000>;
        };
 
        vddio_boot: regulator-vddio_boot {
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
        max-frequency = <100000000>;
        disable-wp;
 
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
        cap-mmc-highspeed;
+       mmc-ddr-3_3v;
        max-frequency = <50000000>;
        non-removable;
        disable-wp;
index 4c2ac7650fcd3317a673efdd7308891a154272d8..1b8f32867aa10ab9ae75e90c995cdf16a088632e 100644 (file)
 &sd_emmc_a {
        status = "okay";
        pinctrl-0 = <&sdio_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
        #address-cells = <1>;
        #size-cells = <0>;
 
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index f3eea8e89d12b7a4479851a8d1e0482374235568..129af9068814d3b0f8e33090adbcda435ea3e202 100644 (file)
@@ -95,7 +95,8 @@
 &sd_emmc_a {
        status = "okay";
        pinctrl-0 = <&sdio_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdio_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
        #address-cells = <1>;
        #size-cells = <0>;
 
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index d6876e64979e7a5c5d539dc3eba7006fe4d79315..d8dd3298b15cfe5a37d653b8c6d5d39f5ca8c008 100644 (file)
                        };
                };
 
+               emmc_clk_gate_pins: emmc_clk_gate {
+                       mux {
+                               groups = "BOOT_8";
+                               function = "gpio_periphs";
+                       };
+                       cfg-pull-down {
+                               pins = "BOOT_8";
+                               bias-pull-down;
+                       };
+               };
+
                nor_pins: nor {
                        mux {
                                groups = "nor_d",
                        };
                };
 
+               sdcard_clk_gate_pins: sdcard_clk_gate {
+                       mux {
+                               groups = "CARD_2";
+                               function = "gpio_periphs";
+                       };
+                       cfg-pull-down {
+                               pins = "CARD_2";
+                               bias-pull-down;
+                       };
+               };
+
                sdio_pins: sdio {
                        mux {
                                groups = "sdio_d0",
                        };
                };
 
+               sdio_clk_gate_pins: sdio_clk_gate {
+                       mux {
+                               groups = "GPIOX_4";
+                               function = "gpio_periphs";
+                       };
+                       cfg-pull-down {
+                               pins = "GPIOX_4";
+                               bias-pull-down;
+                       };
+               };
+
                sdio_irq_pins: sdio_irq {
                        mux {
                                groups = "sdio_irq";
 
 &sd_emmc_a {
        clocks = <&clkc CLKID_SD_EMMC_A>,
-                <&xtal>,
+                <&clkc CLKID_SD_EMMC_A_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_b {
        clocks = <&clkc CLKID_SD_EMMC_B>,
-                <&xtal>,
+                <&clkc CLKID_SD_EMMC_B_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
 
 &sd_emmc_c {
        clocks = <&clkc CLKID_SD_EMMC_C>,
-                <&xtal>,
+                <&clkc CLKID_SD_EMMC_C_CLK0>,
                 <&clkc CLKID_FCLK_DIV2>;
        clock-names = "core", "clkin0", "clkin1";
 };
index 9b10c5f4f8c0311af38380f7d5c4c2a0e709e747..22c697732f668c5fadb5c445a849a80e57956fe0 100644 (file)
 &sd_emmc_b {
        status = "okay";
        pinctrl-0 = <&sdcard_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&sdcard_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <4>;
        cap-sd-highspeed;
 &sd_emmc_c {
        status = "okay";
        pinctrl-0 = <&emmc_pins>;
-       pinctrl-names = "default";
+       pinctrl-1 = <&emmc_clk_gate_pins>;
+       pinctrl-names = "default", "clk-gate";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index 08f1dd69b6792e3ceb54bd1e56697ce14f35df12..470f72bb863c5ff8850508cefd828b1c2e4f5f24 100644 (file)
        pinctrl-names = "default";
 
        bus-width = <8>;
-       cap-sd-highspeed;
        cap-mmc-highspeed;
        max-frequency = <200000000>;
        non-removable;
index 4d360713ed12459199ca726f34c32266739865dc..30d48ecf46e087b24063c0ac546d45ae9afb0d88 100644 (file)
 
                        ap_syscon: system-controller@6f4000 {
                                compatible = "syscon", "simple-mfd";
-                               reg = <0x6f4000 0x1000>;
+                               reg = <0x6f4000 0x2000>;
 
                                ap_clk: clock {
                                        compatible = "marvell,ap806-clock";
                                        compatible = "marvell,ap806-pinctrl";
                                };
 
-                               ap_gpio: gpio {
+                               ap_gpio: gpio@1040 {
                                        compatible = "marvell,armada-8k-gpio";
                                        offset = <0x1040>;
                                        ngpios = <20>;
index e0518b4bc6c2a018963787d0096077ab540b78e8..19fbaa5e7bdd573e6ba6959be9c72ccbb0a388a6 100644 (file)
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKL>;
-                       operating-points-v2 = <&cluster0_opp>;
+
                        #cooling-cells = <2>; /* min followed by max */
                };
 
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKL>;
-                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu_l2: cpu@2 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKL>;
-                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu_l3: cpu@3 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKL>;
-                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu_b0: cpu@100 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKB>;
-                       operating-points-v2 = <&cluster1_opp>;
+
                        #cooling-cells = <2>; /* min followed by max */
                };
 
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKB>;
-                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu_b2: cpu@102 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKB>;
-                       operating-points-v2 = <&cluster1_opp>;
                };
 
                cpu_b3: cpu@103 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
-                       clocks = <&cru ARMCLKB>;
-                       operating-points-v2 = <&cluster1_opp>;
-               };
-       };
-
-       cluster0_opp: opp-table0 {
-               compatible = "operating-points-v2";
-               opp-shared;
-
-               opp00 {
-                       opp-hz = /bits/ 64 <312000000>;
-                       opp-microvolt = <950000>;
-                       clock-latency-ns = <40000>;
-               };
-               opp01 {
-                       opp-hz = /bits/ 64 <408000000>;
-                       opp-microvolt = <950000>;
-               };
-               opp02 {
-                       opp-hz = /bits/ 64 <600000000>;
-                       opp-microvolt = <950000>;
-               };
-               opp03 {
-                       opp-hz = /bits/ 64 <816000000>;
-                       opp-microvolt = <1025000>;
-               };
-               opp04 {
-                       opp-hz = /bits/ 64 <1008000000>;
-                       opp-microvolt = <1125000>;
-               };
-       };
-
-       cluster1_opp: opp-table1 {
-               compatible = "operating-points-v2";
-               opp-shared;
-
-               opp00 {
-                       opp-hz = /bits/ 64 <312000000>;
-                       opp-microvolt = <950000>;
-                       clock-latency-ns = <40000>;
-               };
-               opp01 {
-                       opp-hz = /bits/ 64 <408000000>;
-                       opp-microvolt = <950000>;
-               };
-               opp02 {
-                       opp-hz = /bits/ 64 <600000000>;
-                       opp-microvolt = <950000>;
-               };
-               opp03 {
-                       opp-hz = /bits/ 64 <816000000>;
-                       opp-microvolt = <975000>;
-               };
-               opp04 {
-                       opp-hz = /bits/ 64 <1008000000>;
-                       opp-microvolt = <1050000>;
                };
        };
 
index d79e9b3265b98cbe0955c8139950627d2af09492..ab7629c5b856d7a6ed2ac8e95600262e098a01d6 100644 (file)
                compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
                reg = <0x0 0xff960000 0x0 0x8000>;
                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
-               clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
-                        <&cru SCLK_DPHY_TX0_CFG>;
-               clock-names = "ref", "pclk", "phy_cfg";
+               clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
+                        <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
+               clock-names = "ref", "pclk", "phy_cfg", "grf";
                power-domains = <&power RK3399_PD_VIO>;
                rockchip,grf = <&grf>;
                status = "disabled";
index 3585a5e2615105162f82510f64917b094974a2a4..f7c4d2146aed09b715a59506f7e01ab0d167f3de 100644 (file)
 #define KERNEL_END        _end
 
 /*
- * The size of the KASAN shadow region. This should be 1/8th of the
- * size of the entire kernel virtual address space.
+ * KASAN requires 1/8th of the kernel virtual address space for the shadow
+ * region. KASAN can bloat the stack significantly, so double the (minimum)
+ * stack size when KASAN is in use.
  */
 #ifdef CONFIG_KASAN
 #define KASAN_SHADOW_SIZE      (UL(1) << (VA_BITS - 3))
+#define KASAN_THREAD_SHIFT     1
 #else
 #define KASAN_SHADOW_SIZE      (0)
+#define KASAN_THREAD_SHIFT     0
 #endif
 
-#define MIN_THREAD_SHIFT       14
+#define MIN_THREAD_SHIFT       (14 + KASAN_THREAD_SHIFT)
 
 /*
  * VMAP'd stacks are allocated at page granularity, so we must ensure that such
index f0e6d717885b1fcf3b22f64c10c38f19c25f809d..d06fbe4cd38d7423c900aff64b0e728f995478d3 100644 (file)
@@ -649,4 +649,4 @@ static int __init armv8_deprecated_init(void)
        return 0;
 }
 
-late_initcall(armv8_deprecated_init);
+core_initcall(armv8_deprecated_init);
index cd52d365d1f01aefae2f63e6a0207e65e0fdcb57..21e2c95d24e72a8e339406af601f02690675d3d8 100644 (file)
@@ -1307,4 +1307,4 @@ static int __init enable_mrs_emulation(void)
        return 0;
 }
 
-late_initcall(enable_mrs_emulation);
+core_initcall(enable_mrs_emulation);
index f444f374bd7b3ccea1b097cc13d9229db5c8f2c3..5d547deb6996c0091c64f14de18b5b8a75c88ae4 100644 (file)
@@ -444,4 +444,4 @@ static int __init fpsimd_init(void)
 
        return 0;
 }
-late_initcall(fpsimd_init);
+core_initcall(fpsimd_init);
index 2069e9bc0fca674ba1d6fe769be05e6f731ef93d..b64958b23a7fa193c23dd1a9039f69f4e9f0b863 100644 (file)
@@ -97,7 +97,7 @@ static void data_abort_decode(unsigned int esr)
                         (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
                         (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
        } else {
-               pr_alert("  ISV = 0, ISS = 0x%08lu\n", esr & ESR_ELx_ISS_MASK);
+               pr_alert("  ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
        }
 
        pr_alert("  CM = %lu, WnR = %lu\n",
index 87cde1e4b38ca026483729dec6ea61ad5c242a97..0777f3a8a1f37d6f93d707a3333be23c486492e2 100644 (file)
@@ -194,6 +194,10 @@ config TIMER_DIVIDE
        int "Timer divider (integer)"
        default "128"
 
+config CPU_BIG_ENDIAN
+        bool "Generate big endian code"
+       default n
+
 config CPU_LITTLE_ENDIAN
         bool "Generate little endian code"
        default n
index 647dd94a0c399f13f8311e751d273b033908328e..72b96f282689aec63378d85cc50b079ddff2b799 100644 (file)
@@ -114,6 +114,15 @@ static void set_eit_vector_entries(void)
        _flush_cache_copyback_all();
 }
 
+void abort(void)
+{
+       BUG();
+
+       /* if that doesn't kill us, halt */
+       panic("Oops failed to kill thread");
+}
+EXPORT_SYMBOL(abort);
+
 void __init trap_init(void)
 {
        set_eit_vector_entries();
index a45a67d526f8ca8001fd1d06625b3b233d5a3835..30f92391a93ef6d5a90970b81921a2133d5e2eb0 100644 (file)
@@ -146,7 +146,7 @@ void machine_power_off(void)
 
        /* prevent soft lockup/stalled CPU messages for endless loop. */
        rcu_sysrq_start();
-       lockup_detector_suspend();
+       lockup_detector_soft_poweroff();
        for (;;);
 }
 
index 1df770e8cbe03194f31576cff264fdedbb1aa517..7275fed271afa601711b2f43b0da2c2377c68eff 100644 (file)
@@ -102,10 +102,10 @@ static void cpufeatures_flush_tlb(void)
        case PVR_POWER8:
        case PVR_POWER8E:
        case PVR_POWER8NVL:
-               __flush_tlb_power8(POWER8_TLB_SETS);
+               __flush_tlb_power8(TLB_INVAL_SCOPE_GLOBAL);
                break;
        case PVR_POWER9:
-               __flush_tlb_power9(POWER9_TLB_SETS_HASH);
+               __flush_tlb_power9(TLB_INVAL_SCOPE_GLOBAL);
                break;
        default:
                pr_err("unknown CPU version for boot TLB flush\n");
index b76ca198e09c186e2d90e9b3eb83c7765c6c1cdf..72f153c6f3facea2bda06b64e90b24a6fed253d5 100644 (file)
@@ -624,5 +624,18 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs)
 
 long __machine_check_early_realmode_p9(struct pt_regs *regs)
 {
+       /*
+        * On POWER9 DD2.1 and below, it's possible to get a machine check
+        * caused by a paste instruction where only DSISR bit 25 is set. This
+        * will result in the MCE handler seeing an unknown event and the kernel
+        * crashing. An MCE that occurs like this is spurious, so we don't need
+        * to do anything in terms of servicing it. If there is something that
+        * needs to be serviced, the CPU will raise the MCE again with the
+        * correct DSISR so that it can be serviced properly. So detect this
+        * case and mark it as handled.
+        */
+       if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
+               return 1;
+
        return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);
 }
index 0ac741fae90ea5c1cffc227323fe40cbb5319188..2e3bc16d02b289b5d03906010518bc7005233452 100644 (file)
@@ -904,9 +904,6 @@ void __init setup_arch(char **cmdline_p)
 #endif
 #endif
 
-#ifdef CONFIG_PPC_64K_PAGES
-       init_mm.context.pte_frag = NULL;
-#endif
 #ifdef CONFIG_SPAPR_TCE_IOMMU
        mm_iommu_init(&init_mm);
 #endif
index 2f6eadd9408d9490b171ca20f937c1af79096acd..c702a898145250aa4e4da3a88bd32a960ad4fb78 100644 (file)
@@ -310,9 +310,6 @@ static int start_wd_on_cpu(unsigned int cpu)
        if (!(watchdog_enabled & NMI_WATCHDOG_ENABLED))
                return 0;
 
-       if (watchdog_suspended)
-               return 0;
-
        if (!cpumask_test_cpu(cpu, &watchdog_cpumask))
                return 0;
 
@@ -358,36 +355,39 @@ static void watchdog_calc_timeouts(void)
        wd_timer_period_ms = watchdog_thresh * 1000 * 2 / 5;
 }
 
-void watchdog_nmi_reconfigure(void)
+void watchdog_nmi_stop(void)
 {
        int cpu;
 
-       watchdog_calc_timeouts();
-
        for_each_cpu(cpu, &wd_cpus_enabled)
                stop_wd_on_cpu(cpu);
+}
 
+void watchdog_nmi_start(void)
+{
+       int cpu;
+
+       watchdog_calc_timeouts();
        for_each_cpu_and(cpu, cpu_online_mask, &watchdog_cpumask)
                start_wd_on_cpu(cpu);
 }
 
 /*
- * This runs after lockup_detector_init() which sets up watchdog_cpumask.
+ * Invoked from core watchdog init.
  */
-static int __init powerpc_watchdog_init(void)
+int __init watchdog_nmi_probe(void)
 {
        int err;
 
-       watchdog_calc_timeouts();
-
-       err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/watchdog:online",
-                               start_wd_on_cpu, stop_wd_on_cpu);
-       if (err < 0)
+       err = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
+                                       "powerpc/watchdog:online",
+                                       start_wd_on_cpu, stop_wd_on_cpu);
+       if (err < 0) {
                pr_warn("Watchdog could not be initialized");
-
+               return err;
+       }
        return 0;
 }
-arch_initcall(powerpc_watchdog_init);
 
 static void handle_backtrace_ipi(struct pt_regs *regs)
 {
index 13304622ab1c78682fa18f06120f5eb0970f57fb..bf457843e03217b9aa02815d7791f0fce72aea2b 100644 (file)
@@ -622,7 +622,7 @@ int kvmppc_xive_get_xive(struct kvm *kvm, u32 irq, u32 *server,
                return -EINVAL;
        state = &sb->irq_state[idx];
        arch_spin_lock(&sb->lock);
-       *server = state->guest_server;
+       *server = state->act_server;
        *priority = state->guest_priority;
        arch_spin_unlock(&sb->lock);
 
@@ -1331,7 +1331,7 @@ static int xive_get_source(struct kvmppc_xive *xive, long irq, u64 addr)
        xive->saved_src_count++;
 
        /* Convert saved state into something compatible with xics */
-       val = state->guest_server;
+       val = state->act_server;
        prio = state->saved_scan_prio;
 
        if (prio == MASKED) {
@@ -1507,7 +1507,6 @@ static int xive_set_source(struct kvmppc_xive *xive, long irq, u64 addr)
        /* First convert prio and mark interrupt as untargetted */
        act_prio = xive_prio_from_guest(guest_prio);
        state->act_priority = MASKED;
-       state->guest_server = server;
 
        /*
         * We need to drop the lock due to the mutex below. Hopefully
index 5938f7644dc17587dc811132459cf8b71425856a..6ba63f8e8a614ed4aad2a5890236834f3e08c0a7 100644 (file)
@@ -35,7 +35,6 @@ struct kvmppc_xive_irq_state {
        struct xive_irq_data *pt_data;  /* XIVE Pass-through associated data */
 
        /* Targetting as set by guest */
-       u32 guest_server;               /* Current guest selected target */
        u8 guest_priority;              /* Guest set priority */
        u8 saved_priority;              /* Saved priority when masking */
 
index 65eda1997c3f8750c899294bc1d9bb15215d9426..f6c7f54c05157e226c5426798b6fa0f379f8becb 100644 (file)
@@ -361,9 +361,9 @@ static int change_page_attr(struct page *page, int numpages, pgprot_t prot)
                        break;
        }
        wmb();
+       local_irq_restore(flags);
        flush_tlb_kernel_range((unsigned long)page_address(start),
                               (unsigned long)page_address(page));
-       local_irq_restore(flags);
        return err;
 }
 
index 897aa1400eb833e944fabbc65840904006267a1f..bbb73aa0eb8f041630110c795828215471cc5f2d 100644 (file)
@@ -272,7 +272,15 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
 static unsigned long pnv_memory_block_size(void)
 {
-       return 256UL * 1024 * 1024;
+       /*
+        * We map the kernel linear region with 1GB large pages on radix. For
+        * memory hot unplug to work our memory block size must be at least
+        * this size.
+        */
+       if (radix_enabled())
+               return 1UL * 1024 * 1024 * 1024;
+       else
+               return 256UL * 1024 * 1024;
 }
 #endif
 
index 9234be1e66f556b129148efec300c1f5a4f24239..5011ffea4e4b3a8d3c69160bb1bb896cdeb8cb1f 100644 (file)
@@ -71,6 +71,8 @@
 #define RIWAR_WRTYP_ALLOC      0x00006000
 #define RIWAR_SIZE_MASK                0x0000003F
 
+static DEFINE_SPINLOCK(fsl_rio_config_lock);
+
 #define __fsl_read_rio_config(x, addr, err, op)                \
        __asm__ __volatile__(                           \
                "1:     "op" %1,0(%2)\n"                \
@@ -184,6 +186,7 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
                        u8 hopcount, u32 offset, int len, u32 *val)
 {
        struct rio_priv *priv = mport->priv;
+       unsigned long flags;
        u8 *data;
        u32 rval, err = 0;
 
@@ -197,6 +200,8 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
        if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
                return -EINVAL;
 
+       spin_lock_irqsave(&fsl_rio_config_lock, flags);
+
        out_be32(&priv->maint_atmu_regs->rowtar,
                 (destid << 22) | (hopcount << 12) | (offset >> 12));
        out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
@@ -213,6 +218,7 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
                __fsl_read_rio_config(rval, data, err, "lwz");
                break;
        default:
+               spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
                return -EINVAL;
        }
 
@@ -221,6 +227,7 @@ fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
                         err, destid, hopcount, offset);
        }
 
+       spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
        *val = rval;
 
        return err;
@@ -244,7 +251,10 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
                        u8 hopcount, u32 offset, int len, u32 val)
 {
        struct rio_priv *priv = mport->priv;
+       unsigned long flags;
        u8 *data;
+       int ret = 0;
+
        pr_debug
                ("fsl_rio_config_write:"
                " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
@@ -255,6 +265,8 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
        if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
                return -EINVAL;
 
+       spin_lock_irqsave(&fsl_rio_config_lock, flags);
+
        out_be32(&priv->maint_atmu_regs->rowtar,
                 (destid << 22) | (hopcount << 12) | (offset >> 12));
        out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
@@ -271,10 +283,11 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
                out_be32((u32 *) data, val);
                break;
        default:
-               return -EINVAL;
+               ret = -EINVAL;
        }
+       spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
 
-       return 0;
+       return ret;
 }
 
 static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
index ab7a74c75be8f6a8da71c77ad027cf16bb5eac3b..88b35a3dcdc599b01c37da944ba3f8481215d6cc 100644 (file)
 
 #define DOORBELL_MESSAGE_SIZE  0x08
 
+static DEFINE_SPINLOCK(fsl_rio_doorbell_lock);
+
 struct rio_msg_regs {
        u32 omr;
        u32 osr;
@@ -626,9 +628,13 @@ err_out:
 int fsl_rio_doorbell_send(struct rio_mport *mport,
                                int index, u16 destid, u16 data)
 {
+       unsigned long flags;
+
        pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
                 index, destid, data);
 
+       spin_lock_irqsave(&fsl_rio_doorbell_lock, flags);
+
        /* In the serial version silicons, such as MPC8548, MPC8641,
         * below operations is must be.
         */
@@ -638,6 +644,8 @@ int fsl_rio_doorbell_send(struct rio_mport *mport,
        out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data);
        out_be32(&dbell->dbell_regs->odmr, 0x00000001);
 
+       spin_unlock_irqrestore(&fsl_rio_doorbell_lock, flags);
+
        return 0;
 }
 
index f387318678b97abdfa8e57fe46eade5a707e566d..a3b8d7d1316eb1863f19ffa19ff34f0c761ada33 100644 (file)
@@ -1402,6 +1402,14 @@ void xive_teardown_cpu(void)
 
        if (xive_ops->teardown_cpu)
                xive_ops->teardown_cpu(cpu, xc);
+
+#ifdef CONFIG_SMP
+       /* Get rid of IPI */
+       xive_cleanup_cpu_ipi(cpu, xc);
+#endif
+
+       /* Disable and free the queues */
+       xive_cleanup_cpu_queues(cpu, xc);
 }
 
 void xive_kexec_teardown_cpu(int secondary)
index f24a70bc6855d54cf86a50d17fefebc9777e2ed0..d9c4c93660491849029044d37ab8e60160b0d7de 100644 (file)
@@ -431,7 +431,11 @@ static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 
 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 {
+       if (!xc->hw_ipi)
+               return;
+
        xive_irq_bitmap_free(xc->hw_ipi);
+       xc->hw_ipi = 0;
 }
 #endif /* CONFIG_SMP */
 
index 4d1ef6d74bd6050cb34d0f2fdd91d114fb0baa96..2ae0e938b657a109963dc2059b401f02a673d4fc 100644 (file)
@@ -43,9 +43,7 @@ enum {
        GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
        GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
 
-       /* Port H */
-       GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
-       GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
+       /* Port H - Port H does not have a Data Register */
 
        /* Port I - not on device */
 
index 2a0ca8780f0d8c343fb87e434cf6acec73acaddb..13c495a9fc0007b414bb8f8e36c0e9618e356c3e 100644 (file)
@@ -45,9 +45,7 @@ enum {
        GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
        GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
 
-       /* Port H */
-       GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
-       GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
+       /* Port H - Port H does not have a Data Register */
 
        /* Port I - not on device */
 
index 3bb74e534d0f8ca44208827d762e9dec03b2525a..78961ab78a5a9c83320706171123e59115d00ba5 100644 (file)
@@ -67,7 +67,7 @@ enum {
        GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
 
        /* PTQ */
-       GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
+       GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
        GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
 
        /* PTR */
index 5340f3bc1863c3890dde9a8286e05d111a8393ed..b40fb541e72a78ae18002aa79702fa2e72e298b7 100644 (file)
@@ -40,7 +40,7 @@ enum {
 
        /* PTJ */
        GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3,
-       GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, GPIO_PTJ7_RESV,
+       GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6,
 
        /* PTK */
        GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3,
@@ -48,7 +48,7 @@ enum {
 
        /* PTL */
        GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3,
-       GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, GPIO_PTL7_RESV,
+       GPIO_PTL4, GPIO_PTL5, GPIO_PTL6,
 
        /* PTM */
        GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3,
@@ -56,7 +56,7 @@ enum {
 
        /* PTN */
        GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3,
-       GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, GPIO_PTN7_RESV,
+       GPIO_PTN4, GPIO_PTN5, GPIO_PTN6,
 
        /* PTO */
        GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3,
@@ -68,7 +68,7 @@ enum {
 
        /* PTQ */
        GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3,
-       GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, GPIO_PTQ7_RESV,
+       GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6,
 
        /* PTR */
        GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3,
index 829e89cfcee2deff8b937806b16dd573d736a895..9fb9a1f1e47bd0d0db3f9be9d4722f956d48dcfe 100644 (file)
@@ -4409,10 +4409,9 @@ static __init int fixup_ht_bug(void)
                return 0;
        }
 
-       if (lockup_detector_suspend() != 0) {
-               pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
-               return 0;
-       }
+       cpus_read_lock();
+
+       hardlockup_detector_perf_stop();
 
        x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
 
@@ -4420,9 +4419,7 @@ static __init int fixup_ht_bug(void)
        x86_pmu.commit_scheduling = NULL;
        x86_pmu.stop_scheduling = NULL;
 
-       lockup_detector_resume();
-
-       cpus_read_lock();
+       hardlockup_detector_perf_restart();
 
        for_each_online_cpu(c)
                free_excl_cntrs(c);
index bc62e7cbf1b1f883fc9acb0a145305384a3bf062..59ad3d132353280cae5a1ba4f3a8ae0efe996331 100644 (file)
@@ -88,7 +88,7 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
 bool kvm_para_available(void);
 unsigned int kvm_arch_para_features(void);
 void __init kvm_guest_init(void);
-void kvm_async_pf_task_wait(u32 token);
+void kvm_async_pf_task_wait(u32 token, int interrupt_kernel);
 void kvm_async_pf_task_wake(u32 token);
 u32 kvm_read_and_reset_pf_reason(void);
 extern void kvm_disable_steal_time(void);
@@ -103,7 +103,7 @@ static inline void kvm_spinlock_init(void)
 
 #else /* CONFIG_KVM_GUEST */
 #define kvm_guest_init() do {} while (0)
-#define kvm_async_pf_task_wait(T) do {} while(0)
+#define kvm_async_pf_task_wait(T, I) do {} while(0)
 #define kvm_async_pf_task_wake(T) do {} while(0)
 
 static inline bool kvm_para_available(void)
index e675704fa6f7d89ed919631284156717e342979f..8bb9594d076166ee0f6bd4f70350fe3ecf8c3d8b 100644 (file)
@@ -117,7 +117,11 @@ static struct kvm_task_sleep_node *_find_apf_task(struct kvm_task_sleep_head *b,
        return NULL;
 }
 
-void kvm_async_pf_task_wait(u32 token)
+/*
+ * @interrupt_kernel: Is this called from a routine which interrupts the kernel
+ *                   (other than user space)?
+ */
+void kvm_async_pf_task_wait(u32 token, int interrupt_kernel)
 {
        u32 key = hash_32(token, KVM_TASK_SLEEP_HASHBITS);
        struct kvm_task_sleep_head *b = &async_pf_sleepers[key];
@@ -140,8 +144,10 @@ void kvm_async_pf_task_wait(u32 token)
 
        n.token = token;
        n.cpu = smp_processor_id();
-       n.halted = is_idle_task(current) || preempt_count() > 1 ||
-                  rcu_preempt_depth();
+       n.halted = is_idle_task(current) ||
+                  (IS_ENABLED(CONFIG_PREEMPT_COUNT)
+                   ? preempt_count() > 1 || rcu_preempt_depth()
+                   : interrupt_kernel);
        init_swait_queue_head(&n.wq);
        hlist_add_head(&n.link, &b->list);
        raw_spin_unlock(&b->lock);
@@ -269,7 +275,7 @@ do_async_page_fault(struct pt_regs *regs, unsigned long error_code)
        case KVM_PV_REASON_PAGE_NOT_PRESENT:
                /* page is swapped out by the host. */
                prev_state = exception_enter();
-               kvm_async_pf_task_wait((u32)read_cr2());
+               kvm_async_pf_task_wait((u32)read_cr2(), !user_mode(regs));
                exception_exit(prev_state);
                break;
        case KVM_PV_REASON_PAGE_READY:
index 3ea624452f9327d252dda724100bd6e97f8c6e0c..3c48bc8bf08c7bc6afe896a2dae21d4f22d8f58e 100644 (file)
@@ -23,6 +23,7 @@ config KVM
        depends on HIGH_RES_TIMERS
        # for TASKSTATS/TASK_DELAY_ACCT:
        depends on NET && MULTIUSER
+       depends on X86_LOCAL_APIC
        select PREEMPT_NOTIFIERS
        select MMU_NOTIFIER
        select ANON_INODES
index a36254cbf7765aabf3e77c45e7cc82c3e3ff0fbb..d90cdc77e077354f1407235e6b73f2fda21c430c 100644 (file)
@@ -425,8 +425,10 @@ static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
        #op " %al \n\t" \
        FOP_RET
 
-asm(".global kvm_fastop_exception \n"
-    "kvm_fastop_exception: xor %esi, %esi; ret");
+asm(".pushsection .fixup, \"ax\"\n"
+    ".global kvm_fastop_exception \n"
+    "kvm_fastop_exception: xor %esi, %esi; ret\n"
+    ".popsection");
 
 FOP_START(setcc)
 FOP_SETCC(seto)
index eca30c1eb1d97cd367c6b2b76396991b79328b1a..106d4a029a8a933ad3865a11a5e2c1a11810e714 100644 (file)
@@ -3837,7 +3837,7 @@ int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
        case KVM_PV_REASON_PAGE_NOT_PRESENT:
                vcpu->arch.apf.host_apf_reason = 0;
                local_irq_disable();
-               kvm_async_pf_task_wait(fault_address);
+               kvm_async_pf_task_wait(fault_address, 0);
                local_irq_enable();
                break;
        case KVM_PV_REASON_PAGE_READY:
index 8c9573660d51e6b0297e4464b3af2056d93b9f3c..0554e8aef4d54522393f78b8b7973f8dfac4750c 100644 (file)
@@ -284,9 +284,9 @@ static void emit_bpf_tail_call(u8 **pprog)
        /* if (index >= array->map.max_entries)
         *   goto out;
         */
-       EMIT4(0x48, 0x8B, 0x46,                   /* mov rax, qword ptr [rsi + 16] */
+       EMIT2(0x89, 0xD2);                        /* mov edx, edx */
+       EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
              offsetof(struct bpf_array, map.max_entries));
-       EMIT3(0x48, 0x39, 0xD0);                  /* cmp rax, rdx */
 #define OFFSET1 43 /* number of bytes to jump */
        EMIT2(X86_JBE, OFFSET1);                  /* jbe out */
        label1 = cnt;
index 980e7309564332ee1c23e0d96b13996f27c0aeca..de294d775acfa413854c109eeaa08b9b6bdfd354 100644 (file)
@@ -815,10 +815,14 @@ int blk_mq_debugfs_register(struct request_queue *q)
                goto err;
 
        /*
-        * blk_mq_init_hctx() attempted to do this already, but q->debugfs_dir
+        * blk_mq_init_sched() attempted to do this already, but q->debugfs_dir
         * didn't exist yet (because we don't know what to name the directory
         * until the queue is registered to a gendisk).
         */
+       if (q->elevator && !q->sched_debugfs_dir)
+               blk_mq_debugfs_register_sched(q);
+
+       /* Similarly, blk_mq_init_hctx() couldn't do this previously. */
        queue_for_each_hw_ctx(q, hctx, i) {
                if (!hctx->debugfs_dir && blk_mq_debugfs_register_hctx(q, hctx))
                        goto err;
index 0fea76aa0f3ff0093c4867f10139d331589df53a..17816a028dcbb6fb7f7fe4e068fb90f313448ebf 100644 (file)
@@ -1911,11 +1911,11 @@ static void throtl_upgrade_state(struct throtl_data *td)
 
                tg->disptime = jiffies - 1;
                throtl_select_dispatch(sq);
-               throtl_schedule_next_dispatch(sq, false);
+               throtl_schedule_next_dispatch(sq, true);
        }
        rcu_read_unlock();
        throtl_select_dispatch(&td->service_queue);
-       throtl_schedule_next_dispatch(&td->service_queue, false);
+       throtl_schedule_next_dispatch(&td->service_queue, true);
        queue_work(kthrotld_workqueue, &td->dispatch_work);
 }
 
index dbddff8174e57a92d09f5bdc9cc83ee6f7217eb9..15d25ccd51a5cad7c9505427888f88c15a9e5d99 100644 (file)
@@ -207,20 +207,34 @@ static int bsg_init_rq(struct request_queue *q, struct request *req, gfp_t gfp)
        struct bsg_job *job = blk_mq_rq_to_pdu(req);
        struct scsi_request *sreq = &job->sreq;
 
+       /* called right after the request is allocated for the request_queue */
+
+       sreq->sense = kzalloc(SCSI_SENSE_BUFFERSIZE, gfp);
+       if (!sreq->sense)
+               return -ENOMEM;
+
+       return 0;
+}
+
+static void bsg_initialize_rq(struct request *req)
+{
+       struct bsg_job *job = blk_mq_rq_to_pdu(req);
+       struct scsi_request *sreq = &job->sreq;
+       void *sense = sreq->sense;
+
+       /* called right before the request is given to the request_queue user */
+
        memset(job, 0, sizeof(*job));
 
        scsi_req_init(sreq);
+
+       sreq->sense = sense;
        sreq->sense_len = SCSI_SENSE_BUFFERSIZE;
-       sreq->sense = kzalloc(sreq->sense_len, gfp);
-       if (!sreq->sense)
-               return -ENOMEM;
 
        job->req = req;
-       job->reply = sreq->sense;
+       job->reply = sense;
        job->reply_len = sreq->sense_len;
        job->dd_data = job + 1;
-
-       return 0;
 }
 
 static void bsg_exit_rq(struct request_queue *q, struct request *req)
@@ -251,6 +265,7 @@ struct request_queue *bsg_setup_queue(struct device *dev, const char *name,
        q->cmd_size = sizeof(struct bsg_job) + dd_job_size;
        q->init_rq_fn = bsg_init_rq;
        q->exit_rq_fn = bsg_exit_rq;
+       q->initialize_rq_fn = bsg_initialize_rq;
        q->request_fn = bsg_request_fn;
 
        ret = blk_init_allocated_queue(q);
index 9565d572f8dd2f3d65c0e16b8257f61100bbad50..de56394dd161f7813b7f5bce64321d3196bc4904 100644 (file)
@@ -1178,12 +1178,44 @@ dev_put:
        return ret;
 }
 
+static bool __init iort_enable_acs(struct acpi_iort_node *iort_node)
+{
+       if (iort_node->type == ACPI_IORT_NODE_PCI_ROOT_COMPLEX) {
+               struct acpi_iort_node *parent;
+               struct acpi_iort_id_mapping *map;
+               int i;
+
+               map = ACPI_ADD_PTR(struct acpi_iort_id_mapping, iort_node,
+                                  iort_node->mapping_offset);
+
+               for (i = 0; i < iort_node->mapping_count; i++, map++) {
+                       if (!map->output_reference)
+                               continue;
+
+                       parent = ACPI_ADD_PTR(struct acpi_iort_node,
+                                       iort_table,  map->output_reference);
+                       /*
+                        * If we detect a RC->SMMU mapping, make sure
+                        * we enable ACS on the system.
+                        */
+                       if ((parent->type == ACPI_IORT_NODE_SMMU) ||
+                               (parent->type == ACPI_IORT_NODE_SMMU_V3)) {
+                               pci_request_acs();
+                               return true;
+                       }
+               }
+       }
+
+       return false;
+}
+
 static void __init iort_init_platform_devices(void)
 {
        struct acpi_iort_node *iort_node, *iort_end;
        struct acpi_table_iort *iort;
        struct fwnode_handle *fwnode;
        int i, ret;
+       bool acs_enabled = false;
 
        /*
         * iort_table and iort both point to the start of IORT table, but
@@ -1203,6 +1235,9 @@ static void __init iort_init_platform_devices(void)
                        return;
                }
 
+               if (!acs_enabled)
+                       acs_enabled = iort_enable_acs(iort_node);
+
                if ((iort_node->type == ACPI_IORT_NODE_SMMU) ||
                        (iort_node->type == ACPI_IORT_NODE_SMMU_V3)) {
 
index d055b3f2a2078cedb078b3359777146c66c910a9..ab34239a76ee53fbb3dc62b0f37b30eaf3a9031e 100644 (file)
@@ -2217,7 +2217,7 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
                                       debug_id, (u64)fda->num_fds);
                                continue;
                        }
-                       fd_array = (u32 *)(parent_buffer + fda->parent_offset);
+                       fd_array = (u32 *)(parent_buffer + (uintptr_t)fda->parent_offset);
                        for (fd_index = 0; fd_index < fda->num_fds; fd_index++)
                                task_close_fd(proc, fd_array[fd_index]);
                } break;
@@ -2326,7 +2326,6 @@ static int binder_translate_handle(struct flat_binder_object *fp,
                             (u64)node->ptr);
                binder_node_unlock(node);
        } else {
-               int ret;
                struct binder_ref_data dest_rdata;
 
                binder_node_unlock(node);
@@ -2442,7 +2441,7 @@ static int binder_translate_fd_array(struct binder_fd_array_object *fda,
         */
        parent_buffer = parent->buffer -
                binder_alloc_get_user_buffer_offset(&target_proc->alloc);
-       fd_array = (u32 *)(parent_buffer + fda->parent_offset);
+       fd_array = (u32 *)(parent_buffer + (uintptr_t)fda->parent_offset);
        if (!IS_ALIGNED((unsigned long)fd_array, sizeof(u32))) {
                binder_user_error("%d:%d parent offset not aligned correctly.\n",
                                  proc->pid, thread->pid);
@@ -2508,7 +2507,7 @@ static int binder_fixup_parent(struct binder_transaction *t,
                                  proc->pid, thread->pid);
                return -EINVAL;
        }
-       parent_buffer = (u8 *)(parent->buffer -
+       parent_buffer = (u8 *)((uintptr_t)parent->buffer -
                        binder_alloc_get_user_buffer_offset(
                                &target_proc->alloc));
        *(binder_uintptr_t *)(parent_buffer + bp->parent_offset) = bp->buffer;
@@ -3083,6 +3082,7 @@ static void binder_transaction(struct binder_proc *proc,
 err_dead_proc_or_thread:
        return_error = BR_DEAD_REPLY;
        return_error_line = __LINE__;
+       binder_dequeue_work(proc, tcomplete);
 err_translate_failed:
 err_bad_object_type:
 err_bad_offset:
index 8fe165844e4708a3646a69384fe55db592fbe87f..064f5e31ec55253e830740b4f99f3ba15ee20f1f 100644 (file)
@@ -913,6 +913,7 @@ enum lru_status binder_alloc_free_page(struct list_head *item,
        struct binder_alloc *alloc;
        uintptr_t page_addr;
        size_t index;
+       struct vm_area_struct *vma;
 
        alloc = page->alloc;
        if (!mutex_trylock(&alloc->mutex))
@@ -923,16 +924,22 @@ enum lru_status binder_alloc_free_page(struct list_head *item,
 
        index = page - alloc->pages;
        page_addr = (uintptr_t)alloc->buffer + index * PAGE_SIZE;
-       if (alloc->vma) {
+       vma = alloc->vma;
+       if (vma) {
                mm = get_task_mm(alloc->tsk);
                if (!mm)
                        goto err_get_task_mm_failed;
                if (!down_write_trylock(&mm->mmap_sem))
                        goto err_down_write_mmap_sem_failed;
+       }
+
+       list_lru_isolate(lru, item);
+       spin_unlock(lock);
 
+       if (vma) {
                trace_binder_unmap_user_start(alloc, index);
 
-               zap_page_range(alloc->vma,
+               zap_page_range(vma,
                               page_addr + alloc->user_buffer_offset,
                               PAGE_SIZE);
 
@@ -950,13 +957,12 @@ enum lru_status binder_alloc_free_page(struct list_head *item,
 
        trace_binder_unmap_kernel_end(alloc, index);
 
-       list_lru_isolate(lru, item);
-
+       spin_lock(lock);
        mutex_unlock(&alloc->mutex);
-       return LRU_REMOVED;
+       return LRU_REMOVED_RETRY;
 
 err_down_write_mmap_sem_failed:
-       mmput(mm);
+       mmput_async(mm);
 err_get_task_mm_failed:
 err_page_already_freed:
        mutex_unlock(&alloc->mutex);
index cb9b0e9090e3b8ec7e32fff751b1e34332cb7068..9f78bb03bb763c8ba9577ffce47c405c9fa7fb27 100644 (file)
@@ -621,8 +621,11 @@ static void ahci_pci_save_initial_config(struct pci_dev *pdev,
 static int ahci_pci_reset_controller(struct ata_host *host)
 {
        struct pci_dev *pdev = to_pci_dev(host->dev);
+       int rc;
 
-       ahci_reset_controller(host);
+       rc = ahci_reset_controller(host);
+       if (rc)
+               return rc;
 
        if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
                struct ahci_host_priv *hpriv = host->private_data;
index 8401c3b5be921335492ccc3f76f0a7d229306ec0..b702c20fbc2bbb2d9ebcb6188e5e1f522adf9271 100644 (file)
@@ -492,6 +492,7 @@ static const struct ich_laptop ich_laptop[] = {
        { 0x27DF, 0x152D, 0x0778 },     /* ICH7 on unknown Intel */
        { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on ACER Aspire 2023WLMi */
        { 0x24CA, 0x1025, 0x003d },     /* ICH4 on ACER TM290 */
+       { 0x24CA, 0x10CF, 0x11AB },     /* ICH4M on Fujitsu-Siemens Lifebook S6120 */
        { 0x266F, 0x1025, 0x0066 },     /* ICH6 on ACER Aspire 1694WLMi */
        { 0x2653, 0x1043, 0x82D8 },     /* ICH6M on Asus Eee 701 */
        { 0x27df, 0x104d, 0x900e },     /* ICH7 on Sony TZ-90 */
index 1945a8ea20998490b48aa70dfe56c4fbaad744ea..ee4c1ec9dca0ef9e51f4abf56924aab2112d9f77 100644 (file)
@@ -3234,19 +3234,19 @@ static const struct ata_timing ata_timing[] = {
 };
 
 #define ENOUGH(v, unit)                (((v)-1)/(unit)+1)
-#define EZ(v, unit)            ((v)?ENOUGH(v, unit):0)
+#define EZ(v, unit)            ((v)?ENOUGH(((v) * 1000), unit):0)
 
 static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
 {
-       q->setup        = EZ(t->setup      * 1000,  T);
-       q->act8b        = EZ(t->act8b      * 1000,  T);
-       q->rec8b        = EZ(t->rec8b      * 1000,  T);
-       q->cyc8b        = EZ(t->cyc8b      * 1000,  T);
-       q->active       = EZ(t->active     * 1000,  T);
-       q->recover      = EZ(t->recover    * 1000,  T);
-       q->dmack_hold   = EZ(t->dmack_hold * 1000,  T);
-       q->cycle        = EZ(t->cycle      * 1000,  T);
-       q->udma         = EZ(t->udma       * 1000, UT);
+       q->setup        = EZ(t->setup,       T);
+       q->act8b        = EZ(t->act8b,       T);
+       q->rec8b        = EZ(t->rec8b,       T);
+       q->cyc8b        = EZ(t->cyc8b,       T);
+       q->active       = EZ(t->active,      T);
+       q->recover      = EZ(t->recover,     T);
+       q->dmack_hold   = EZ(t->dmack_hold,  T);
+       q->cycle        = EZ(t->cycle,       T);
+       q->udma         = EZ(t->udma,       UT);
 }
 
 void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
index cfeb049a01ef84425672682c50acb492cbfb04eb..642afd88870ba99ef1c79db74b457515079684b7 100644 (file)
@@ -647,18 +647,25 @@ static ssize_t charlcd_write(struct file *file, const char __user *buf,
 static int charlcd_open(struct inode *inode, struct file *file)
 {
        struct charlcd_priv *priv = to_priv(the_charlcd);
+       int ret;
 
+       ret = -EBUSY;
        if (!atomic_dec_and_test(&charlcd_available))
-               return -EBUSY;  /* open only once at a time */
+               goto fail;      /* open only once at a time */
 
+       ret = -EPERM;
        if (file->f_mode & FMODE_READ)  /* device is write-only */
-               return -EPERM;
+               goto fail;
 
        if (priv->must_clear) {
                charlcd_clear_display(&priv->lcd);
                priv->must_clear = false;
        }
        return nonseekable_open(inode, file);
+
+ fail:
+       atomic_inc(&charlcd_available);
+       return ret;
 }
 
 static int charlcd_release(struct inode *inode, struct file *file)
index df126dcdaf18e1b84951426b6f501810036a64a3..6911acd896d935946b3c805d07c88bc03bf41918 100644 (file)
@@ -1105,14 +1105,21 @@ static ssize_t keypad_read(struct file *file,
 
 static int keypad_open(struct inode *inode, struct file *file)
 {
+       int ret;
+
+       ret = -EBUSY;
        if (!atomic_dec_and_test(&keypad_available))
-               return -EBUSY;  /* open only once at a time */
+               goto fail;      /* open only once at a time */
 
+       ret = -EPERM;
        if (file->f_mode & FMODE_WRITE) /* device is read-only */
-               return -EPERM;
+               goto fail;
 
        keypad_buflen = 0;      /* flush the buffer on opening */
        return 0;
+ fail:
+       atomic_inc(&keypad_available);
+       return ret;
 }
 
 static int keypad_release(struct inode *inode, struct file *file)
index 41be9ff7d70a96d7d901918c6186ea3be035f88c..6df7d6676a48104267b5e739c6e58b85a00724e1 100644 (file)
@@ -166,11 +166,11 @@ bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
 }
 
 #ifdef CONFIG_CPU_FREQ
-static cpumask_var_t cpus_to_visit;
-static void parsing_done_workfn(struct work_struct *work);
-static DECLARE_WORK(parsing_done_work, parsing_done_workfn);
+static cpumask_var_t cpus_to_visit __initdata;
+static void __init parsing_done_workfn(struct work_struct *work);
+static __initdata DECLARE_WORK(parsing_done_work, parsing_done_workfn);
 
-static int
+static int __init
 init_cpu_capacity_callback(struct notifier_block *nb,
                           unsigned long val,
                           void *data)
@@ -206,7 +206,7 @@ init_cpu_capacity_callback(struct notifier_block *nb,
        return 0;
 }
 
-static struct notifier_block init_cpu_capacity_notifier = {
+static struct notifier_block init_cpu_capacity_notifier __initdata = {
        .notifier_call = init_cpu_capacity_callback,
 };
 
@@ -232,7 +232,7 @@ static int __init register_cpufreq_notifier(void)
 }
 core_initcall(register_cpufreq_notifier);
 
-static void parsing_done_workfn(struct work_struct *work)
+static void __init parsing_done_workfn(struct work_struct *work)
 {
        cpufreq_unregister_notifier(&init_cpu_capacity_notifier,
                                         CPUFREQ_POLICY_NOTIFIER);
index d1bd9927106638d7ad94b5cec29650942453b98a..9045c5f3734e8df88d19ec58106e01efbe8f5a31 100644 (file)
@@ -868,7 +868,8 @@ static ssize_t driver_override_store(struct device *dev,
        struct platform_device *pdev = to_platform_device(dev);
        char *driver_override, *old, *cp;
 
-       if (count > PATH_MAX)
+       /* We need to keep extra room for a newline */
+       if (count >= (PAGE_SIZE - 1))
                return -EINVAL;
 
        driver_override = kstrndup(buf, count, GFP_KERNEL);
index 4a438b8abe27ad9c1774c89f608bd47fecc295a3..2dfe99b328f88e35d812b34bd4a48e3392fe5819 100644 (file)
@@ -17,7 +17,7 @@ if BLK_DEV
 
 config BLK_DEV_NULL_BLK
        tristate "Null test block driver"
-       depends on CONFIGFS_FS
+       select CONFIGFS_FS
 
 config BLK_DEV_FD
        tristate "Normal floppy disk support"
index 3684e21d543f23e95bda09fb895e8933b9bce186..883dfebd3014b506a0861aed0640dc313fd8b0cc 100644 (file)
@@ -820,9 +820,13 @@ static blk_status_t nbd_queue_rq(struct blk_mq_hw_ctx *hctx,
         * appropriate.
         */
        ret = nbd_handle_cmd(cmd, hctx->queue_num);
+       if (ret < 0)
+               ret = BLK_STS_IOERR;
+       else if (!ret)
+               ret = BLK_STS_OK;
        complete(&cmd->send_complete);
 
-       return ret < 0 ? BLK_STS_IOERR : BLK_STS_OK;
+       return ret;
 }
 
 static int nbd_add_socket(struct nbd_device *nbd, unsigned long arg,
index 2981c27d3aae316fedd267c6c79d76eb68a9395e..f149d3e612341d1f5e70797a8f62d0330fa3973d 100644 (file)
@@ -766,27 +766,6 @@ static void zram_slot_unlock(struct zram *zram, u32 index)
        bit_spin_unlock(ZRAM_ACCESS, &zram->table[index].value);
 }
 
-static bool zram_same_page_read(struct zram *zram, u32 index,
-                               struct page *page,
-                               unsigned int offset, unsigned int len)
-{
-       zram_slot_lock(zram, index);
-       if (unlikely(!zram_get_handle(zram, index) ||
-                       zram_test_flag(zram, index, ZRAM_SAME))) {
-               void *mem;
-
-               zram_slot_unlock(zram, index);
-               mem = kmap_atomic(page);
-               zram_fill_page(mem + offset, len,
-                                       zram_get_element(zram, index));
-               kunmap_atomic(mem);
-               return true;
-       }
-       zram_slot_unlock(zram, index);
-
-       return false;
-}
-
 static void zram_meta_free(struct zram *zram, u64 disksize)
 {
        size_t num_pages = disksize >> PAGE_SHIFT;
@@ -884,11 +863,20 @@ static int __zram_bvec_read(struct zram *zram, struct page *page, u32 index,</