arm64: Increase ARCH_DMA_MINALIGN to 128
authorCatalin Marinas <catalin.marinas@arm.com>
Fri, 11 May 2018 12:33:12 +0000 (13:33 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Tue, 15 May 2018 12:29:55 +0000 (13:29 +0100)
commitebc7e21e0fa28c46b938baed292c77e2d3ef8165
treefa415205a2ea1ff232aee0b7a6c4e998837b77ef
parentd93277b9839b0bde06238a7a7f644114edb2ad4a
arm64: Increase ARCH_DMA_MINALIGN to 128

This patch increases the ARCH_DMA_MINALIGN to 128 so that it covers the
currently known Cache Writeback Granule (CTR_EL0.CWG) on arm64 and moves
the fallback in cache_line_size() from L1_CACHE_BYTES to this constant.
In addition, it warns (and taints) if the CWG is larger than
ARCH_DMA_MINALIGN as this is not safe with non-coherent DMA.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/include/asm/cache.h
arch/arm64/kernel/cpufeature.c
arch/arm64/mm/dma-mapping.c