x86/asm/64: Use 32-bit XOR to zero registers
authorJan Beulich <JBeulich@suse.com>
Mon, 2 Jul 2018 10:31:54 +0000 (04:31 -0600)
committerIngo Molnar <mingo@kernel.org>
Tue, 3 Jul 2018 07:59:29 +0000 (09:59 +0200)
commita7bea8308933aaeea76dad7d42a6e51000417626
tree66116addaa65ed59f9b8685911571fdeeb7df6f5
parentc5fcdbf15523f6bbbaeb822e3be6003e60f9d3b7
x86/asm/64: Use 32-bit XOR to zero registers

Some Intel CPUs don't recognize 64-bit XORs as zeroing idioms. Zeroing
idioms don't require execution bandwidth, as they're being taken care
of in the frontend (through register renaming). Use 32-bit XORs instead.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Cc: Alok Kataria <akataria@vmware.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: herbert@gondor.apana.org.au
Cc: pavel@ucw.cz
Cc: rjw@rjwysocki.net
Link: http://lkml.kernel.org/r/5B39FF1A02000078001CFB54@prv1-mh.provo.novell.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
13 files changed:
arch/x86/crypto/aegis128-aesni-asm.S
arch/x86/crypto/aegis128l-aesni-asm.S
arch/x86/crypto/aegis256-aesni-asm.S
arch/x86/crypto/aesni-intel_asm.S
arch/x86/crypto/aesni-intel_avx-x86_64.S
arch/x86/crypto/morus1280-avx2-asm.S
arch/x86/crypto/morus1280-sse2-asm.S
arch/x86/crypto/morus640-sse2-asm.S
arch/x86/crypto/sha1_ssse3_asm.S
arch/x86/kernel/head_64.S
arch/x86/kernel/paravirt_patch_64.c
arch/x86/lib/memcpy_64.S
arch/x86/power/hibernate_asm_64.S