clk: uniphier: fix DAPLL2 clock rate of Pro5
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Thu, 5 Oct 2017 02:32:59 +0000 (11:32 +0900)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 14 Nov 2017 18:04:07 +0000 (10:04 -0800)
commit67affb78a4e4feb837953e3434c8402a5c3b272f
tree70b229c8ac60c2e509cd09df75a0b978d8224f0e
parent3a5dfa7d78976fd712b63b3db4357d94dcd3c5ba
clk: uniphier: fix DAPLL2 clock rate of Pro5

The parent of DAPLL2 should be DAPLL1.  Fix the clock connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/uniphier/clk-uniphier-sys.c