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(parent: accf475) | patch
clk: aspeed: Handle inverse polarity of USB port 1 clock gate
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 12 Jan 2018 05:48:01 +0000 (16:48 +1100)
committerStephen Boyd <sboyd@codeaurora.org>
Sat, 27 Jan 2018 00:22:48 +0000 (16:22 -0800)
commit6671507f0fbd582b4003f837ab791d03ade8e0f4
tree87615147b69008ac30cfcff53765d749fc73e979tree
parentaccf475a5ece972af58c81e0742035ed90ad41d2commit | diff
clk: aspeed: Handle inverse polarity of USB port 1 clock gate

The USB port 1 clock gate control has an inversed polarity
from all the other clock gates in the chip. This makes the
aspeed_clk_{enable,disable} functions honor the flag
CLK_GATE_SET_TO_DISABLE and set that flag appropriately
so it's set for all clocks except USB port 1.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-aspeed.c diff | blob | history
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