RISC-V: probes: Treat the instruction stream as host-endian
authorPalmer Dabbelt <palmerdabbelt@google.com>
Sat, 23 Jan 2021 03:34:29 +0000 (19:34 -0800)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Fri, 19 Feb 2021 07:18:02 +0000 (23:18 -0800)
commit5dd671333171d1ba44c16e1404f72788412e36f4
treee41905abd61331577a2add3263502d044029c028
parentd4c34d09ab03e1e631fe195ddf35365a1273be9c
RISC-V: probes: Treat the instruction stream as host-endian

Neither of these are actually correct: the instruction stream is defined
(for versions of the ISA manual newer than 2.2) as a stream of 16-bit
little-endian parcels, which is different than just being little-endian.
In theory we should represent this as a type, but we don't have any
concrete plans for the big endian stuff so it doesn't seem worth the
time -- we've got variants of this all over the place.

Instead I'm just dropping the unnecessary type conversion, which is a
NOP on LE systems but causes an sparse error as the types are all mixed
up.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
arch/riscv/kernel/probes/decode-insn.c
arch/riscv/kernel/probes/kprobes.c