cxl/port: Record parent dport when adding ports
authorDan Williams <dan.j.williams@intel.com>
Fri, 27 May 2022 17:57:01 +0000 (10:57 -0700)
committerDan Williams <dan.j.williams@intel.com>
Fri, 22 Jul 2022 00:19:24 +0000 (17:19 -0700)
commit1b58b4cac6fc6fab55f34f74087594125fc60b84
tree6b6685df5d82ea9e32c130945e23c2d91982b27a
parentde516b40116e98c60ee475e92108453686098c85
cxl/port: Record parent dport when adding ports

At the time that cxl_port instances are being created, cache the dport
from the parent port that points to this new child port. This will be
useful for region provisioning when walking the tree to calculate
decoder targets, and saves rewalking the dport list after the fact to
build this information.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220624041950.559155-1-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/acpi.c
drivers/cxl/core/port.c
drivers/cxl/cxl.h
drivers/cxl/mem.c