X-Git-Url: http://git.samba.org/samba.git/?p=sfrench%2Fcifs-2.6.git;a=blobdiff_plain;f=include%2Fasm-arm%2Farch-pxa%2Fpxa-regs.h;h=139c9d95481831c5dd65270bd9cada530fca8ce8;hp=68731e0923a4caebc86dd6134248ddc790691795;hb=53698d2537bc8c2b8fedc788b8b927da9a004f9b;hpb=cde49b058474ab3f7ff830283e5b538e8fbeefe5 diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 68731e0923a4..139c9d954818 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -99,7 +99,7 @@ #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ -#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ +#define DCSR_EORINTR (1 << 9) /* The end of Receive */ #endif #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ @@ -463,9 +463,6 @@ * Serial Audio Controller */ -/* FIXME: This clash with SA1111 defines */ -#ifndef _ASM_ARCH_SA1111 - #define SACR0 __REG(0x40400000) /* Global Control Register */ #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ @@ -474,8 +471,8 @@ #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ -#define SACR0_RFTH(x) (x << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ -#define SACR0_TFTH(x) (x << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ +#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ +#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ @@ -503,8 +500,6 @@ #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ -#endif - /* * AC97 Controller registers */ @@ -803,12 +798,11 @@ #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */ - +#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ +#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ +#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ +#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ +#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ @@ -1482,7 +1476,7 @@ #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) -#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_OUT) +#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) /* @@ -1627,7 +1621,7 @@ #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ -#define SSCR0_SlotsPerFrm(x) ((x) - 1) /* Time slots per frame [1..8] */ +#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ #define SSCR0_ADC (1 << 30) /* Audio clock select */ #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ #endif @@ -1656,6 +1650,7 @@ #define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ +#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ @@ -1682,15 +1677,18 @@ #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ -#define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */ -#define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */ -#define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */ -#define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */ -#define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */ +#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ +#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ +#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ +#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ +#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ -#define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */ +#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ +#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ +#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ +#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ #define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */ #define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */ @@ -2242,7 +2240,7 @@ #define CICR1_TBIT (1 << 31) /* Transparency bit */ #define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ -#define CICR1_PPL (0x3f << 15) /* Pixels per line mask */ +#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ #define CICR1_RGB_F (1 << 11) /* RGB format */ #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ @@ -2268,7 +2266,7 @@ #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock wait count mask */ -#define CICR3_LPF (0x3ff << 0) /* Lines per frame mask */ +#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ @@ -2289,8 +2287,8 @@ #define CISR_EOL (1 << 8) /* End of line */ #define CISR_PAR_ERR (1 << 7) /* Parity error */ #define CISR_CQD (1 << 6) /* Camera interface quick disable */ -#define CISR_SOF (1 << 5) /* Start of frame */ -#define CISR_CDD (1 << 4) /* Camera interface disable done */ +#define CISR_CDD (1 << 5) /* Camera interface disable done */ +#define CISR_SOF (1 << 4) /* Start of frame */ #define CISR_EOF (1 << 3) /* End of frame */ #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */