ASoC: nau8825: disable sinc filter for high THD of ADC

[sfrench/cifs-2.6.git] / sound / soc / codecs / nau8825.h

diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h
index 1c63e2abafa99cddc7f9a2577e0e088803a68214..5d1704e732415dd04134f44ddab9971156c97de1 100644 (file)
--- a/sound/soc/codecs/nau8825.h
+++ b/sound/soc/codecs/nau8825.h
@@ -115,12 +115,20 @@
 #define NAU8825_CLK_SRC_MASK                   (1 << NAU8825_CLK_SRC_SFT)
 #define NAU8825_CLK_SRC_VCO                    (1 << NAU8825_CLK_SRC_SFT)
 #define NAU8825_CLK_SRC_MCLK                   (0 << NAU8825_CLK_SRC_SFT)
+#define NAU8825_CLK_ADC_SRC_SFT                6
+#define NAU8825_CLK_ADC_SRC_MASK               (0x3 << NAU8825_CLK_ADC_SRC_SFT)
+#define NAU8825_CLK_DAC_SRC_SFT                4
+#define NAU8825_CLK_DAC_SRC_MASK               (0x3 << NAU8825_CLK_DAC_SRC_SFT)
 #define NAU8825_CLK_MCLK_SRC_MASK              (0xf << 0)
 
 /* FLL1 (0x04) */
+#define NAU8825_ICTRL_LATCH_SFT        10
+#define NAU8825_ICTRL_LATCH_MASK       (0x7 << NAU8825_ICTRL_LATCH_SFT)
 #define NAU8825_FLL_RATIO_MASK                 (0x7f << 0)
 
 /* FLL3 (0x06) */
+#define NAU8825_GAIN_ERR_SFT                   12
+#define NAU8825_GAIN_ERR_MASK                  (0xf << NAU8825_GAIN_ERR_SFT)
 #define NAU8825_FLL_INTEGER_MASK               (0x3ff << 0)
 #define NAU8825_FLL_CLK_SRC_SFT                10
 #define NAU8825_FLL_CLK_SRC_MASK               (0x3 << NAU8825_FLL_CLK_SRC_SFT)
@@ -144,6 +152,7 @@
 /* FLL6 (0x9) */
 #define NAU8825_DCO_EN                         (0x1 << 15)
 #define NAU8825_SDM_EN                         (0x1 << 14)
+#define NAU8825_CUTOFF500                      (0x1 << 13)
 
 /* HSD_CTRL (0xc) */
 #define NAU8825_HSD_AUTO_MODE  (1 << 6)
@@ -246,6 +255,11 @@
 #define NAU8825_I2S_MS_SLAVE   (0 << NAU8825_I2S_MS_SFT)
 #define NAU8825_I2S_BLK_DIV_MASK       0x7
 
+/* LEFT_TIME_SLOT (0x1e) */
+#define NAU8825_FS_ERR_CMP_SEL_SFT     14
+#define NAU8825_FS_ERR_CMP_SEL_MASK    (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT)
+#define NAU8825_DIS_FS_SHORT_DET       (1 << 13)
+
 /* BIQ_CTRL (0x20) */
 #define NAU8825_BIQ_WRT_SFT   4
 #define NAU8825_BIQ_WRT_EN     (1 << NAU8825_BIQ_WRT_SFT)
@@ -255,6 +269,8 @@
 #define NAU8825_BIQ_PATH_DAC   (1 << NAU8825_BIQ_PATH_SFT)
 
 /* ADC_RATE (0x2b) */
+#define NAU8825_ADC_SINC4_SFT          4
+#define NAU8825_ADC_SINC4_EN           (1 << NAU8825_ADC_SINC4_SFT)
 #define NAU8825_ADC_SYNC_DOWN_SFT      0
 #define NAU8825_ADC_SYNC_DOWN_MASK     0x3
 #define NAU8825_ADC_SYNC_DOWN_32       0