__u32 num_low_latency_bfregs;
};
+enum mlx5_lib_caps {
+ MLX5_LIB_CAP_4K_UAR = (u64)1 << 0,
+};
+
struct mlx5_ib_alloc_ucontext_req_v2 {
__u32 total_num_bfregs;
__u32 num_low_latency_bfregs;
__u8 reserved0;
__u16 reserved1;
__u32 reserved2;
+ __u64 lib_caps;
};
enum mlx5_ib_alloc_ucontext_resp_mask {
__u8 cmds_supp_uhw;
__u16 reserved2;
__u64 hca_core_clock_offset;
+ __u32 log_uar_size;
+ __u32 num_uars_per_page;
};
struct mlx5_ib_alloc_pd_resp {