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net/mlx5: Add PPCNT physical layer statistical group infrastructure
[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index a852e9db6f0d5ec809cfc0e5245d1ee3fff7c36b..f4860fa719d9398fa56149f7c2b31cd2cd344fe7 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -328,7 +328,7 @@ struct mlx5_ifc_odp_per_transport_service_cap_bits {
        u8         receive[0x1];
        u8         write[0x1];
        u8         read[0x1];
-       u8         reserved_at_4[0x1];
+       u8         atomic[0x1];
        u8         srq_receive[0x1];
        u8         reserved_at_6[0x1a];
 };
@@ -365,8 +365,8 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
        u8         ip_protocol[0x8];
        u8         ip_dscp[0x6];
        u8         ip_ecn[0x2];
-       u8         vlan_tag[0x1];
-       u8         reserved_at_91[0x1];
+       u8         cvlan_tag[0x1];
+       u8         svlan_tag[0x1];
        u8         frag[0x1];
        u8         reserved_at_93[0x4];
        u8         tcp_flags[0x9];
@@ -398,9 +398,11 @@ struct mlx5_ifc_fte_match_set_misc_bits {
        u8         inner_second_cfi[0x1];
        u8         inner_second_vid[0xc];
 
-       u8         outer_second_vlan_tag[0x1];
-       u8         inner_second_vlan_tag[0x1];
-       u8         reserved_at_62[0xe];
+       u8         outer_second_cvlan_tag[0x1];
+       u8         inner_second_cvlan_tag[0x1];
+       u8         outer_second_svlan_tag[0x1];
+       u8         inner_second_svlan_tag[0x1];
+       u8         reserved_at_64[0xc];
        u8         gre_protocol[0x10];
 
        u8         gre_key_h[0x18];
@@ -782,11 +784,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         log_max_eq[0x4];
 
        u8         max_indirection[0x8];
-       u8         reserved_at_108[0x1];
+       u8         fixed_buffer_size[0x1];
        u8         log_max_mrw_sz[0x7];
        u8         reserved_at_110[0x2];
        u8         log_max_bsf_list_size[0x6];
-       u8         reserved_at_118[0x2];
+       u8         umr_extended_translation_offset[0x1];
+       u8         null_mkey[0x1];
        u8         log_max_klm_list_size[0x6];
 
        u8         reserved_at_120[0xa];
@@ -823,18 +826,21 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         nic_flow_table[0x1];
        u8         eswitch_flow_table[0x1];
        u8         early_vf_enable[0x1];
-       u8         reserved_at_1a9[0x2];
+       u8         mcam_reg[0x1];
+       u8         pcam_reg[0x1];
        u8         local_ca_ack_delay[0x5];
        u8         port_module_event[0x1];
-       u8         reserved_at_1b0[0x1];
+       u8         reserved_at_1b1[0x1];
        u8         ports_check[0x1];
-       u8         reserved_at_1b2[0x1];
+       u8         reserved_at_1b3[0x1];
        u8         disable_link_up[0x1];
        u8         beacon_led[0x1];
        u8         port_type[0x2];
        u8         num_ports[0x8];
 
-       u8         reserved_at_1c0[0x3];
+       u8         reserved_at_1c0[0x1];
+       u8         pps[0x1];
+       u8         pps_modify[0x1];
        u8         log_max_msg[0x5];
        u8         reserved_at_1c8[0x4];
        u8         max_tc[0x4];
@@ -858,7 +864,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 
        u8         compact_address_vector[0x1];
        u8         striding_rq[0x1];
-       u8         reserved_at_201[0x2];
+       u8         reserved_at_202[0x2];
        u8         ipoib_basic_offloads[0x1];
        u8         reserved_at_205[0xa];
        u8         drain_sigerr[0x1];
@@ -904,7 +910,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         uc[0x1];
        u8         rc[0x1];
 
-       u8         reserved_at_240[0xa];
+       u8         uar_4k[0x1];
+       u8         reserved_at_241[0x9];
        u8         uar_sz[0x6];
        u8         reserved_at_250[0x8];
        u8         log_pg_sz[0x8];
@@ -996,7 +1003,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         device_frequency_mhz[0x20];
        u8         device_frequency_khz[0x20];
 
-       u8         reserved_at_500[0x80];
+       u8         reserved_at_500[0x20];
+       u8         num_of_uars_per_page[0x20];
+       u8         reserved_at_540[0x40];
 
        u8         reserved_at_580[0x3f];
        u8         cqe_compression[0x1];
@@ -1009,10 +1018,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         rndv_offload_rc[0x1];
        u8         rndv_offload_dc[0x1];
        u8         log_tag_matching_list_sz[0x5];
-       u8         reserved_at_5e8[0x3];
+       u8         reserved_at_5f8[0x3];
        u8         log_max_xrq[0x5];
 
-       u8         reserved_at_5f0[0x200];
+       u8         reserved_at_600[0x200];
 };
 
 enum mlx5_flow_destination_type {
@@ -1375,6 +1384,42 @@ struct mlx5_ifc_phys_layer_cntrs_bits {
        u8         reserved_at_640[0x180];
 };
 
+struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
+       u8         time_since_last_clear_high[0x20];
+
+       u8         time_since_last_clear_low[0x20];
+
+       u8         phy_received_bits_high[0x20];
+
+       u8         phy_received_bits_low[0x20];
+
+       u8         phy_symbol_errors_high[0x20];
+
+       u8         phy_symbol_errors_low[0x20];
+
+       u8         phy_corrected_bits_high[0x20];
+
+       u8         phy_corrected_bits_low[0x20];
+
+       u8         phy_corrected_bits_lane0_high[0x20];
+
+       u8         phy_corrected_bits_lane0_low[0x20];
+
+       u8         phy_corrected_bits_lane1_high[0x20];
+
+       u8         phy_corrected_bits_lane1_low[0x20];
+
+       u8         phy_corrected_bits_lane2_high[0x20];
+
+       u8         phy_corrected_bits_lane2_low[0x20];
+
+       u8         phy_corrected_bits_lane3_high[0x20];
+
+       u8         phy_corrected_bits_lane3_low[0x20];
+
+       u8         reserved_at_200[0x5c0];
+};
+
 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
        u8         symbol_error_counter[0x10];
 
@@ -2495,6 +2540,7 @@ enum {
        MLX5_MKC_ACCESS_MODE_PA    = 0x0,
        MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
        MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
+       MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
 };
 
 struct mlx5_ifc_mkc_bits {
@@ -2918,6 +2964,7 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
        struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
        struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
        struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
+       struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
        u8         reserved_at_0[0x7c0];
 };
 
@@ -3597,6 +3644,10 @@ struct mlx5_ifc_query_special_contexts_out_bits {
        u8         dump_fill_mkey[0x20];
 
        u8         resd_lkey[0x20];
+
+       u8         null_mkey[0x20];
+
+       u8         reserved_at_a0[0x60];
 };
 
 struct mlx5_ifc_query_special_contexts_in_bits {
@@ -4689,12 +4740,11 @@ struct mlx5_ifc_page_fault_resume_in_bits {
 
        u8         error[0x1];
        u8         reserved_at_41[0x4];
-       u8         rdma[0x1];
-       u8         read_write[0x1];
-       u8         req_res[0x1];
-       u8         qpn[0x18];
+       u8         page_fault_type[0x3];
+       u8         wq_number[0x18];
 
-       u8         reserved_at_60[0x20];
+       u8         reserved_at_60[0x8];
+       u8         token[0x18];
 };
 
 struct mlx5_ifc_nop_out_bits {
@@ -7469,6 +7519,63 @@ struct mlx5_ifc_peir_reg_bits {
        u8         error_type[0x8];
 };
 
+struct mlx5_ifc_pcam_enhanced_features_bits {
+       u8         reserved_at_0[0x7e];
+
+       u8         ppcnt_discard_group[0x1];
+       u8         ppcnt_statistical_group[0x1];
+};
+
+struct mlx5_ifc_pcam_reg_bits {
+       u8         reserved_at_0[0x8];
+       u8         feature_group[0x8];
+       u8         reserved_at_10[0x8];
+       u8         access_reg_group[0x8];
+
+       u8         reserved_at_20[0x20];
+
+       union {
+               u8         reserved_at_0[0x80];
+       } port_access_reg_cap_mask;
+
+       u8         reserved_at_c0[0x80];
+
+       union {
+               struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
+               u8         reserved_at_0[0x80];
+       } feature_cap_mask;
+
+       u8         reserved_at_1c0[0xc0];
+};
+
+struct mlx5_ifc_mcam_enhanced_features_bits {
+       u8         reserved_at_0[0x7f];
+
+       u8         pcie_performance_group[0x1];
+};
+
+struct mlx5_ifc_mcam_reg_bits {
+       u8         reserved_at_0[0x8];
+       u8         feature_group[0x8];
+       u8         reserved_at_10[0x8];
+       u8         access_reg_group[0x8];
+
+       u8         reserved_at_20[0x20];
+
+       union {
+               u8         reserved_at_0[0x80];
+       } mng_access_reg_cap_mask;
+
+       u8         reserved_at_c0[0x80];
+
+       union {
+               struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
+               u8         reserved_at_0[0x80];
+       } mng_feature_cap_mask;
+
+       u8         reserved_at_1c0[0x80];
+};
+
 struct mlx5_ifc_pcap_reg_bits {
        u8         reserved_at_0[0x8];
        u8         local_port[0x8];
@@ -7813,6 +7920,60 @@ struct mlx5_ifc_initial_seg_bits {
        u8         reserved_at_80a0[0x17fc0];
 };
 
+struct mlx5_ifc_mtpps_reg_bits {
+       u8         reserved_at_0[0xc];
+       u8         cap_number_of_pps_pins[0x4];
+       u8         reserved_at_10[0x4];
+       u8         cap_max_num_of_pps_in_pins[0x4];
+       u8         reserved_at_18[0x4];
+       u8         cap_max_num_of_pps_out_pins[0x4];
+
+       u8         reserved_at_20[0x24];
+       u8         cap_pin_3_mode[0x4];
+       u8         reserved_at_48[0x4];
+       u8         cap_pin_2_mode[0x4];
+       u8         reserved_at_50[0x4];
+       u8         cap_pin_1_mode[0x4];
+       u8         reserved_at_58[0x4];
+       u8         cap_pin_0_mode[0x4];
+
+       u8         reserved_at_60[0x4];
+       u8         cap_pin_7_mode[0x4];
+       u8         reserved_at_68[0x4];
+       u8         cap_pin_6_mode[0x4];
+       u8         reserved_at_70[0x4];
+       u8         cap_pin_5_mode[0x4];
+       u8         reserved_at_78[0x4];
+       u8         cap_pin_4_mode[0x4];
+
+       u8         reserved_at_80[0x80];
+
+       u8         enable[0x1];
+       u8         reserved_at_101[0xb];
+       u8         pattern[0x4];
+       u8         reserved_at_110[0x4];
+       u8         pin_mode[0x4];
+       u8         pin[0x8];
+
+       u8         reserved_at_120[0x20];
+
+       u8         time_stamp[0x40];
+
+       u8         out_pulse_duration[0x10];
+       u8         out_periodic_adjustment[0x10];
+
+       u8         reserved_at_1a0[0x60];
+};
+
+struct mlx5_ifc_mtppse_reg_bits {
+       u8         reserved_at_0[0x18];
+       u8         pin[0x8];
+       u8         event_arm[0x1];
+       u8         reserved_at_21[0x1b];
+       u8         event_generation_mode[0x4];
+       u8         reserved_at_40[0x40];
+};
+
 union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
        struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -7857,6 +8018,8 @@ union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
        struct mlx5_ifc_slrg_reg_bits slrg_reg;
        struct mlx5_ifc_sltp_reg_bits sltp_reg;
+       struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
+       struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
        u8         reserved_at_0[0x60e0];
 };
 
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