net/mlx5: Fix some spelling mistakes

[sfrench/cifs-2.6.git] / include / linux / mlx5 / mlx5_ifc.h

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index edafedb7b509010c904fccf2cdeffea1afa9317b..1fd1446624911bfa65d0f9139b6be7d8f9ba2e72 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -32,6 +32,8 @@
 #ifndef MLX5_IFC_H
 #define MLX5_IFC_H
 
+#include "mlx5_ifc_fpga.h"
+
 enum {
        MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
        MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
@@ -56,7 +58,8 @@ enum {
        MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
        MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
        MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
-       MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
+       MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
+       MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
 };
 
 enum {
@@ -658,9 +661,9 @@ enum {
 struct mlx5_ifc_atomic_caps_bits {
        u8         reserved_at_0[0x40];
 
-       u8         atomic_req_8B_endianess_mode[0x2];
+       u8         atomic_req_8B_endianness_mode[0x2];
        u8         reserved_at_42[0x4];
-       u8         supported_atomic_req_8B_endianess_mode_1[0x1];
+       u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 
        u8         reserved_at_47[0x19];
 
@@ -860,7 +863,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         max_tc[0x4];
        u8         reserved_at_1d0[0x1];
        u8         dcbx[0x1];
-       u8         reserved_at_1d2[0x4];
+       u8         reserved_at_1d2[0x3];
+       u8         fpga[0x1];
        u8         rol_s[0x1];
        u8         rol_g[0x1];
        u8         reserved_at_1d8[0x1];
@@ -2194,6 +2198,7 @@ union mlx5_ifc_hca_cap_union_bits {
        struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
        struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
        struct mlx5_ifc_qos_cap_bits qos_cap;
+       struct mlx5_ifc_fpga_cap_bits fpga_cap;
        u8         reserved_at_0[0x8000];
 };
 
@@ -6622,6 +6627,24 @@ struct mlx5_ifc_create_flow_table_out_bits {
        u8         reserved_at_60[0x20];
 };
 
+struct mlx5_ifc_flow_table_context_bits {
+       u8         encap_en[0x1];
+       u8         decap_en[0x1];
+       u8         reserved_at_2[0x2];
+       u8         table_miss_action[0x4];
+       u8         level[0x8];
+       u8         reserved_at_10[0x8];
+       u8         log_size[0x8];
+
+       u8         reserved_at_20[0x8];
+       u8         table_miss_id[0x18];
+
+       u8         reserved_at_40[0x8];
+       u8         lag_master_next_table_id[0x18];
+
+       u8         reserved_at_60[0xe0];
+};
+
 struct mlx5_ifc_create_flow_table_in_bits {
        u8         opcode[0x10];
        u8         reserved_at_10[0x10];
@@ -6640,21 +6663,7 @@ struct mlx5_ifc_create_flow_table_in_bits {
 
        u8         reserved_at_a0[0x20];
 
-       u8         encap_en[0x1];
-       u8         decap_en[0x1];
-       u8         reserved_at_c2[0x2];
-       u8         table_miss_mode[0x4];
-       u8         level[0x8];
-       u8         reserved_at_d0[0x8];
-       u8         log_size[0x8];
-
-       u8         reserved_at_e0[0x8];
-       u8         table_miss_id[0x18];
-
-       u8         reserved_at_100[0x8];
-       u8         lag_master_next_table_id[0x18];
-
-       u8         reserved_at_120[0x80];
+       struct mlx5_ifc_flow_table_context_bits flow_table_context;
 };
 
 struct mlx5_ifc_create_flow_group_out_bits {
@@ -7286,7 +7295,8 @@ struct mlx5_ifc_ptys_reg_bits {
        u8         ib_link_width_oper[0x10];
        u8         ib_proto_oper[0x10];
 
-       u8         reserved_at_160[0x20];
+       u8         reserved_at_160[0x1c];
+       u8         connector_type[0x4];
 
        u8         eth_proto_lp_advertise[0x20];
 
@@ -7689,8 +7699,10 @@ struct mlx5_ifc_peir_reg_bits {
 };
 
 struct mlx5_ifc_pcam_enhanced_features_bits {
-       u8         reserved_at_0[0x7e];
+       u8         reserved_at_0[0x7c];
 
+       u8         ptys_connector_type[0x1];
+       u8         reserved_at_7d[0x1];
        u8         ppcnt_discard_group[0x1];
        u8         ppcnt_statistical_group[0x1];
 };
@@ -8190,6 +8202,8 @@ union mlx5_ifc_ports_control_registers_document_bits {
        struct mlx5_ifc_sltp_reg_bits sltp_reg;
        struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
        struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
+       struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
+       struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
        u8         reserved_at_0[0x60e0];
 };
 
@@ -8270,17 +8284,7 @@ struct mlx5_ifc_modify_flow_table_in_bits {
        u8         reserved_at_a0[0x8];
        u8         table_id[0x18];
 
-       u8         reserved_at_c0[0x4];
-       u8         table_miss_mode[0x4];
-       u8         reserved_at_c8[0x18];
-
-       u8         reserved_at_e0[0x8];
-       u8         table_miss_id[0x18];
-
-       u8         reserved_at_100[0x8];
-       u8         lag_master_next_table_id[0x18];
-
-       u8         reserved_at_120[0x80];
+       struct mlx5_ifc_flow_table_context_bits flow_table_context;
 };
 
 struct mlx5_ifc_ets_tcn_config_reg_bits {