[POWERPC] Use 4kB iommu pages even on 64kB-page systems

[sfrench/cifs-2.6.git] / include / asm-powerpc / tce.h

diff --git a/include/asm-powerpc/tce.h b/include/asm-powerpc/tce.h
index d099d5200f9bbb7ffea65a29535300289c7d84b9..f663634cccc9c89b8d87164d98387cc61e97773a 100644 (file)
--- a/include/asm-powerpc/tce.h
+++ b/include/asm-powerpc/tce.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  * Rewrite, cleanup:
- * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
+ * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,6 +20,9 @@
 
 #ifndef _ASM_POWERPC_TCE_H
 #define _ASM_POWERPC_TCE_H
+#ifdef __KERNEL__
+
+#include <asm/iommu.h>
 
 /*
  * Tces come in two formats, one for the virtual bus and a different
@@ -32,33 +35,16 @@
 
 #define TCE_SHIFT      12
 #define TCE_PAGE_SIZE  (1 << TCE_SHIFT)
-#define TCE_PAGE_FACTOR        (PAGE_SHIFT - TCE_SHIFT)
-
 
-/* tce_entry
- * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
- * abstracted so layout is irrelevant.
- */
-union tce_entry {
-       unsigned long te_word;
-       struct {
-               unsigned int  tb_cacheBits :6;  /* Cache hash bits - not used */
-               unsigned int  tb_rsvd      :6;
-               unsigned long tb_rpn       :40; /* Real page number */
-               unsigned int  tb_valid     :1;  /* Tce is valid (vb only) */
-               unsigned int  tb_allio     :1;  /* Tce is valid for all lps (vb only) */
-               unsigned int  tb_lpindex   :8;  /* LpIndex for user of TCE (vb only) */
-               unsigned int  tb_pciwr     :1;  /* Write allowed (pci only) */
-               unsigned int  tb_rdwr      :1;  /* Read allowed  (pci), Write allowed (vb) */
-       } te_bits;
-#define te_cacheBits te_bits.tb_cacheBits
-#define te_rpn       te_bits.tb_rpn
-#define te_valid     te_bits.tb_valid
-#define te_allio     te_bits.tb_allio
-#define te_lpindex   te_bits.tb_lpindex
-#define te_pciwr     te_bits.tb_pciwr
-#define te_rdwr      te_bits.tb_rdwr
-};
+#define TCE_ENTRY_SIZE         8               /* each TCE is 64 bits */
 
+#define TCE_RPN_MASK           0xfffffffffful  /* 40-bit RPN (4K pages) */
+#define TCE_RPN_SHIFT          12
+#define TCE_VALID              0x800           /* TCE valid */
+#define TCE_ALLIO              0x400           /* TCE valid for all lpars */
+#define TCE_PCI_WRITE          0x2             /* write from PCI allowed */
+#define TCE_PCI_READ           0x1             /* read from PCI allowed */
+#define TCE_VB_WRITE           0x1             /* write from VB allowed */
 
+#endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_TCE_H */