m68knommu: fix 528x ColdFire cache settings

[sfrench/cifs-2.6.git] / include / asm-m68knommu / mcfcache.h

diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h
index b17cd920977f592c7a05f5fdae337039fb784a66..c042634fadaa0cecb2c83d0ea9e3feac3ecc91d5 100644 (file)
--- a/include/asm-m68knommu/mcfcache.h
+++ b/include/asm-m68knommu/mcfcache.h
@@ -11,7 +11,6 @@
 #define        __M68KNOMMU_MCFCACHE_H
 /****************************************************************************/
 
-#include <linux/config.h>
 
 /*
  *     The different ColdFire families have different cache arrangments.
@@ -61,7 +60,7 @@
        nop
        movel   #0x0000c020, %d0        /* Set SDRAM cached only */
        movec   %d0, %ACR0
-       movel   #0xff00c000, %d0        /* Cache Flash also */
+       movel   #0x00000000, %d0        /* No other regions cached */
        movec   %d0, %ACR1
        movel   #0x80000200, %d0        /* Setup cache mask */
        movec   %d0, %CACR              /* Enable cache */
@@ -93,6 +92,21 @@
 .endm
 #endif /* CONFIG_M5249 || CONFIG_M5307 */
 
+#if defined(CONFIG_M532x)
+.macro CACHE_ENABLE
+       movel   #0x01000000,%d0         /* invalidate cache cmd */
+       movec   %d0,%CACR               /* do invalidate cache */
+       nop
+       movel   #0x4001C000,%d0         /* set SDRAM cached (write-thru) */
+       movec   %d0,%ACR0
+       movel   #0x00000000,%d0         /* no other regions cached */
+       movec   %d0,%ACR1
+       movel   #0x80000200,%d0         /* setup cache mask */
+       movec   %d0,%CACR               /* enable cache */
+       nop
+.endm
+#endif /* CONFIG_M532x */
+
 #if defined(CONFIG_M5407)
 /*
  *     Version 4 cores have a true harvard style separate instruction
@@ -117,6 +131,20 @@
 .endm
 #endif /* CONFIG_M5407 */
 
+#if defined(CONFIG_M520x)
+.macro CACHE_ENABLE
+       move.l  #0x01000000,%d0         /* invalidate whole cache */
+       movec   %d0,%CACR
+       nop
+       move.l  #0x0000c000,%d0         /* set SDRAM cached (write-thru) */
+       movec   %d0,%ACR0
+       move.l  #0x00000000,%d0         /* no other regions cached */
+       movec   %d0,%ACR1
+       move.l  #0x80400000,%d0         /* enable 8K instruction cache */
+       movec   %d0,%CACR
+       nop
+.endm
+#endif /* CONFIG_M520x */
 
 /****************************************************************************/
 #endif /* __M68KNOMMU_MCFCACHE_H */