x86: x86 i387 cleanup

[sfrench/cifs-2.6.git] / include / asm-ia64 / spinlock.h

diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h
index 5b78611411c30e244a650b230aaae7c62ec5a6e9..0229fb95fb3824f657452dc4adbd1bd4e52c48e1 100644 (file)
--- a/include/asm-ia64/spinlock.h
+++ b/include/asm-ia64/spinlock.h
@@ -11,9 +11,9 @@
 
 #include <linux/compiler.h>
 #include <linux/kernel.h>
+#include <linux/bitops.h>
 
 #include <asm/atomic.h>
-#include <asm/bitops.h>
 #include <asm/intrinsics.h>
 #include <asm/system.h>
 
@@ -34,7 +34,7 @@ __raw_spin_lock_flags (raw_spinlock_t *lock, unsigned long flags)
 {
        register volatile unsigned int *ptr asm ("r31") = &lock->lock;
 
-#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
+#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
 # ifdef CONFIG_ITANIUM
        /* don't use brl on Itanium... */
        asm volatile ("{\n\t"
@@ -201,6 +201,20 @@ static inline void __raw_write_unlock(raw_rwlock_t *x)
 
 #endif /* !ASM_SUPPORTED */
 
-#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
+static inline int __raw_read_trylock(raw_rwlock_t *x)
+{
+       union {
+               raw_rwlock_t lock;
+               __u32 word;
+       } old, new;
+       old.lock = new.lock = *x;
+       old.lock.write_lock = new.lock.write_lock = 0;
+       ++new.lock.read_counter;
+       return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
+}
+
+#define _raw_spin_relax(lock)  cpu_relax()
+#define _raw_read_relax(lock)  cpu_relax()
+#define _raw_write_relax(lock) cpu_relax()
 
 #endif /*  _ASM_IA64_SPINLOCK_H */