Merge x86-64 update from Andi

[sfrench/cifs-2.6.git] / include / asm-i386 / processor.h

diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
index a0489b2227020208c541eafcf58478e45d528c7b..5c96cf6dcb3916f5735cdf6005b2ac7b3755cd4d 100644 (file)
--- a/include/asm-i386/processor.h
+++ b/include/asm-i386/processor.h
@@ -65,7 +65,9 @@ struct cpuinfo_x86 {
        int     f00f_bug;
        int     coma_bug;
        unsigned long loops_per_jiffy;
-       unsigned char x86_num_cores;
+       unsigned char x86_max_cores;    /* cpuid returned max cores value */
+       unsigned char booted_cores;     /* number of cores as seen by OS */
+       unsigned char apicid;
 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 
 #define X86_VENDOR_INTEL 0
@@ -455,6 +457,7 @@ struct thread_struct {
        unsigned int            saved_fs, saved_gs;
 /* IO permissions */
        unsigned long   *io_bitmap_ptr;
+       unsigned long   iopl;
 /* max allowed port in the bitmap, in bytes: */
        unsigned long   io_bitmap_max;
 };
@@ -475,7 +478,6 @@ struct thread_struct {
        .esp0           = sizeof(init_stack) + (long)&init_stack,       \
        .ss0            = __KERNEL_DS,                                  \
        .ss1            = __KERNEL_CS,                                  \
-       .ldt            = GDT_ENTRY_LDT,                                \
        .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,                     \
        .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 }
@@ -512,6 +514,21 @@ static inline void load_esp0(struct tss_struct *tss, struct thread_struct *threa
                        : /* no output */                       \
                        :"r" (value))
 
+/*
+ * Set IOPL bits in EFLAGS from given mask
+ */
+static inline void set_iopl_mask(unsigned mask)
+{
+       unsigned int reg;
+       __asm__ __volatile__ ("pushfl;"
+                             "popl %0;"
+                             "andl %1, %0;"
+                             "orl %2, %0;"
+                             "pushl %0;"
+                             "popfl"
+                               : "=&r" (reg)
+                               : "i" (~X86_EFLAGS_IOPL), "r" (mask));
+}
 
 /* Forward declaration, a strange C thing */
 struct task_struct;
@@ -664,7 +681,7 @@ static inline void rep_nop(void)
    However we don't do prefetches for pre XP Athlons currently
    That should be fixed. */
 #define ARCH_HAS_PREFETCH
-extern inline void prefetch(const void *x)
+static inline void prefetch(const void *x)
 {
        alternative_input(ASM_NOP4,
                          "prefetchnta (%1)",
@@ -678,7 +695,7 @@ extern inline void prefetch(const void *x)
 
 /* 3dnow! prefetch to get an exclusive cache line. Useful for 
    spinlocks to avoid one state transition in the cache coherency protocol. */
-extern inline void prefetchw(const void *x)
+static inline void prefetchw(const void *x)
 {
        alternative_input(ASM_NOP4,
                          "prefetchw (%1)",
@@ -703,4 +720,10 @@ extern void mtrr_bp_init(void);
 #define mtrr_bp_init() do {} while (0)
 #endif
 
+#ifdef CONFIG_X86_MCE
+extern void mcheck_init(struct cpuinfo_x86 *c);
+#else
+#define mcheck_init(c) do {} while(0)
+#endif
+
 #endif /* __ASM_I386_PROCESSOR_H */