spi: pxa2xx_spi clock polarity fix

[sfrench/cifs-2.6.git] / include / asm-arm / arch-pxa / regs-ssp.h

diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 991cb688db757ef2591a29d8bb9a1aabcd776dbf..0255328c3c18814d0ed94762c39c9162cca153e7 100644 (file)
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -85,6 +85,7 @@
 #define SSCR1_RSRE             (1 << 20)       /* Receive Service Request Enable */
 #define SSCR1_TINTE            (1 << 19)       /* Receiver Time-out Interrupt enable */
 #define SSCR1_PINTE            (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
+#define SSCR1_IFS              (1 << 16)       /* Invert Frame Signal */
 #define SSCR1_STRF             (1 << 15)       /* Select FIFO or EFWR */
 #define SSCR1_EFWR             (1 << 14)       /* Enable FIFO Write/Read */