atyfb: increase SPLL delay
[sfrench/cifs-2.6.git] / drivers / video / aty / mach64_ct.c
index 1fdcfdbf669b2a26f770af8d4b5816479f8f6f86..cc9e9779b75f753fd9f937d845ca7a5cd7b415a8 100644 (file)
@@ -608,12 +608,10 @@ static void aty_resume_pll_ct(const struct fb_info *info,
                aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
                aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
                /*
                aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
                aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
                /*
-                * The sclk has been started. However, I believe the first clock
-                * ticks it generates are not very stable. Hope this primitive loop
-                * helps for Rage Mobilities that sometimes crash when
-                * we switch to sclk. (Daniel Mantione, 13-05-2003)
+                * SCLK has been started. Wait for the PLL to lock. 5 ms
+                * should be enough according to mach64 programmer's guide.
                 */
                 */
-               udelay(500);
+               mdelay(5);
        }
 
        aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
        }
 
        aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);