spi: pxa2xx_spi clock polarity fix

[sfrench/cifs-2.6.git] / drivers / spi / pxa2xx_spi.c

diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index 365e0e355aea302e684451592d9315862f565275..59deed79e0ab9e9da5db9781a869ca4c90b9f1ff 100644 (file)
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -51,13 +51,19 @@ MODULE_LICENSE("GPL");
 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
 
-/* for testing SSCR1 changes that require SSP restart, basically
- * everything except the service and interrupt enables */
-#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
+/*
+ * for testing SSCR1 changes that require SSP restart, basically
+ * everything except the service and interrupt enables, the pxa270 developer
+ * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
+ * list, but the PXA255 dev man says all bits without really meaning the
+ * service and interrupt enables
+ */
+#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
                                | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
-                               | SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
-                               | SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \
-                               | SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
+                               | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
+                               | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
+                               | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
+                               | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
 
 #define DEFINE_SSP_REG(reg, off) \
 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
@@ -973,9 +979,6 @@ static void pump_transfers(unsigned long data)
                if (drv_data->ssp_type == PXA25x_SSP)
                        DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
 
-               /* Fix me, need to handle cs polarity */
-               drv_data->cs_control(PXA2XX_CS_ASSERT);
-
                /* Clear status and start DMA engine */
                cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
                write_SSSR(drv_data->clear_sr, reg);
@@ -985,9 +988,6 @@ static void pump_transfers(unsigned long data)
                /* Ensure we have the correct interrupt handler */
                drv_data->transfer_handler = interrupt_transfer;
 
-               /* Fix me, need to handle cs polarity */
-               drv_data->cs_control(PXA2XX_CS_ASSERT);
-
                /* Clear status  */
                cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
                write_SSSR(drv_data->clear_sr, reg);
@@ -998,16 +998,29 @@ static void pump_transfers(unsigned long data)
                || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
                        (cr1 & SSCR1_CHANGE_MASK)) {
 
+               /* stop the SSP, and update the other bits */
                write_SSCR0(cr0 & ~SSCR0_SSE, reg);
                if (drv_data->ssp_type != PXA25x_SSP)
                        write_SSTO(chip->timeout, reg);
-               write_SSCR1(cr1, reg);
+               /* first set CR1 without interrupt and service enables */
+               write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
+               /* restart the SSP */
                write_SSCR0(cr0, reg);
+
        } else {
                if (drv_data->ssp_type != PXA25x_SSP)
                        write_SSTO(chip->timeout, reg);
-               write_SSCR1(cr1, reg);
        }
+
+       /* FIXME, need to handle cs polarity,
+        * this driver uses struct pxa2xx_spi_chip.cs_control to
+        * specify a CS handling function, and it ignores most
+        * struct spi_device.mode[s], including SPI_CS_HIGH */
+       drv_data->cs_control(PXA2XX_CS_ASSERT);
+
+       /* after chip select, release the data by enabling service
+        * requests and interrupts, without changing any mode bits */
+       write_SSCR1(cr1, reg);
 }
 
 static void pump_messages(struct work_struct *work)