phy: qcom-qmp: Add msm8998 PCIe QMP PHY support

[sfrench/cifs-2.6.git] / drivers / phy / qualcomm / phy-qcom-qmp.h

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index a1b6cdee9a089ca711dea70a8f6ed9e8cf8d959f..335ea5d7ef4002743e372c39c09a17d2a7f63afc 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -241,6 +241,7 @@
 #define QSERDES_V3_RX_RX_BAND                          0x110
 #define QSERDES_V3_RX_RX_INTERFACE_MODE                        0x11c
 #define QSERDES_V3_RX_RX_MODE_00                       0x164
+#define QSERDES_V3_RX_RX_MODE_01                       0x168
 
 /* Only for QMP V3 PHY - PCS registers */
 #define QPHY_V3_PCS_POWER_DOWN_CONTROL                 0x004
@@ -280,6 +281,7 @@
 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME                   0x08c
 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK                0x0a0
 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK          0x0a4
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME              0x0a8
 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK            0x0b0
 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME             0x0b8
 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME              0x0bc
@@ -292,13 +294,23 @@
 #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME                        0x138
 #define QPHY_V3_PCS_RX_SIGDET_CTRL1                    0x13c
 #define QPHY_V3_PCS_RX_SIGDET_CTRL2                    0x140
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB      0x1a8
+#define QPHY_V3_PCS_OSC_DTCT_ACTIONS                   0x1ac
+#define QPHY_V3_PCS_SIGDET_CNTRL                       0x1b0
 #define QPHY_V3_PCS_TX_MID_TERM_CTRL1                  0x1bc
 #define QPHY_V3_PCS_MULTI_LANE_CTRL1                   0x1c4
 #define QPHY_V3_PCS_RX_SIGDET_LVL                      0x1d8
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB    0x1dc
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB    0x1e0
 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1                 0x20c
 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2                 0x210
 
 /* Only for QMP V3 PHY - PCS_MISC registers */
 #define QPHY_V3_PCS_MISC_CLAMP_ENABLE                  0x0c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2              0x2c
+#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1      0x44
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2                0x54
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4                0x5c
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5                0x60
 
 #endif