Merge tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

[sfrench/cifs-2.6.git] / drivers / pci / controller / pcie-mediatek.c

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 55e471c18e8d84fd9f49a0b8dd57468f6155ee36..0b6c72804e03b77816c7bef286d7e350651c38d4 100644 (file)
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -90,6 +90,12 @@
 #define AHB2PCIE_SIZE(x)       ((x) & GENMASK(4, 0))
 #define PCIE_AXI_WINDOW0       0x448
 #define WIN_ENABLE             BIT(7)
+/*
+ * Define PCIe to AHB window size as 2^33 to support max 8GB address space
+ * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
+ * start from 0x40000000).
+ */
+#define PCIE2AHB_SIZE  0x21
 
 /* PCIe V2 configuration transaction header */
 #define PCIE_CFG_HEADER0       0x460
@@ -654,7 +660,6 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
        struct resource *mem = &pcie->mem;
        const struct mtk_pcie_soc *soc = port->pcie->soc;
        u32 val;
-       size_t size;
        int err;
 
        /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
@@ -706,15 +711,15 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
                mtk_pcie_enable_msi(port);
 
        /* Set AHB to PCIe translation windows */
-       size = mem->end - mem->start;
-       val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
+       val = lower_32_bits(mem->start) |
+             AHB2PCIE_SIZE(fls(resource_size(mem)));
        writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
 
        val = upper_32_bits(mem->start);
        writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
 
        /* Set PCIe to AXI translation memory space.*/
-       val = fls(0xffffffff) | WIN_ENABLE;
+       val = PCIE2AHB_SIZE | WIN_ENABLE;
        writel(val, port->base + PCIE_AXI_WINDOW0);
 
        return 0;