ntb: Adding split BAR support for Haswell platforms

[sfrench/cifs-2.6.git] / drivers / ntb / ntb_regs.h

diff --git a/drivers/ntb/ntb_regs.h b/drivers/ntb/ntb_regs.h
index 9774506419d75ba1a5dc08a5f0e4d52e90d33ad7..f028ff81fd774b0d8901665bb7f43abbb5c234d7 100644 (file)
--- a/drivers/ntb/ntb_regs.h
+++ b/drivers/ntb/ntb_regs.h
@@ -57,34 +57,43 @@
 #define SNB_MAX_DB_BITS                15
 #define SNB_LINK_DB            15
 #define SNB_DB_BITS_PER_VEC    5
+#define HSX_SPLITBAR_MAX_MW    3
 #define SNB_MAX_MW             2
 #define SNB_ERRATA_MAX_MW      1
 
 #define SNB_DB_HW_LINK         0x8000
 
+#define SNB_UNCERRSTS_OFFSET   0x014C
+#define SNB_CORERRSTS_OFFSET   0x0158
+#define SNB_LINK_STATUS_OFFSET 0x01A2
 #define SNB_PCICMD_OFFSET      0x0504
 #define SNB_DEVCTRL_OFFSET     0x0598
+#define SNB_DEVSTS_OFFSET      0x059A
 #define SNB_SLINK_STATUS_OFFSET        0x05A2
-#define SNB_LINK_STATUS_OFFSET 0x01A2
 
 #define SNB_PBAR2LMT_OFFSET    0x0000
 #define SNB_PBAR4LMT_OFFSET    0x0008
+#define SNB_PBAR5LMT_OFFSET    0x000C
 #define SNB_PBAR2XLAT_OFFSET   0x0010
 #define SNB_PBAR4XLAT_OFFSET   0x0018
+#define SNB_PBAR5XLAT_OFFSET   0x001C
 #define SNB_SBAR2LMT_OFFSET    0x0020
 #define SNB_SBAR4LMT_OFFSET    0x0028
+#define SNB_SBAR5LMT_OFFSET    0x002C
 #define SNB_SBAR2XLAT_OFFSET   0x0030
 #define SNB_SBAR4XLAT_OFFSET   0x0038
+#define SNB_SBAR5XLAT_OFFSET   0x003C
 #define SNB_SBAR0BASE_OFFSET   0x0040
 #define SNB_SBAR2BASE_OFFSET   0x0048
 #define SNB_SBAR4BASE_OFFSET   0x0050
+#define SNB_SBAR5BASE_OFFSET   0x0054
 #define SNB_NTBCNTL_OFFSET     0x0058
 #define SNB_SBDF_OFFSET                0x005C
 #define SNB_PDOORBELL_OFFSET   0x0060
 #define SNB_PDBMSK_OFFSET      0x0062
 #define SNB_SDOORBELL_OFFSET   0x0064
 #define SNB_SDBMSK_OFFSET      0x0066
-#define SNB_USMEMMISS          0x0070
+#define SNB_USMEMMISS_OFFSET   0x0070
 #define SNB_SPAD_OFFSET                0x0080
 #define SNB_SPADSEMA4_OFFSET   0x00c0
 #define SNB_WCCNTRL_OFFSET     0x00e0
@@ -93,12 +102,18 @@
 #define SNB_B2B_XLAT_OFFSETL   0x0144
 #define SNB_B2B_XLAT_OFFSETU   0x0148
 
-#define SNB_MBAR01_USD_ADDR    0x000000210000000CULL
-#define SNB_MBAR23_USD_ADDR    0x000000410000000CULL
-#define SNB_MBAR45_USD_ADDR    0x000000810000000CULL
-#define SNB_MBAR01_DSD_ADDR    0x000000200000000CULL
-#define SNB_MBAR23_DSD_ADDR    0x000000400000000CULL
-#define SNB_MBAR45_DSD_ADDR    0x000000800000000CULL
+/*
+ * The addresses are setup so the 32bit BARs can function. Thus
+ * the addresses are all in 32bit space
+ */
+#define SNB_MBAR01_USD_ADDR    0x000000002100000CULL
+#define SNB_MBAR23_USD_ADDR    0x000000004100000CULL
+#define SNB_MBAR4_USD_ADDR     0x000000008100000CULL
+#define SNB_MBAR5_USD_ADDR     0x00000000A100000CULL
+#define SNB_MBAR01_DSD_ADDR    0x000000002000000CULL
+#define SNB_MBAR23_DSD_ADDR    0x000000004000000CULL
+#define SNB_MBAR4_DSD_ADDR     0x000000008000000CULL
+#define SNB_MBAR5_DSD_ADDR     0x00000000A000000CULL
 
 #define BWD_MSIX_CNT           34
 #define BWD_MAX_SPADS          16
@@ -147,13 +162,16 @@
 #define NTB_CNTL_LINK_DISABLE          (1 << 1)
 #define NTB_CNTL_S2P_BAR23_SNOOP       (1 << 2)
 #define NTB_CNTL_P2S_BAR23_SNOOP       (1 << 4)
-#define NTB_CNTL_S2P_BAR45_SNOOP       (1 << 6)
-#define NTB_CNTL_P2S_BAR45_SNOOP       (1 << 8)
+#define NTB_CNTL_S2P_BAR4_SNOOP        (1 << 6)
+#define NTB_CNTL_P2S_BAR4_SNOOP        (1 << 8)
+#define NTB_CNTL_S2P_BAR5_SNOOP        (1 << 12)
+#define NTB_CNTL_P2S_BAR5_SNOOP        (1 << 14)
 #define BWD_CNTL_LINK_DOWN             (1 << 16)
 
 #define NTB_PPD_OFFSET         0x00D4
 #define SNB_PPD_CONN_TYPE      0x0003
 #define SNB_PPD_DEV_TYPE       0x0010
+#define SNB_PPD_SPLIT_BAR      (1 << 6)
 #define BWD_PPD_INIT_LINK      0x0008
 #define BWD_PPD_CONN_TYPE      0x0300
 #define BWD_PPD_DEV_TYPE       0x1000