net/mlx5: Implement PCAM, MCAM access register commands

[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / port.c

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c
index d2ec9d232a70727df71d0c733f60c78a55415392..969e352435ee96276c77c3e260872a2b14e1ccf0 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/port.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c
@@ -74,6 +74,30 @@ out:
 }
 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
 
+int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
+                       u8 access_reg_group)
+{
+       u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
+       int sz = MLX5_ST_SZ_BYTES(pcam_reg);
+
+       MLX5_SET(pcam_reg, in, feature_group, feature_group);
+       MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
+
+       return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
+}
+
+int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
+                       u8 access_reg_group)
+{
+       u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
+       int sz = MLX5_ST_SZ_BYTES(mcam_reg);
+
+       MLX5_SET(mcam_reg, in, feature_group, feature_group);
+       MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
+
+       return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
+}
+
 struct mlx5_reg_pcap {
        u8                      rsvd0;
        u8                      port_num;
@@ -866,3 +890,51 @@ void mlx5_port_module_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe)
                               module_num, mlx5_pme_status[module_status - 1],
                               mlx5_pme_error[error_type]);
 }
+
+int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
+{
+       u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
+
+       return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
+                                   mtpps_size, MLX5_REG_MTPPS, 0, 0);
+}
+
+int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
+{
+       u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
+
+       return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
+                                   sizeof(out), MLX5_REG_MTPPS, 0, 1);
+}
+
+int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
+{
+       u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
+       u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
+       int err = 0;
+
+       MLX5_SET(mtppse_reg, in, pin, pin);
+
+       err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
+                                  sizeof(out), MLX5_REG_MTPPSE, 0, 0);
+       if (err)
+               return err;
+
+       *arm = MLX5_GET(mtppse_reg, in, event_arm);
+       *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
+
+       return err;
+}
+
+int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
+{
+       u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
+       u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
+
+       MLX5_SET(mtppse_reg, in, pin, pin);
+       MLX5_SET(mtppse_reg, in, event_arm, arm);
+       MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
+
+       return mlx5_core_access_reg(mdev, in, sizeof(in), out,
+                                   sizeof(out), MLX5_REG_MTPPSE, 0, 1);
+}