net/mlx5: Update eqe_type_str() event names

[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / eq.c

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
index 33eae5ad2fb09efe302e2b892c3c9e30d4b117f5..23048247d8278a42b3f743a59e7b21dbf28e0a25 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@ -35,6 +35,7 @@
 #include <linux/mlx5/driver.h>
 #include <linux/mlx5/cmd.h>
 #include "mlx5_core.h"
+#include "fpga/core.h"
 #ifdef CONFIG_MLX5_CORE_EN
 #include "eswitch.h"
 #endif
@@ -156,6 +157,10 @@ static const char *eqe_type_str(u8 type)
                return "MLX5_EVENT_TYPE_PAGE_FAULT";
        case MLX5_EVENT_TYPE_PPS_EVENT:
                return "MLX5_EVENT_TYPE_PPS_EVENT";
+       case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
+               return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
+       case MLX5_EVENT_TYPE_FPGA_ERROR:
+               return "MLX5_EVENT_TYPE_FPGA_ERROR";
        default:
                return "Unrecognized event";
        }
@@ -476,6 +481,11 @@ static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
                        if (dev->event)
                                dev->event(dev, MLX5_DEV_EVENT_PPS, (unsigned long)eqe);
                        break;
+
+               case MLX5_EVENT_TYPE_FPGA_ERROR:
+                       mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
+                       break;
+
                default:
                        mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
                                       eqe->type, eq->eqn);
@@ -548,7 +558,7 @@ int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
        inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
                MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
 
-       in = mlx5_vzalloc(inlen);
+       in = kvzalloc(inlen, GFP_KERNEL);
        if (!in) {
                err = -ENOMEM;
                goto err_buf;
@@ -693,6 +703,9 @@ int mlx5_start_eqs(struct mlx5_core_dev *dev)
        if (MLX5_CAP_GEN(dev, pps))
                async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
 
+       if (MLX5_CAP_GEN(dev, fpga))
+               async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
+
        err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
                                 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
                                 "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);