net/mlx5e: Add a counter for congested UMRs

[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.h

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
index 643153bb360722375c822f7f530e670c31c7f736..4e54cb86fecedc86ee0f1e6ecd8369c1d2e0caa3 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
@@ -70,6 +70,7 @@ struct mlx5e_sw_stats {
        u64 rx_csum_unnecessary_inner;
        u64 rx_xdp_drop;
        u64 rx_xdp_tx;
+       u64 rx_xdp_tx_cqe;
        u64 rx_xdp_tx_full;
        u64 tx_csum_none;
        u64 tx_csum_partial;
@@ -78,7 +79,9 @@ struct mlx5e_sw_stats {
        u64 tx_queue_dropped;
        u64 tx_xmit_more;
        u64 tx_recover;
+       u64 tx_cqes;
        u64 tx_queue_wake;
+       u64 tx_udp_seg_rem;
        u64 tx_cqe_err;
        u64 rx_wqe_err;
        u64 rx_mpwqe_filler;
@@ -91,6 +94,10 @@ struct mlx5e_sw_stats {
        u64 rx_cache_empty;
        u64 rx_cache_busy;
        u64 rx_cache_waive;
+       u64 rx_congst_umr;
+       u64 ch_poll;
+       u64 ch_arm;
+       u64 ch_aff_change;
        u64 ch_eq_rearm;
 
 #ifdef CONFIG_MLX5_EN_TLS
@@ -169,6 +176,7 @@ struct mlx5e_rq_stats {
        u64 removed_vlan_packets;
        u64 xdp_drop;
        u64 xdp_tx;
+       u64 xdp_tx_cqe;
        u64 xdp_tx_full;
        u64 wqe_err;
        u64 mpwqe_filler;
@@ -181,6 +189,7 @@ struct mlx5e_rq_stats {
        u64 cache_empty;
        u64 cache_busy;
        u64 cache_waive;
+       u64 congst_umr;
 };
 
 struct mlx5e_sq_stats {
@@ -196,6 +205,7 @@ struct mlx5e_sq_stats {
        u64 csum_partial_inner;
        u64 added_vlan_packets;
        u64 nop;
+       u64 udp_seg_rem;
 #ifdef CONFIG_MLX5_EN_TLS
        u64 tls_ooo;
        u64 tls_resync_bytes;
@@ -206,11 +216,15 @@ struct mlx5e_sq_stats {
        u64 dropped;
        u64 recover;
        /* dirtied @completion */
-       u64 wake ____cacheline_aligned_in_smp;
+       u64 cqes ____cacheline_aligned_in_smp;
+       u64 wake;
        u64 cqe_err;
 };
 
 struct mlx5e_ch_stats {
+       u64 poll;
+       u64 arm;
+       u64 aff_change;
        u64 eq_rearm;
 };