net/mlx5e: Properly indent within conditional statements

[sfrench/cifs-2.6.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
index 917fade5f5d55aa1a89c5abaadf73d9e5f37d612..1f3d87e2861801961f08969cf9db357ffafd3a6c 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
@@ -176,7 +176,6 @@ static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
 
 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
 {
-
        switch (sset) {
        case ETH_SS_STATS:
                return NUM_SW_COUNTERS +
@@ -242,10 +241,22 @@ static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
                strcpy(data + (idx++) * ETH_GSTRING_LEN,
                       pport_phy_statistical_stats_desc[i].format);
 
+       for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS(priv); i++)
+               strcpy(data + (idx++) * ETH_GSTRING_LEN,
+                      pport_eth_ext_stats_desc[i].format);
+
        for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
                strcpy(data + (idx++) * ETH_GSTRING_LEN,
                       pcie_perf_stats_desc[i].format);
 
+       for (i = 0; i < NUM_PCIE_PERF_COUNTERS64(priv); i++)
+               strcpy(data + (idx++) * ETH_GSTRING_LEN,
+                      pcie_perf_stats_desc64[i].format);
+
+       for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
+        strcpy(data + (idx++) * ETH_GSTRING_LEN,
+               pcie_perf_stall_stats_desc[i].format);
+
        for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
                for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
                        sprintf(data + (idx++) * ETH_GSTRING_LEN,
@@ -373,10 +384,22 @@ void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
                data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
                                                  pport_phy_statistical_stats_desc, i);
 
+       for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS(priv); i++)
+               data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
+                                                 pport_eth_ext_stats_desc, i);
+
        for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
                data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
                                                  pcie_perf_stats_desc, i);
 
+       for (i = 0; i < NUM_PCIE_PERF_COUNTERS64(priv); i++)
+               data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
+                                                 pcie_perf_stats_desc64, i);
+
+       for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
+               data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
+                                                 pcie_perf_stall_stats_desc, i);
+
        for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
                for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
                        data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
@@ -964,24 +987,27 @@ static u8 get_connector_port(u32 eth_proto, u8 connector_type)
        if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
                return ptys2connector_type[connector_type];
 
-       if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
-                        | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
-                        | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
-                        | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
-                       return PORT_FIBRE;
+       if (eth_proto &
+           (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)   |
+            MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)  |
+            MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
+            MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
+               return PORT_FIBRE;
        }
 
-       if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
-                        | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
-                        | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
-                       return PORT_DA;
+       if (eth_proto &
+           (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
+            MLX5E_PROT_MASK(MLX5E_10GBASE_CR)  |
+            MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
+               return PORT_DA;
        }
 
-       if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
-                        | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
-                        | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
-                        | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
-                       return PORT_NONE;
+       if (eth_proto &
+           (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
+            MLX5E_PROT_MASK(MLX5E_10GBASE_KR)  |
+            MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
+            MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
+               return PORT_NONE;
        }
 
        return PORT_OTHER;